CN107968757B - Demodulation method and system for frequency shift keying modulation signal - Google Patents
Demodulation method and system for frequency shift keying modulation signal Download PDFInfo
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
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Abstract
A demodulation method and a system of frequency shift keying modulation signals relate to the field of frequency shift keying modulation and demodulation. Processing data sent by an external radio frequency system to obtain two paths of I/Q data of intermediate frequency and removing direct current offset; then, carrying out zero intermediate frequency treatment by a numerical control oscillator; limiting out-of-band noise of the zero intermediate frequency I/Q data through low-pass filtering, and converting the I/Q data into phase data after time phase conversion; limiting out-of-band noise of the phase data through low-pass filtering, and generating a bit code stream after differential subtraction and judgment operation; comparing the generated bit code stream with the address code, and outputting frame synchronization pulses when the error number of the comparison result is less than the preset maximum number; after the generated bit code stream is subjected to frequency offset calculation, outputting a frequency offset code; and demodulating the output frequency offset code, outputting a final demodulation result bit code stream and simultaneously performing clock synchronization processing. The invention is suitable for frequency shift keying modulation and demodulation.
Description
Technical Field
The present invention relates to the field of frequency shift keying modulation and demodulation.
Background
Different modem technologies have different energy utilization efficiencies to accommodate different application environments. Short-range wireless communication generally employs a simple and efficient modulation and demodulation scheme, including ASK (amplitude shift keying), PSK (phase shift keying), FSK (frequency shift keying), and the like, because of short communication distance, low cost, low complexity, and low power consumption. In the conventional modulation and demodulation technology, at the moment of data change, carrier phase changes suddenly, so that a spectrum of a modulated signal has a large side lobe outside a main lobe, and interference on an adjacent channel is formed. Although the use of the re-band filter can filter out the side lobes other than the main lobe without affecting the transmission of information, the constant envelope characteristic of the modulated signal is impaired. Non-constant envelope signals require high linearity and can only be amplified using amplifiers with lower power efficiency but better linearity. The FSK modulation and demodulation mode is improved to obtain a GFSK modulation and demodulation mode (Gaussian frequency shift keying), the continuous phase at the original code alternation position can be realized, the mode can be adopted to concentrate the signal energy on the main lobe, and the method is an efficient modulation and demodulation mode.
The traditional scheme requires low complexity and good receiving performance in a white gaussian noise channel, and a demodulation function is usually realized by adopting a direct phase discrimination mode. Direct phase discrimination is a demodulation that uses the phase of a signal without using the amplitude of the signal. After the received signal is subjected to orthogonal down-conversion, the phase of the signal is solved, and then the division operation is carried out to recover the baseband signal after passing through the Gaussian filter.
The existing frequency shift keying demodulation method is shown in fig. 1, and the method has the following defects:
1. the frame synchronization is generated by an external circuit, the realization process is very complex, the support of the external circuit is needed, and the frame synchronization algorithm can cause the problem of high retransmission rate;
2. the frequency compensation circuit is in a feedback-free form, so that the real-time performance of compensation is poor, and the error rate is influenced;
3. the time sequence compensation algorithm is complex to realize, and meanwhile, bit information is extracted from the zero crossing point of the baseband signal, so that the time sequence compensation algorithm is greatly influenced by noise under the condition of low signal-to-noise ratio.
Disclosure of Invention
The invention provides a demodulation method and a demodulation system for frequency shift keying modulation signals, and aims to solve the problem that in the field of short-distance wireless communication application, on the premise that the transmitting power is low, various data transmission rates and modulation indexes are compatible, and error correction coding and error rate are not applicable, the difficulty in improving the sensitivity of a receiver is high.
The technical scheme for solving the technical problems is as follows:
a method of demodulating a frequency shift keying modulated signal, the method comprising:
s1, processing data sent by an external radio frequency system to obtain two paths of I/Q data of intermediate frequency, and performing down-conversion processing and frequency offset compensation on the I/Q data subjected to direct current elimination processing through a numerically controlled oscillator to enable the I/Q data to reach zero intermediate frequency;
s2, converting the zero intermediate frequency I/Q data into phase data, and generating bit code stream after differential subtraction and decision operation;
s3, comparing the generated bit code stream with the address code, and outputting frame synchronization pulse when the error number of the comparison result is less than the preset maximum number;
and S4, after the generated bit code stream is subjected to frequency offset calculation, outputting a frequency offset code, demodulating the frequency offset code, outputting a final demodulation result bit code stream, and simultaneously performing clock synchronization processing.
The invention has the beneficial effects that: the invention provides a simple and more accurate frequency shift keying demodulation method aiming at the problems of high implementation difficulty, dependence on an external frame synchronization circuit and higher error rate of the conventional short-distance wireless communication frequency shift keying demodulation technology.
On the basis of the technical scheme, the invention can be further improved as follows.
Further, the process of performing the frequency offset compensation process on the I/Q data after the dc cancellation process in S1 is as follows:
s11, carrying out Gaussian modulation on the received I/Q data to obtain data A with the length of M bit;
s12, decoding the data A to obtain data B, subtracting the data B and the data A to obtain a frequency offset control word and sending the frequency offset control word to the numerically controlled oscillator;
and S13, adjusting the output frequency of the numerical control oscillator according to the frequency control word.
The beneficial effect of adopting the further scheme is that: the received intermediate frequency can be consistent with the intermediate frequency generated by the numerical control oscillator through the processing process, zero intermediate frequency conversion of the received data is guaranteed, the received data is used for subsequent demodulation, the traditional demodulation mode is adopted, frequency compensation is not carried out in the process, the data is compensated before data judgment, errors can be accumulated to the judged position due to the fact that the zero intermediate frequency conversion of the received data cannot be guaranteed, the sensitivity is reduced, and the error rate is increased.
Further, the bit code stream data generated in S2 includes a J bit preamble, a K bit address code, and I bit load data.
Further, the process of obtaining the frame synchronization pulse in S3 is:
s31, accumulating the received bit code stream data for J times of leading data, and solving the average value of the accumulated values as a reference value;
s32, comparing the address code data in the received bit code stream data with a reference value, wherein if the address code data is greater than the reference value, the address code to be compared is 1, and if the address code data is less than the reference value, the address code to be compared is 0;
s33, after comparing the address code data in the bit code stream data with the reference value and generating the address code to be compared each time, comparing the address code to be compared with the preset address code, if equal, adding 1 to the counter, and if not, keeping the current numerical value unchanged by the counter;
and S34, when the comparison times are K times, if the value obtained by subtracting the configuration threshold value from K is smaller than the value of the counter, completing synchronization and sending out a frame synchronization pulse, and if the value obtained by subtracting the configuration threshold value from K is larger than the value of the counter, entering a retransmission process.
The beneficial effect of adopting the further scheme is that: the traditional technology firstly does not introduce a reference value concept, directly compares received data with a preset address code, and actually the received address code and the preset address code are not equal in large area due to the influence of factors such as system gain adjustment or direct current elimination in the comparison process.
Further, the process that the frequency offset code output in S4 outputs the final demodulation result bit code stream after demodulation and performs clock synchronization processing at the same time is as follows:
s41, decoding the received frequency offset code to obtain 1bit load data;
s42, automatically recovering the clock frequency according to the demodulation signal and the sampling frequency, comparing the clock frequency with the load data, and then adjusting the clock period, wherein when the clock frequency is ahead of the load data, the clock period is increased; when the clock frequency lags behind the load data, the clock period is reduced automatically, and finally a recovered clock signal is obtained;
s43, according to the recovered clock signal, encoding the load data obtained after decoding to obtain encoded data;
and S44, comparing the coded data with externally input demodulation data to obtain a crystal oscillator frequency, and using the crystal oscillator frequency as a reference point of the decoding demodulation data.
The beneficial effect of adopting the further scheme is that: the method adopts an internal self-generated clock to ensure the consistency of the decoded data and the clock, and obtains the crystal oscillator frequency of the crystal by recovering the internal part of the clock to carry out frequency shift keying modulation, and feeds the crystal oscillator frequency back to a decoding end to carry out input data decoding, thereby improving the decoding accuracy.
In order to solve the above technical problem, the present invention further provides a demodulation system for frequency shift keying modulated signals, the system comprising:
the processing module is used for processing data sent by an external radio frequency system to obtain two paths of I/Q data of intermediate frequency; performing down-conversion processing and frequency offset compensation on the I/Q data subjected to the direct current elimination processing through a numerically controlled oscillator to enable an I/Q signal to reach zero intermediate frequency;
the conversion module is used for limiting out-of-band noise of the zero intermediate frequency I/Q data through low-pass filtering, converting the data into phase data after time phase conversion, and generating a bit code stream after differential subtraction and judgment operation;
the output module is used for comparing the generated bit code stream with the address code and outputting frame synchronization pulse when the error number of the comparison result is less than the preset maximum number;
and the synchronization module is used for outputting the frequency offset code after the generated bit code stream is subjected to frequency offset calculation, outputting the final demodulation result bit code stream after demodulation and simultaneously performing clock synchronization processing.
The invention has the beneficial effects that: the invention provides a simple and more accurate frequency shift keying demodulation system aiming at the problems of high implementation difficulty, dependence on an external frame synchronization circuit and higher error rate of the conventional short-distance wireless communication frequency shift keying demodulation system.
Further, the processing module includes:
the Gaussian modulation module is used for carrying out Gaussian modulation on the received I/Q data to obtain data A with the length of M bit;
the decoding comparison module is used for decoding the data A to obtain data B, carrying out subtraction operation on the data B and the data A to obtain a frequency offset control word and sending the frequency offset control word to the numerically controlled oscillator;
and the frequency control module is used for adjusting the output frequency of the numerical control oscillator according to the frequency control word.
The beneficial effect of adopting the further scheme is that: the received intermediate frequency can be consistent with the intermediate frequency generated by the numerical control oscillator through the processing process, zero intermediate frequency conversion of the received data is guaranteed, the received data is used for subsequent demodulation, the traditional demodulation mode is adopted, frequency compensation is not carried out in the process, the data is compensated before data judgment, errors can be accumulated to the judged position due to the fact that the zero intermediate frequency conversion of the received data cannot be guaranteed, the sensitivity is reduced, and the error rate is increased.
Further, the bit code stream data generated in the conversion module includes a J bit preamble, a K bit address code and an I bit load data.
Further, the output module includes:
the reference value calculation module is used for accumulating the received bit code stream data for J times of leading data and solving the average value of the accumulated values as a reference value;
the data comparison module is used for comparing address code data in the received bit code stream data with a reference value, if the address code data is greater than the reference value, the address code to be compared is 1, and if the address code data is less than the reference value, the address code to be compared is 0;
the counting and accumulating module is used for comparing the address code data in the bit code stream data with the reference value every time after the comparison between the address code data and the reference value is completed and the address code to be compared is generated, comparing the address code to be compared with the preset address code, if the address code to be compared is equal to the preset address code, adding 1 to the counter, and if the address code to be compared is not equal to the preset address code, keeping the current numerical value of the counter unchanged;
and the pulse generation module is used for finishing synchronization and sending out a frame synchronization pulse if the value obtained by subtracting the configuration threshold value from the K is smaller than the value of the counter after the comparison times are K times, and entering a retransmission process if the value obtained by subtracting the configuration threshold value from the K is larger than the value of the counter.
The beneficial effect of adopting the further scheme is that: the traditional technology firstly does not introduce a reference value concept, directly compares received data with a preset address code, and actually the received address code and the preset address code are not equal in large area due to the influence of factors such as system gain adjustment or direct current elimination in the comparison process.
Further, the synchronization module includes:
the decoding module is used for decoding the received frequency offset code to obtain 1-bit load data;
the clock self-recovery module is used for automatically recovering the clock frequency according to the demodulation signal and the sampling frequency, comparing the clock frequency with the load data and then adjusting the clock period, and when the clock frequency is ahead of the load data, the clock period is automatically increased; when the clock frequency lags behind the load data, the clock period is reduced automatically, and finally a recovered clock signal is obtained;
the encoding module is used for encoding the load data obtained after decoding according to the recovered clock signal to obtain encoded data;
and the comparison module is used for comparing the coded data with externally input demodulation data so as to obtain the crystal oscillator frequency.
The beneficial effect of adopting the further scheme is that: the clock synchronization module adopts an internal self-generating clock to ensure the consistency of the decoded data and the clock, and the internal part of the clock is recovered to carry out frequency shift keying modulation to obtain the crystal oscillator frequency of the crystal, and the crystal oscillator frequency is fed back to a decoding end to carry out input data decoding, so that the decoding accuracy is improved.
Drawings
FIG. 1 is a schematic diagram of a prior art FSK modulation;
fig. 2 is a flowchart of a demodulation method of a frequency shift keying modulated signal according to an embodiment of the present invention;
FIG. 3 is a flow chart of frequency offset compensation according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating an embodiment of obtaining frame synchronization pulses according to the present invention;
FIG. 5 is a flowchart of a clock synchronization process according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a demodulation system for frequency shift keying modulated signals according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a down conversion processing module according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a clock synchronization module according to an embodiment of the present invention.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
Example 1
As shown in fig. 2, the present embodiment proposes a demodulation method for frequency shift keying modulated signals, the method including:
s1, processing data sent by an external radio frequency system to obtain two paths of I/Q data of intermediate frequency;
s2, performing direct current elimination processing on the I/Q data to remove direct current offset;
s3, performing down-conversion processing and frequency offset compensation on the I/Q data subjected to the direct current elimination processing through a numerically controlled oscillator, so that the I/Q signals reach zero intermediate frequency;
s4, limiting out-of-band noise by low-pass filtering the zero intermediate frequency I/Q data, and converting the I/Q data into phase data after time phase conversion;
and S5, limiting out-of-band noise of the phase data through low-pass filtering, and generating a bit code stream after differential subtraction and judgment operation, wherein the bit code stream data comprises J bit preamble, K bit address code and I bit load data. (ii) a
S6, comparing the generated bit code stream with the address code, and outputting frame synchronization pulse when the error number of the comparison result is less than the preset maximum number;
s7, outputting a frequency offset code after the generated bit code stream is subjected to frequency offset calculation;
and S8, demodulating the output frequency offset code, outputting a final demodulation result bit code stream, and simultaneously performing clock synchronization processing.
The embodiment provides a simple and more accurate frequency shift keying demodulation method aiming at the problems of high implementation difficulty, dependence on an external frame synchronization circuit and high error rate of the existing short-distance wireless communication frequency shift keying demodulation technology.
For the purpose of digitizing the input I/Q data in the zero, the frequency ω of the input data I/QRFPositive residue generated by digital controlled oscillatorThe string waveform frequency ω should be equal to achieve zero intermediate frequency. Ideal frequency omega of input data I/QRFThe sine-cosine waveform frequency omega generated by the numerical control oscillator is a known condition, but the ideal frequency omega of the input data I/QRFInfluenced by frequency error of transmission channel and transmitting system, and may be greater or less than ideal frequency omegaRF. This will cause the error rate of the whole demodulation system to increase, and in order to solve this problem, this embodiment proposes a method for performing frequency offset compensation processing on the I/Q data after dc cancellation processing, as shown in fig. 3, the method specifically implements the following processes:
s31, carrying out Gaussian modulation on the received I/Q data to obtain data A with the length of M bit;
s32, decoding the data A to obtain data B, subtracting the data B and the data A to obtain a frequency offset control word and sending the frequency offset control word to the numerically controlled oscillator;
and S33, adjusting the output frequency of the numerical control oscillator according to the frequency control word.
Through the process, omega can be ensured in real timeRFAnd the received intermediate frequency is equal to omega, namely the received intermediate frequency is consistent with the intermediate frequency generated by a numerical control oscillator in the receiving system, and the zero intermediate frequency of the received data is ensured for subsequent demodulation. In the conventional demodulation mode, frequency compensation is not performed at the position, but is performed before data decision, and because omega cannot be guaranteedRFEqual to ω, the error will be accumulated to the decided position, so the sensitivity will decrease and the error rate will increase.
Preferably, as shown in fig. 4, the process of obtaining the frame synchronization pulse in S6 is:
s61, accumulating the received bit code stream data for J times of leading data, and solving the average value of the accumulated values as a reference value;
s62, comparing the address code data in the received bit code stream data with a reference value, wherein if the address code data is greater than the reference value, the address code to be compared is 1, and if the address code data is less than the reference value, the address code to be compared is 0;
s63, after comparing the address code data in the bit code stream data with the reference value and generating the address code to be compared each time, comparing the address code to be compared with the preset address code, if equal, adding 1 to the counter, and if not, keeping the current numerical value unchanged by the counter;
and S64, when the comparison times are K times, if the value obtained by subtracting the configuration threshold value from K is smaller than the value of the counter, completing synchronization and sending out a frame synchronization pulse, and if the value obtained by subtracting the configuration threshold value from K is larger than the value of the counter, entering a retransmission process.
Through the above process, the demodulation system can be ensured to roughly lock the address code, generate the synchronous pulse and reduce the retransmission times.
The method comprises the steps of firstly, not introducing a reference value concept, directly comparing received data with a preset address code, wherein the received address code and the preset address code are possibly unequal in large area due to the fact that the actual comparison process is influenced by factors such as system gain adjustment or direct current elimination, secondly, a threshold value concept is not configured in the traditional technology, frame synchronization is successful only after the address code of K bit is completely matched with the preset address code of K bit, the actual comparison process is also influenced by factors such as system gain adjustment or direct current elimination, the comparison process is not completely reliable, and the frame synchronization can be determined to be completed only by successfully matching a certain number of address codes.
Preferably, as shown in fig. 5, the process of demodulating the frequency offset code output in S8, outputting a final demodulation result bit code stream, and performing clock synchronization processing at the same time includes:
s81, decoding the received frequency offset code to obtain 1bit load data;
s82, automatically recovering the clock frequency according to the demodulation signal and the sampling frequency, comparing the clock frequency with the load data, and then adjusting the clock period, wherein when the clock frequency is ahead of the load data, the clock period is increased; when the clock frequency lags behind the load data, the clock period is reduced automatically, and finally a recovered clock signal is obtained;
s83, according to the recovered clock signal, encoding the load data obtained after decoding to obtain encoded data;
and S84, comparing the coded data with externally input demodulation data to obtain a crystal oscillator frequency, and using the crystal oscillator frequency as a reference point of the decoding demodulation data.
The method adopts an internal self-generated clock to ensure the consistency of the decoded data and the clock, and obtains the crystal oscillator frequency of the crystal by recovering the internal part of the clock to carry out frequency shift keying modulation, and feeds the crystal oscillator frequency back to a decoding end to carry out input data decoding, thereby improving the decoding accuracy.
Example 2
As shown in fig. 6, the present embodiment proposes a demodulation system of a frequency shift keying modulated signal, the system including:
the original data processing module is used for processing data sent by an external radio frequency system to obtain two paths of I/Q data of intermediate frequency;
the direct current elimination module is used for carrying out direct current elimination processing on the I/Q data and eliminating direct current offset;
the down-conversion processing module is used for carrying out down-conversion processing and frequency offset compensation on the I/Q data subjected to the direct current elimination processing through a numerically controlled oscillator so that an I/Q signal reaches zero intermediate frequency;
the data conversion module is used for limiting out-of-band noise of the I/Q data subjected to zero intermediate frequency conversion through a pre-demodulation filter, and converting the I/Q data into phase data after time phase conversion;
the code stream generation module is used for limiting out-of-band noise of the phase data through the post-demodulation filter and generating a bit code stream after differential subtraction and judgment operation; the bit code stream data comprises J bit preamble, K bit address code and I bit load data.
The pulse output module is used for comparing the generated bit code stream with the address codes and outputting frame synchronization pulses when the error number of the comparison result is less than the preset maximum number;
the frequency offset calculation module is used for outputting a frequency offset code after the generated bit code stream is subjected to frequency offset calculation;
and the clock synchronization module is used for outputting a final demodulation result bit code stream after the output frequency offset code is demodulated and simultaneously carrying out clock synchronization processing.
The system aims at the problems that the existing short-distance wireless communication frequency shift keying demodulation system is difficult to realize, depends on an external frame synchronization circuit and has higher error rate, and provides a simple and more accurate frequency shift keying demodulation system.
For the purpose of digitizing the input I/Q data in the zero, the frequency ω of the input data I/QRFThe sine and cosine waveform frequency omega generated by the numerical control oscillator is equal to achieve the purpose of zero intermediate frequency conversion. Ideal frequency omega of input data I/QRFThe sine-cosine waveform frequency omega generated by the numerical control oscillator is a known condition, but the ideal frequency omega of the input data I/QRFInfluenced by frequency error of transmission channel and transmitting system, and may be greater or less than ideal frequency omegaRF. This will cause the error rate of the entire demodulation system to increase, and in order to solve this problem, this embodiment proposes a specific implementation manner of performing frequency offset compensation processing on the I/Q data after dc cancellation processing in the down-conversion processing module, as shown in fig. 7, the down-conversion processing module includes:
the Gaussian modulation module is used for carrying out Gaussian modulation on the received I/Q data to obtain data A with the length of M bit;
the decoding comparison module is used for decoding the data A to obtain data B, carrying out subtraction operation on the data B and the data A to obtain a frequency offset control word and sending the frequency offset control word to the numerically controlled oscillator;
and the frequency control module is used for adjusting the output frequency of the numerical control oscillator according to the frequency control word.
The received intermediate frequency can be consistent with the intermediate frequency generated by the numerical control oscillator through the processing process, zero intermediate frequency conversion of the received data is guaranteed, the received data is used for subsequent demodulation, the traditional demodulation mode is adopted, frequency compensation is not carried out in the process, the data is compensated before data judgment, errors can be accumulated to the judged position due to the fact that the zero intermediate frequency conversion of the received data cannot be guaranteed, the sensitivity is reduced, and the error rate is increased.
Preferably, the pulse output module includes:
the reference value calculation module is used for accumulating the received bit code stream data for J times of leading data and solving the average value of the accumulated values as a reference value;
the data comparison module is used for comparing address code data in the received bit code stream data with a reference value, if the address code data is greater than the reference value, the address code to be compared is 1, and if the address code data is less than the reference value, the address code to be compared is 0;
the counting and accumulating module is used for comparing the address code data in the bit code stream data with the reference value every time after the comparison between the address code data and the reference value is completed and the address code to be compared is generated, comparing the address code to be compared with the preset address code, if the address code to be compared is equal to the preset address code, adding 1 to the counter, and if the address code to be compared is not equal to the preset address code, keeping the current numerical value of the counter unchanged;
and the pulse generation module is used for finishing synchronization and sending out a frame synchronization pulse if the value obtained by subtracting the configuration threshold value from the K is smaller than the value of the counter after the comparison times are K times, and entering a retransmission process if the value obtained by subtracting the configuration threshold value from the K is larger than the value of the counter.
The traditional technology firstly does not introduce a reference value concept, directly compares received data with a preset address code, and actually the received address code and the preset address code are not equal in large area due to the influence of factors such as system gain adjustment or direct current elimination in the comparison process.
Preferably, as shown in fig. 8, the clock synchronization module includes:
the decoding module is used for decoding the received frequency offset code to obtain 1-bit load data;
the clock self-recovery module is used for automatically recovering the clock frequency according to the demodulation signal and the sampling frequency, comparing the clock frequency with the load data and then adjusting the clock period, and when the clock frequency is ahead of the load data, the clock period is automatically increased; when the clock frequency lags behind the load data, the clock period is reduced automatically, and finally a recovered clock signal is obtained;
the encoding module is used for encoding the load data obtained after decoding according to the recovered clock signal to obtain encoded data;
and the comparison module is used for comparing the coded data with externally input demodulation data so as to obtain the crystal oscillator frequency.
The clock synchronization module adopts an internal self-generating clock to ensure the consistency of the decoded data and the clock, and the internal part of the clock is recovered to carry out frequency shift keying modulation to obtain the crystal oscillator frequency of the crystal, and the crystal oscillator frequency is fed back to a decoding end to carry out input data decoding, so that the decoding accuracy is improved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (8)
1. A method of demodulating a frequency shift keying modulated signal, the method comprising:
s1, processing data sent by an external radio frequency system to obtain two paths of I/Q data of intermediate frequency, and performing down-conversion processing and frequency offset compensation on the I/Q data subjected to direct current elimination processing through a numerically controlled oscillator to enable the I/Q data to reach zero intermediate frequency;
s2, converting the zero intermediate frequency I/Q data into phase data, and generating bit code stream after differential subtraction and decision operation;
s3, comparing the generated bit code stream with the address code, and outputting frame synchronization pulse when the error number of the comparison result is less than the preset maximum number;
s4, after the generated bit code stream is subjected to frequency offset calculation, outputting a frequency offset code, demodulating the frequency offset code, outputting a final demodulation result bit code stream, and simultaneously performing clock synchronization processing;
the process of outputting the frame synchronization pulse in S3 is as follows:
s31, accumulating the received bit code stream data for J times of leading data, and solving the average value of the accumulated values as a reference value;
s32, comparing the address code data in the received bit code stream data with a reference value, wherein if the address code data is greater than the reference value, the address code to be compared is 1, and if the address code data is less than the reference value, the address code to be compared is 0;
s33, after comparing the address code data in the bit code stream data with the reference value and generating the address code to be compared each time, comparing the address code to be compared with the preset address code, if equal, adding 1 to the counter, and if not, keeping the current numerical value unchanged by the counter;
and S34, when the comparison times are K times, if the value obtained by subtracting the configuration threshold value from K is smaller than the value of the counter, completing synchronization and sending out a frame synchronization pulse, and if the value obtained by subtracting the configuration threshold value from K is larger than the value of the counter, entering a retransmission process.
2. The method according to claim 1, wherein the step of performing frequency offset compensation on the I/Q data after dc cancellation in S1 comprises:
s11, carrying out Gaussian modulation on the received I/Q data to obtain data A with the length of M bit;
s12, decoding the data A to obtain data B, subtracting the data B and the data A to obtain a frequency offset control word and sending the frequency offset control word to the numerically controlled oscillator;
and S13, adjusting the output frequency of the numerical control oscillator according to the frequency control word.
3. The method according to claim 1 or 2, wherein the bit code stream data generated in S2 includes J bit preamble, K bit address code and Ibit load data.
4. The method according to claim 3, wherein the process of outputting the final demodulation result bit stream after demodulating the frequency offset code output in the S4 and simultaneously performing the clock synchronization processing comprises:
s41, decoding the received frequency offset code to obtain 1bit load data;
s42, automatically recovering the clock frequency according to the demodulation signal and the sampling frequency, comparing the clock frequency with the load data, and then adjusting the clock period, wherein when the clock frequency is ahead of the load data, the clock period is increased; when the clock frequency lags behind the load data, the clock period is reduced automatically, and finally a recovered clock signal is obtained;
s43, according to the recovered clock signal, encoding the load data obtained after decoding to obtain encoded data;
and S44, comparing the coded data with externally input demodulation data to obtain a crystal oscillator frequency, and using the crystal oscillator frequency as a reference point of the decoding demodulation data.
5. A system for demodulating a frequency shift keying modulated signal, the system comprising:
the processing module is used for processing data sent by an external radio frequency system to obtain two paths of I/Q data of intermediate frequency; performing down-conversion processing and frequency offset compensation on the I/Q data subjected to the direct current elimination processing through a numerically controlled oscillator to enable an I/Q signal to reach zero intermediate frequency;
the conversion module is used for limiting out-of-band noise of the zero intermediate frequency I/Q data through low-pass filtering, converting the data into phase data after time phase conversion, and generating a bit code stream after differential subtraction and judgment operation;
the output module is used for comparing the generated bit code stream with the address code and outputting frame synchronization pulse when the error number of the comparison result is less than the preset maximum number;
the synchronization module is used for outputting the frequency offset code after the generated bit code stream is subjected to frequency offset calculation, outputting the final demodulation result bit code stream after demodulation and simultaneously performing clock synchronization processing;
the output module includes:
the reference value calculation module is used for accumulating the received bit code stream data for J times of leading data and solving the average value of the accumulated values as a reference value;
the data comparison module is used for comparing address code data in the received bit code stream data with a reference value, if the address code data is greater than the reference value, the address code to be compared is 1, and if the address code data is less than the reference value, the address code to be compared is 0;
the counting and accumulating module is used for comparing the address code data in the bit code stream data with the reference value every time after the comparison between the address code data and the reference value is completed and the address code to be compared is generated, comparing the address code to be compared with the preset address code, if the address code to be compared is equal to the preset address code, adding 1 to the counter, and if the address code to be compared is not equal to the preset address code, keeping the current numerical value of the counter unchanged;
and the pulse generation module is used for finishing synchronization and sending out a frame synchronization pulse if the value obtained by subtracting the configuration threshold value from the K is smaller than the value of the counter after the comparison times are K times, and entering a retransmission process if the value obtained by subtracting the configuration threshold value from the K is larger than the value of the counter.
6. The system of claim 5, wherein the processing module comprises:
the Gaussian modulation module is used for carrying out Gaussian modulation on the received I/Q data to obtain data A with the length of M bit;
the decoding comparison module is used for decoding the data A to obtain data B and carrying out subtraction operation on the data B and the data A to obtain a frequency offset control word;
and the frequency control module is used for adjusting the output frequency of the numerical control oscillator according to the frequency control word.
7. The demodulation system of the frequency shift keying modulation signal according to claim 5 or 6, wherein the bit code stream data generated in the conversion module includes J bit preamble, K bit address code and Ibit load data.
8. The system of claim 7, wherein the synchronization module comprises:
the decoding module is used for decoding the received frequency offset code to obtain 1-bit load data;
the clock self-recovery module is used for automatically recovering the clock frequency according to the demodulation signal and the sampling frequency, comparing the clock frequency with the load data and then adjusting the clock period, and when the clock frequency is ahead of the load data, the clock period is automatically increased; when the clock frequency lags behind the load data, the clock period is reduced automatically, and finally a recovered clock signal is obtained;
the encoding module is used for encoding the load data obtained after decoding according to the recovered clock signal to obtain encoded data;
and the comparison module is used for comparing the coded data with externally input demodulation data so as to obtain the crystal oscillator frequency.
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| TWI750589B (en) * | 2020-02-17 | 2021-12-21 | 茂達電子股份有限公司 | System and method for demodulating frequency shift keying signal |
| CN111314256B (en) * | 2020-03-03 | 2022-10-18 | 上海航天电子有限公司 | Method for restoring PCM code stream in burst data across clock domains |
| CN113098811B (en) * | 2021-04-01 | 2022-06-28 | 高拓讯达（北京）科技有限公司 | Demodulation decoding method and demodulation decoding device for GFSK (Gaussian filtered Shift keying) signals |
| CN113949486B (en) * | 2021-09-23 | 2023-10-20 | 武汉正维电子技术有限公司 | ADS_B signal analysis method and system based on symbol accumulation and correlation operation |
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| CN114124632B (en) * | 2021-11-23 | 2024-01-23 | 江苏势通生物科技有限公司 | Adaptive demodulation system and adaptive demodulation method for frequency shift keying signal |
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| CN115037431B (en) * | 2022-06-03 | 2023-07-21 | 深圳市纽瑞芯科技有限公司 | Symbol synchronization method in binary digital modulation |
| CN116016072B (en) * | 2023-03-22 | 2023-06-16 | 天津讯联科技有限公司 | Zero intermediate frequency structure low-complexity MSK quadrature demodulation device and demodulation method thereof |
| CN117692289A (en) * | 2023-12-08 | 2024-03-12 | 无锡盛景微电子股份有限公司 | Electronic detonator initiator communication system and method based on 2FSK |
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