CN107968757A - A kind of demodulation method and system of shift keying modulation signal - Google Patents
A kind of demodulation method and system of shift keying modulation signal Download PDFInfo
- Publication number
- CN107968757A CN107968757A CN201610919795.5A CN201610919795A CN107968757A CN 107968757 A CN107968757 A CN 107968757A CN 201610919795 A CN201610919795 A CN 201610919795A CN 107968757 A CN107968757 A CN 107968757A
- Authority
- CN
- China
- Prior art keywords
- data
- frequency
- bit
- code
- address code
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/14—Demodulator circuits; Receiver circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/14—Demodulator circuits; Receiver circuits
- H04L27/142—Compensating direct current components occurring during the demodulation and which are caused by mistuning
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
A kind of demodulation method and system of shift keying modulation signal, are related to shift keying modulation demodulation field.The data sent to exterior radio frequency system carry out processing and obtain the I/Q data of two-way IF frequency and remove direct current offset；Then zero intermediate frequency processing is carried out by digital controlled oscillator；The I/Q data of zero intermediate frequency are limited into out-of-band noise by low-pass filtering, and are changed into phase data after carrying out time phase conversion；Phase data is limited into out-of-band noise by low-pass filtering, and bit code streams are generated after difference subtraction and judgement computing；The bit code streams of generation are compared with address code, when comparison result number of errors is less than default maximum quantity, export frame-synchronizing impulse；Bit code streams will be generated after frequency offset computations, output frequency offset code；The frequency shift (FS) code final demodulation result bit code streams of demodulated output afterwards of output are simultaneously carried out at the same time clock synchronization process.The present invention is suitable for shift keying modulation and demodulates.
Description
Technical field
The present invention relates to shift keying modulation to demodulate field.
Background technology
Different modulation-demodulation techniques has different energy utilization efficiencies, to adapt to different application environments.Short distance
Wireless communication is short due to communication distance, it is desirable to low cost, low complex degree, low-power consumption, so can generally use simple and effective
Modulation demodulation system, including ASK (amplitude shift keying), PSK (phase-shift keying (PSK)), FSK (frequency shift keying) etc..Above-mentioned conventional modulation
Demodulation techniques change moment in data, and mutation occurs in carrier phase, cause the frequency spectrum of modulated signal outside main lobe in the presence of compared with
Big secondary lobe, forms the interference to adjacent channel.Although secondary lobe outside main lobe can be filtered out without shadow using band filter again
The transmission of information is rung, but the permanent envelope trait of modulated signal can be damaged.The signal of non-perseverance envelope is very high to linearity, only
Energy is relatively low using power efficiency but the preferable amplifier of the linearity is amplified.FSK modulation demodulation mode is improved can be with
GFSK modulation demodulation systems (GFSK Gaussian Frequency Shift Keying) are obtained, it can realize that phase is continuous at the former alternating of code, using the party
Formula can make signal energy concentrate on main lobe, be a kind of efficient modulation demodulation system.
Traditional scheme requirement has good acceptance while with low complex degree in Gaussian white noise channel
Can, the direct phase demodulation mode of generally use realizes demodulation function.Direct Phase Demodulation is a kind of phase using signal, without utilizing letter
Number amplitude demodulation mode.The signal received passes through after quadrature frequency conversion, solves the phase of signal, is looked into again afterwards
Partite transport is calculated, and recovers the baseband signal after Gaussian filter.
Current existing frequency shift-keying demodulation mode is as shown in Figure 1, this method has following defect：
1st, frame synchronization is produced by external circuit, realizes that process is extremely complex, it is necessary to the support for having external circuit, while its frame
The problem of synchronized algorithm can cause retransmission rate higher；
2nd, frequency compensated circuit is feedback-less form, and compensation real-time is poor, influences the bit error rate；
3rd, timing compensation algorithm is realized complicated, simultaneously because bits of information is carried from the zero crossing of baseband signal, in noise
It is affected by noise larger in the case of frequently relatively low.
The content of the invention
The present invention provides a kind of demodulation method and system of shift keying modulation signal, it is therefore intended that solve short distance without
Line communications applications field, it is relatively low in transmission power while in compatible a variety of message transmission rates and modulation index, inapplicable error correction
Coding and the bit error rate on the premise of, improve receiver sensitivity difficulty it is big the problem of.
The technical solution that the present invention solves above-mentioned technical problem is as follows：
A kind of demodulation method of shift keying modulation signal, the described method includes：
S1, the data sent to exterior radio frequency system are handled, and the I/Q data of two-way IF frequency are obtained, by direct current
I/Q data after Processing for removing carry out down-converted and frequency offset compensation by digital controlled oscillator so that I/Q data reach
To zero intermediate frequency；
S2, generate bit codes after the I/Q data of zero intermediate frequency are changed into phase data after difference subtraction and judgement computing
Stream；
S3, the bit code streams of generation are compared with address code, when comparison result number of errors is less than default maximum number
During amount, frame-synchronizing impulse is exported；
S4, will generate bit code streams after frequency offset computations, and demodulated rear output is final again for output frequency offset code
Demodulation result bit code streams are simultaneously carried out at the same time clock synchronization process.
The beneficial effects of the invention are as follows：It is difficult that the present invention is realized for existing short-distance wireless communication frequency shift-keying demodulation technology
The problem of degree is big, relies on exterior vertical sync circuit, while the bit error rate is higher, proposes a kind of simple, more accurate frequency shift keyed
Demodulation method, this method are detectd using the generation of internal self-synchronizing code, the generation of configurable frame swynchronization code and frequency shift (FS) to be feedback
Compensation technique is surveyed, instead of traditional frequency shift-keying demodulation technology, demodulating system is reached the sensitivity of higher, lower error code
Rate, and achieve complexity and substantially reduce.
Based on the above technical solutions, the present invention can also be improved as follows.
Further, the process in the S1 by the I/Q data progress frequency offset compensation processing after direct current Processing for removing is：
S11, the received I/Q data of docking carry out Gaussian modulation, obtain the data A of M length bit；
S12, carry out data A decoding acquisition data B, and data B and data A is carried out subtraction and obtains frequency shift (FS)
Control word is simultaneously sent to digital controlled oscillator；
S13, according to FREQUENCY CONTROL regulation digital controlled oscillator output frequency.
It is using the above-mentioned further beneficial effect of scheme：The IF frequency that can make to receive by journey processed above
It is consistent with the intermediate frequency that digital controlled oscillator produces, ensure to receive data zero intermediate frequency, for subsequent demodulation, and use traditional demodulation side
Formula, does not carry out frequency compensation in this process, but is compensated before data decision, due to cannot be guaranteed the number received
According to zero intermediate frequency, error accumulation to the position of judgement, such sensitivity be able to will be declined, the bit error rate can also rise.
Further, the bit bit stream datas generated in the S2 include J bit leading, K bit address codes and I bit and bear
Carry data.
Further, the process of acquisition frame-synchronizing impulse is in the S3：
S31, add up the bit bit stream datas received J lead data, asks for the average value of accumulated value as benchmark
Value；
S32, compare the address code data in the bit bit stream datas received with a reference value, if address code data
More than a reference value, then address code to be contrasted is 1, if address code data are less than a reference value, address code to be contrasted is 0；
S33, it is every completion bit bit stream data in address code data and a reference value relatively and generate treat contrastively
After the code of location, by address code to be contrasted compared with address code set in advance, if equal, counter adds 1, if not phase
Deng, then counter keep current value it is constant；
S34, when the number compared be K time after, if K subtract configuration threshold value numerical value be less than counter values, synchronization
Complete and send frame-synchronizing impulse, if the numerical value that K subtracts configuration threshold value is more than counter values, into retransmission procedure.
It is using the above-mentioned further beneficial effect of scheme：Conventional art is not introduce a reference value concept first, directly
The data and address code set in advance that receive are compared, the actual process in comparison due to by system gain adjustment or
Direct current, which such as eliminates at the factor, to be influenced, and the address code that receives and address code large area set in advance may be caused unequal, secondly
Also the concept of threshold value is configured without in conventional art, the address code set in advance of the only address code of K bit and K bit is complete
After matching, frame synchronization success is just represented, reality is equally in by comparison process by the factor shadow such as system gain adjustment or direct current elimination
Ring, comparison process is not completely reliable, it is only necessary to certain amount address code successful match, you can assert that frame synchronization is completed.
Further, final demodulation result bit code streams of output and same after the frequency shift (FS) code that is exported in the S4 is demodulated
The process of Shi Jinhang clock synchronization process is：
S41, the received frequency shift (FS) code of docking are decoded, and obtain 1bit load datas；
S42, recover clock frequency according to demodulated signal and sample frequency automatically, and by clock frequency and load data
Laggard clock cycle adjustment is compared, when clock frequency is ahead of load data, the clock cycle increases certainly；When clock frequency
When rate lags behind load data, the clock cycle from reducing, finally obtains the clock signal recovered；
S43, according to recovered clock signal, the load data obtained after decoding is encoded, obtains coded data；
S44, by coded data compared with externally input demodulating data, and then obtain crystal oscillator frequency, and will described in
Datum mark of the crystal oscillator frequency as decoding demodulating data.
It is using the above-mentioned further beneficial effect of scheme：Internal self-generating clock is used in the above method, ensures decoding
Data and the uniformity of clock afterwards, and by carrying out shift keying modulation inside recovered clock, obtain the crystal oscillator frequency of crystal
Rate, feeds back to decoding end and carries out input data decoding, improves decoding accuracy.
In order to solve the above-mentioned technical problem, the invention also provides a kind of demodulating system of shift keying modulation signal, institute
The system of stating includes：
Processing module, the data for being sent to exterior radio frequency system are handled, and obtain the I/Q numbers of two-way IF frequency
According to；I/Q data after direct current Processing for removing are subjected to down-converted and frequency offset compensation by digital controlled oscillator so that
I/q signal reaches zero intermediate frequency；
Conversion module, for the I/Q data of zero intermediate frequency to be limited out-of-band noise by low-pass filtering, and carries out time phase
It is changed into phase data after the conversion of position, and bit code streams is generated after difference subtraction and judgement computing；
Output module, for the bit code streams of generation to be compared with address code, when comparison result number of errors is less than in advance
If maximum quantity when, export frame-synchronizing impulse；
Synchronization module, for that will generate bit code streams after frequency offset computations, output frequency offset code is simultaneously demodulated
After export final demodulation result bit code streams and be carried out at the same time clock synchronization process.
The beneficial effects of the invention are as follows：It is difficult that the present invention is realized for existing short-distance wireless communication frequency shift-keying demodulation system
The problem of degree is big, relies on exterior vertical sync circuit, while the bit error rate is higher, proposes a kind of simple, more accurate frequency shift keyed
Demodulating system, the system are detectd using the generation of internal self-synchronizing code, the generation of configurable frame swynchronization code and frequency shift (FS) to be feedback
Compensation technique is surveyed, instead of traditional frequency shift-keying demodulation technology, demodulating system is reached the sensitivity of higher, lower error code
Rate, and achieve complexity and substantially reduce.
Further, the processing module includes：
Gaussian modulation module, carries out Gaussian modulation for docking received I/Q data, obtains the data A of M length bit；
Comparison module is decoded, obtains data B for carrying out decoding to data A, and data B and data A is subjected to subtraction fortune
Calculate and obtain frequency shift (FS) control word and send to digital controlled oscillator；
Frequency control module, for according to FREQUENCY CONTROL regulation digital controlled oscillator output frequency.
It is using the above-mentioned further beneficial effect of scheme：The IF frequency that can make to receive by journey processed above
It is consistent with the intermediate frequency that digital controlled oscillator produces, ensure to receive data zero intermediate frequency, for subsequent demodulation, and use traditional demodulation side
Formula, does not carry out frequency compensation in this process, but is compensated before data decision, due to cannot be guaranteed the number received
According to zero intermediate frequency, error accumulation to the position of judgement, such sensitivity be able to will be declined, the bit error rate can also rise.
Further, the bit bit stream datas generated in the conversion module include J bit leading, K bit address codes and I
Bit load datas.
Further, the output module includes：
A reference value computing module, for the bit received bit stream datas to be added up J lead data, asks for accumulated value
Average value is as a reference value；
Data comparison module, for the address code data in the bit received bit stream datas to be compared with a reference value, such as
Fruit address code data are more than a reference value, then address code to be contrasted is 1, if address code data are less than a reference value, is treated contrastively
Location code is 0；
Accumulator module is counted, the comparison for address code data and a reference value in bit bit stream data of every completion
And generate after address code is contrasted, by address code to be contrasted compared with address code set in advance, if equal, count
Device adds 1, if unequal, counter keeps current value constant；
Pulse generation module, for when the number compared be K time after, if K subtract configuration threshold value numerical value be less than counting
Device numerical value, then synchronously complete and send frame-synchronizing impulse, if the numerical value that K subtracts configuration threshold value is more than counter values, into
Enter retransmission procedure.
It is using the above-mentioned further beneficial effect of scheme：Conventional art is not introduce a reference value concept first, directly
The data and address code set in advance that receive are compared, the actual process in comparison due to by system gain adjustment or
Direct current, which such as eliminates at the factor, to be influenced, and the address code that receives and address code large area set in advance may be caused unequal, secondly
Also the concept of threshold value is configured without in conventional art, the address code set in advance of the only address code of K bit and K bit is complete
After matching, frame synchronization success is just represented, reality is equally in by comparison process by the factor shadow such as system gain adjustment or direct current elimination
Ring, comparison process is not completely reliable, it is only necessary to certain amount address code successful match, you can assert that frame synchronization is completed.
Further, the synchronization module includes：
Decoder module, is decoded for docking received frequency shift (FS) code, obtains 1bit load datas；
Self-recovery module, for recovering clock frequency automatically according to demodulated signal and sample frequency, and by when
The laggard clock cycle adjustment compared with load data of clock frequency, when clock frequency is ahead of load data, clock week
Phase increases certainly；When clock frequency lags behind load data, the clock cycle from reducing, finally obtains the clock signal recovered；
Coding module, for according to recovered clock signal, the load data obtained after decoding being encoded, is encoded
Data；
Comparison module, for by coded data compared with externally input demodulating data, and then obtain crystal oscillator frequency.
It is using the above-mentioned further beneficial effect of scheme：Internal self-generating clock is used in the clock synchronization module,
Ensure decoded data and the uniformity of clock, and by carrying out shift keying modulation inside recovered clock, obtain crystal
Crystal oscillator frequency, feed back to decoding end carry out input data decoding, improve decoding accuracy.
Brief description of the drawings
Fig. 1 is the principle schematic of shift keying modulation in the prior art；
Fig. 2 is the flow chart of the demodulation method of the shift keying modulation signal described in the embodiment of the present invention；
Fig. 3 is the flow chart of the frequency offset compensation described in the embodiment of the present invention；
Fig. 4 is the flow chart of the acquisition frame-synchronizing impulse described in the embodiment of the present invention；
Fig. 5 is the flow chart of the clock synchronization process described in the embodiment of the present invention；
Fig. 6 is the principle schematic of the demodulating system of the shift keying modulation signal described in the embodiment of the present invention；
Fig. 7 is the principle schematic of the down-converted module described in the embodiment of the present invention；
Fig. 8 is the principle schematic of the clock synchronization module described in the embodiment of the present invention.
Embodiment
The principle and features of the present invention will be described below with reference to the accompanying drawings, and the given examples are served only to explain the present invention, and
It is non-to be used to limit the scope of the present invention.
Embodiment 1
As shown in Fig. 2, the present embodiment proposes a kind of demodulation method of shift keying modulation signal, the described method includes：
S1, the data sent to exterior radio frequency system are handled, and obtain the I/Q data of two-way IF frequency；
S2, carry out direct current Processing for removing to I/Q data, removes direct current offset；
S3, pass through digital controlled oscillator by the I/Q data after direct current Processing for removing and carry out down-converted and frequency shift (FS)
Compensation so that i/q signal reaches zero intermediate frequency；
S4, by the I/Q data of zero intermediate frequency limit out-of-band noise by low-pass filtering, and becomes after carrying out time phase conversion
For phase data；
S5, by phase data by low-pass filtering limit out-of-band noise, and by difference subtraction and judgement computing after generate
Bit code streams, the bit bit stream datas include J bit leading, K bit address codes and I bit load datas.；
S6, the bit code streams of generation are compared with address code, when comparison result number of errors is less than default maximum number
During amount, frame-synchronizing impulse is exported；
S7, will generate bit code streams after frequency offset computations, output frequency offset code；
Final demodulation result bit code streams of output and to be carried out at the same time clock same after S8, the frequency shift (FS) code of output are demodulated
Step processing.
The present embodiment realizes that difficulty is big for existing short-distance wireless communication frequency shift-keying demodulation technology, and it is same to rely on external frame
Step circuit, while the problem of the bit error rate is higher, propose a kind of simple, more accurate frequency shift keyed demodulation method, this method is adopted
The frame swynchronization code generation that generated with internal self-synchronizing code, can configure and frequency shift (FS) to be feedback detecting compensation technique, instead of passing
System frequency shift-keying demodulation technology, enables demodulating system to reach the sensitivity of higher, the lower bit error rate, and achieves multiple
Miscellaneous degree substantially reduces.
For the purpose of zero point intermediate frequencyization input I/Q data, the frequencies omega of its input data I/QRFProduced with digital controlled oscillator
Raw sine and cosine waveform frequency ω should be equal, can be only achieved the purpose of zero intermediate frequency.The ideal frequency ω of input data I/QRF
The sine and cosine waveform frequency ω produced with digital controlled oscillator is known conditions, but the ideal frequency ω of input data I/QRFBy
The influence of transmission channel and emission system frequency error, may be greater than or less than ideal frequency ωRF.This will cause entirely demodulation system
The bit error rate of system rises, and in order to solve this problem, the present embodiment proposes the I/Q data after the middle Processing for removing by direct current into line frequency
The method of rate migration processing, as shown in figure 3, the method specific implementation process is：
S31, the received I/Q data of docking carry out Gaussian modulation, obtain the data A of M length bit；
S32, carry out data A decoding acquisition data B, and data B and data A is carried out subtraction and obtains frequency shift (FS)
Control word is simultaneously sent to digital controlled oscillator；
S33, according to FREQUENCY CONTROL regulation digital controlled oscillator output frequency.
, can be with real-time ensuring ω by the above processRFEqual to ω, that is, numerical control in the IF frequency and reception system received
The intermediate frequency that oscillator produces is consistent, ensures to receive data zero intermediate frequency, for subsequent demodulation.And traditional demodulation mode is used, do not have
Have and carry out frequency compensation in the position, but compensated before data decision, due to cannot be guaranteed ωRFEqual to ω, then can incite somebody to action
The accumulation of error will decline to the position of judgement, such sensitivity, and the bit error rate will rise.
Preferably, as shown in figure 4, the process that frame-synchronizing impulse is obtained in the S6 is：
S61, add up the bit bit stream datas received J lead data, asks for the average value of accumulated value as benchmark
Value；
S62, compare the address code data in the bit bit stream datas received with a reference value, if address code data
More than a reference value, then address code to be contrasted is 1, if address code data are less than a reference value, address code to be contrasted is 0；
S63, it is every completion bit bit stream data in address code data and a reference value relatively and generate treat contrastively
After the code of location, by address code to be contrasted compared with address code set in advance, if equal, counter adds 1, if not phase
Deng, then counter keep current value it is constant；
S64, when the number compared be K time after, if K subtract configuration threshold value numerical value be less than counter values, synchronization
Complete and send frame-synchronizing impulse, if the numerical value that K subtracts configuration threshold value is more than counter values, into retransmission procedure.
Demodulating system maximum probability lock address code can be ensured by above procedure, produce lock-out pulse, reduce repeating transmission time
Number.
First without a reference value concept is introduced in conventional art, directly the data and address code set in advance received
It is compared, the actual process in comparison may cause to receive due to being influenced by the factor such as system gain adjustment or direct current elimination
The address code and address code large area set in advance arrived is unequal, and the concept of threshold value is secondly also configured without in conventional art,
Only after the matching completely of the address code set in advance of the address code of K bit and K bit, frame synchronization success is just represented, it is actual same
Sample is influenced in by comparison process by the factor such as system gain adjustment or direct current elimination, and comparison process is not completely reliable, is only needed
Want certain amount address code successful match, you can assert that frame synchronization is completed.
Preferably, as shown in figure 5, exporting final demodulation result after the frequency shift (FS) code exported in the S8 is demodulated
Bit code streams are simultaneously carried out at the same time the process of clock synchronization process and are：
S81, the received frequency shift (FS) code of docking are decoded, and obtain 1bit load datas；
S82, recover clock frequency according to demodulated signal and sample frequency automatically, and by clock frequency and load data
Laggard clock cycle adjustment is compared, when clock frequency is ahead of load data, the clock cycle increases certainly；When clock frequency
When rate lags behind load data, the clock cycle from reducing, finally obtains the clock signal recovered；
S83, according to recovered clock signal, the load data obtained after decoding is encoded, obtains coded data；
S84, by coded data compared with externally input demodulating data, and then obtain crystal oscillator frequency, and will described in
Datum mark of the crystal oscillator frequency as decoding demodulating data.
Internal self-generating clock is used in the above method, ensures decoded data and the uniformity of clock, and pass through
Shift keying modulation is carried out inside recovered clock, obtains the crystal oscillator frequency of crystal, decoding end is fed back to and carries out input data decoding,
Improve decoding accuracy.
Embodiment 2
As shown in fig. 6, the present embodiment proposes a kind of demodulating system of shift keying modulation signal, the system comprises：
Original data processing module, the data for being sent to exterior radio frequency system are handled, and are obtained in two-way again and again
The I/Q data of rate；
Direct current cancellation module, for carrying out direct current Processing for removing to I/Q data, removes direct current offset；
Down-converted module, for the I/Q data after direct current Processing for removing to be carried out down coversion by digital controlled oscillator
Processing and frequency offset compensation so that i/q signal reaches zero intermediate frequency；
Data conversion module, for the I/Q data of zero intermediate frequency to be limited out-of-band noise by pre-demodulating wave filter, goes forward side by side
It is changed into phase data after the conversion of row time phase；
Code stream generation module, for phase data to be limited out-of-band noise by rear demodulator filter, and subtracts by difference
Bit code streams are generated after method and judgement computing；The bit bit stream datas include J bit leading, K bit address codes and I bit and bear
Carry data.
Pulse output module, for the bit code streams of generation to be compared with address code, when comparison result number of errors is small
When default maximum quantity, frame-synchronizing impulse is exported；
Frequency offset computations module, for bit code streams will to be generated after frequency offset computations, output frequency offset code；
Clock synchronization module, the demodulated rear final demodulation result bit code streams of output of frequency shift (FS) code for output are simultaneously
It is carried out at the same time clock synchronization process.
The system realizes that difficulty is big for existing short-distance wireless communication frequency shift-keying demodulation system, relies on exterior frame synchronization
Circuit, while the problem of the bit error rate is higher, propose a kind of simple, more accurate frequency shift keyed demodulating system, which uses
Internal self-synchronizing code generation, the generation of configurable frame swynchronization code and frequency shift (FS) to be feedback detecting compensation technique, instead of tradition
Frequency shift-keying demodulation technology, enables demodulating system to reach the sensitivity of higher, the lower bit error rate, and achieves complexity
Degree substantially reduces.
For the purpose of zero point intermediate frequencyization input I/Q data, the frequencies omega of its input data I/QRFProduced with digital controlled oscillator
Raw sine and cosine waveform frequency ω should be equal, can be only achieved the purpose of zero intermediate frequency.The ideal frequency ω of input data I/QRF
The sine and cosine waveform frequency ω produced with digital controlled oscillator is known conditions, but the ideal frequency ω of input data I/QRFBy
The influence of transmission channel and emission system frequency error, may be greater than or less than ideal frequency ωRF.This will cause entirely demodulation system
The bit error rate of system rises, and in order to solve this problem, the present embodiment is proposed after direct current Processing for removing in down-converted module
I/Q data carry out frequency offset compensation processing specific implementation, as shown in fig. 7, the down-converted module includes：
Gaussian modulation module, carries out Gaussian modulation for docking received I/Q data, obtains the data A of M length bit；
Comparison module is decoded, obtains data B for carrying out decoding to data A, and data B and data A is subjected to subtraction fortune
Calculate and obtain frequency shift (FS) control word and send to digital controlled oscillator；
Frequency control module, for according to FREQUENCY CONTROL regulation digital controlled oscillator output frequency.
By journey processed above the IF frequency that receives can be made consistent with the intermediate frequency that digital controlled oscillator produces, ensured
Data zero intermediate frequency is received, for subsequent demodulation, and traditional demodulation mode is used, does not carry out frequency compensation in this process,
But compensated before data decision, can be by error accumulation to judgement due to the data zero intermediate frequency that cannot be guaranteed to receive
Position, such sensitivity will decline, and the bit error rate can also rise.
Preferably, the pulse output module includes：
A reference value computing module, for the bit received bit stream datas to be added up J lead data, asks for accumulated value
Average value is as a reference value；
Data comparison module, for the address code data in the bit received bit stream datas to be compared with a reference value, such as
Fruit address code data are more than a reference value, then address code to be contrasted is 1, if address code data are less than a reference value, is treated contrastively
Location code is 0；
Accumulator module is counted, the comparison for address code data and a reference value in bit bit stream data of every completion
And generate after address code is contrasted, by address code to be contrasted compared with address code set in advance, if equal, count
Device adds 1, if unequal, counter keeps current value constant；
Pulse generation module, for when the number compared be K time after, if K subtract configuration threshold value numerical value be less than counting
Device numerical value, then synchronously complete and send frame-synchronizing impulse, if the numerical value that K subtracts configuration threshold value is more than counter values, into
Enter retransmission procedure.
Conventional art is not introduce a reference value concept first, directly the data and address code set in advance received
It is compared, the actual process in comparison may cause to receive due to being influenced by the factor such as system gain adjustment or direct current elimination
The address code and address code large area set in advance arrived is unequal, and the concept of threshold value is secondly also configured without in conventional art,
Only after the matching completely of the address code set in advance of the address code of K bit and K bit, frame synchronization success is just represented, it is actual same
Sample is influenced in by comparison process by the factor such as system gain adjustment or direct current elimination, and comparison process is not completely reliable, is only needed
Want certain amount address code successful match, you can assert that frame synchronization is completed.
Preferably, as shown in figure 8, the clock synchronization module includes：
Decoder module, is decoded for docking received frequency shift (FS) code, obtains 1bit load datas；
Self-recovery module, for recovering clock frequency automatically according to demodulated signal and sample frequency, and by when
The laggard clock cycle adjustment compared with load data of clock frequency, when clock frequency is ahead of load data, clock week
Phase increases certainly；When clock frequency lags behind load data, the clock cycle from reducing, finally obtains the clock signal recovered；
Coding module, for according to recovered clock signal, the load data obtained after decoding being encoded, is encoded
Data；
Comparison module, for by coded data compared with externally input demodulating data, and then obtain crystal oscillator frequency.
Internal self-generating clock is used in the clock synchronization module, ensures decoded data and the uniformity of clock,
And by carrying out shift keying modulation inside recovered clock, the crystal oscillator frequency of crystal is obtained, decoding end is fed back to and is inputted
Data decode, and improve decoding accuracy.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all the present invention spirit and
Within principle, any modification, equivalent replacement, improvement and so on, should all be included in the protection scope of the present invention.
Claims (10)
- A kind of 1. demodulation method of shift keying modulation signal, it is characterised in that the described method includes：S1, the data sent to exterior radio frequency system are handled, and obtain the I/Q data of two-way IF frequency, direct current is eliminated I/Q data after processing carry out down-converted and frequency offset compensation by digital controlled oscillator so that I/Q data reach zero Intermediate frequency；S2, generate bit code streams after the I/Q data of zero intermediate frequency are changed into phase data after difference subtraction and judgement computing；S3, the bit code streams of generation are compared with address code, when comparison result number of errors is less than default maximum quantity When, export frame-synchronizing impulse；S4, will generate bit code streams after frequency offset computations, the demodulated final demodulation of rear output again of output frequency offset code As a result bit code streams and it is carried out at the same time clock synchronization process.
- 2. the demodulation method of a kind of shift keying modulation signal according to claim 1, it is characterised in that will in the S1 The process that I/Q data after direct current Processing for removing carry out frequency offset compensation processing is：S11, the received I/Q data of docking carry out Gaussian modulation, obtain the data A of M length bit；S12, carry out data A decoding acquisition data B, and data B and data A is carried out subtraction and obtains frequency shift (FS) control Word is simultaneously sent to digital controlled oscillator；S13, the output frequency according to FREQUENCY CONTROL regulation digital controlled oscillator.
- A kind of 3. demodulation method of shift keying modulation signal according to claim 1 or 2, it is characterised in that the S2 The bit bit stream datas of middle generation include J bit leading, K bit address codes and I bit load datas.
- 4. the demodulation method of a kind of shift keying modulation signal according to claim 3, it is characterised in that obtained in the S3 The process of frame-synchronizing impulse is：S31, add up the bit bit stream datas received J lead data, asks for the average value of accumulated value as a reference value；S32, compare the address code data in the bit bit stream datas received with a reference value, if address code data are more than A reference value, then address code to be contrasted is 1, if address code data are less than a reference value, address code to be contrasted is 0；S33, the address code data in bit bit stream data of every completion and a reference value relatively and generate address code to be contrasted Afterwards, by address code to be contrasted compared with address code set in advance, if equal, counter adds 1, if unequal, Then counter keeps current value constant；S34, when the number compared be K time after, if K subtract configure threshold value numerical value be less than counter values, synchronously complete And frame-synchronizing impulse is sent, if the numerical value that K subtracts configuration threshold value is more than counter values, into retransmission procedure.
- 5. the demodulation method of a kind of shift keying modulation signal according to claim 4, it is characterised in that defeated in the S4 The final demodulation result bit code streams of output and the process of clock synchronization process is carried out at the same time after the frequency shift (FS) code that goes out is demodulated For：S41, the received frequency shift (FS) code of docking are decoded, and obtain 1bit load datas；S42, recover clock frequency according to demodulated signal and sample frequency automatically, and clock frequency and load data are carried out More laggard clock cycle adjustment, when clock frequency is ahead of load data, the clock cycle increases certainly；When clock frequency falls When load data, the clock cycle from reducing, finally obtains the clock signal recovered；S43, according to recovered clock signal, the load data obtained after decoding is encoded, obtains coded data；S44, by coded data compared with externally input demodulating data, and then obtain crystal oscillator frequency, and by the crystal oscillator Datum mark of the frequency as decoding demodulating data.
- A kind of 6. demodulating system of shift keying modulation signal, it is characterised in that the system comprises：Processing module, the data for being sent to exterior radio frequency system are handled, and obtain the I/Q data of two-way IF frequency； I/Q data after direct current Processing for removing are subjected to down-converted and frequency offset compensation by digital controlled oscillator so that I/Q Signal reaches zero intermediate frequency；Conversion module, for the I/Q data of zero intermediate frequency to be limited out-of-band noise by low-pass filtering, and carries out time phase turn It is changed into phase data after change, and bit code streams is generated after difference subtraction and judgement computing；Output module, for the bit code streams of generation to be compared with address code, when comparison result number of errors is less than default During maximum quantity, frame-synchronizing impulse is exported；Synchronization module, for that will generate bit code streams after frequency offset computations, output frequency offset code is simultaneously demodulated rear defeated Go out final demodulation result bit code streams and be carried out at the same time clock synchronization process.
- A kind of 7. demodulating system of shift keying modulation signal according to claim 6, it is characterised in that the processing mould Block includes：Gaussian modulation module, carries out Gaussian modulation for docking received I/Q data, obtains the data A of M length bit；Comparison module is decoded, obtains data B for carrying out decoding to data A, and data B and data A progress subtractions are obtained Obtain frequency shift (FS) control word；Frequency control module, for according to FREQUENCY CONTROL regulation digital controlled oscillator output frequency.
- 8. the demodulating system of a kind of shift keying modulation signal according to claim 6 or 7, it is characterised in that described turn Changing the bit bit stream datas generated in module includes J bit leading, K bit address codes and I bit load datas.
- A kind of 9. demodulating system of shift keying modulation signal according to claim 8, it is characterised in that the output mould Block includes：A reference value computing module, for the bit received bit stream datas to be added up J lead data, asks for being averaged for accumulated value Value is used as a reference value；Data comparison module, for the address code data in the bit received bit stream datas to be compared with a reference value, if ground Location code data are more than a reference value, then address code to be contrasted is 1, if address code data are less than a reference value, address code to be contrasted For 0；Accumulator module is counted, for the relatively and raw of the address code data in bit bit stream data of every completion and a reference value Into after address code is contrasted, by address code to be contrasted compared with address code set in advance, if equal, counter adds 1, if unequal, counter keeps current value constant；Pulse generation module, for when the number compared be K time after, if K subtract configure threshold value numerical value be less than counter number Value, then synchronously complete and send frame-synchronizing impulse, if the numerical value that K subtracts configuration threshold value is more than counter values, enters weight Send out flow.
- A kind of 10. demodulating system of shift keying modulation signal according to claim 9, it is characterised in that the synchronization Module includes：Decoder module, is decoded for docking received frequency shift (FS) code, obtains 1bit load datas；Self-recovery module, for recovering clock frequency automatically according to demodulated signal and sample frequency, and by clock frequently Rate laggard clock cycle adjustment compared with load data, when clock frequency is ahead of load data, the clock cycle is certainly Increase；When clock frequency lags behind load data, the clock cycle from reducing, finally obtains the clock signal recovered；Coding module, for according to recovered clock signal, the load data obtained after decoding being encoded, obtains coded number According to；Comparison module, for by coded data compared with externally input demodulating data, and then obtain crystal oscillator frequency.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610919795.5A CN107968757B (en) | 2016-10-20 | 2016-10-20 | Demodulation method and system for frequency shift keying modulation signal |
| PCT/CN2017/086836 WO2018072448A1 (en) | 2016-10-20 | 2017-06-01 | Frequency shift key modulation signal demodulation method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610919795.5A CN107968757B (en) | 2016-10-20 | 2016-10-20 | Demodulation method and system for frequency shift keying modulation signal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107968757A true CN107968757A (en) | 2018-04-27 |
| CN107968757B CN107968757B (en) | 2020-12-18 |
Family
ID=61997319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610919795.5A Active CN107968757B (en) | 2016-10-20 | 2016-10-20 | Demodulation method and system for frequency shift keying modulation signal |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN107968757B (en) |
| WO (1) | WO2018072448A1 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109167650A (en) * | 2018-10-18 | 2019-01-08 | 珠海市杰理科技股份有限公司 | Bluetooth receiver and bluetooth encode frame detection method |
| WO2020037974A1 (en) * | 2018-08-20 | 2020-02-27 | 北京邮电大学 | Signal capturing method and apparatus |
| CN111314256A (en) * | 2020-03-03 | 2020-06-19 | 上海航天电子有限公司 | Method for restoring PCM code stream in burst data across clock domains |
| CN113271275A (en) * | 2020-02-17 | 2021-08-17 | 茂达电子股份有限公司 | Frequency shift keying signal demodulation system and method |
| CN114124632A (en) * | 2021-11-23 | 2022-03-01 | 江苏势通生物科技有限公司 | Adaptive demodulation system and adaptive demodulation method for frequency shift keying signals |
| CN115037431A (en) * | 2022-06-03 | 2022-09-09 | 深圳市纽瑞芯科技有限公司 | Code element synchronization method in binary digital modulation |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113098811B (en) * | 2021-04-01 | 2022-06-28 | 高拓讯达（北京）科技有限公司 | Demodulation decoding method and demodulation decoding device for GFSK (Gaussian filtered Shift keying) signals |
| CN113949486B (en) * | 2021-09-23 | 2023-10-20 | 武汉正维电子技术有限公司 | ADS_B signal analysis method and system based on symbol accumulation and correlation operation |
| CN114070341B (en) * | 2021-11-17 | 2023-05-05 | 南京英锐创电子科技有限公司 | Tire pressure detection signal receiving circuit, system and method |
| CN114553646B (en) * | 2022-01-09 | 2023-03-31 | 苏州大学 | Reconfigurable modulation-demodulation system based on WBAN (white blood cell network) narrowband physical layer |
| CN116016072B (en) * | 2023-03-22 | 2023-06-16 | 天津讯联科技有限公司 | Zero intermediate frequency structure low-complexity MSK quadrature demodulation device and demodulation method thereof |
| CN117692289A (en) * | 2023-12-08 | 2024-03-12 | 无锡盛景微电子股份有限公司 | Electronic detonator initiator communication system and method based on 2FSK |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1224730A1 (en) * | 1999-10-08 | 2002-07-24 | Medtronic Inc. | Fsk demodulator using a frequency conversion stage with three parallel mixers |
| CN105515615A (en) * | 2016-01-12 | 2016-04-20 | 浙江共同电子科技有限公司 | Power line carrier communication method |
| CN105812303A (en) * | 2016-03-15 | 2016-07-27 | 苏州卓智创芯电子科技有限公司 | GFSK baseband digital receiver and baseband synchronization and demodulation method of the GFSK baseband digital receiver |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100579094C (en) * | 2003-02-25 | 2010-01-06 | 华为技术有限公司 | A kind of receiving handling method of frequency shift keyed signals |
| CN101309253B (en) * | 2007-06-11 | 2012-04-25 | 杭州中科微电子有限公司 | Non-coherent frequency compensation, demodulation method and demodulating apparatus |
| GB2453767A (en) * | 2007-10-19 | 2009-04-22 | Toumaz Technology Ltd | Automatic frequency correction in a frequency shift keying recevier |
-
2016
- 2016-10-20 CN CN201610919795.5A patent/CN107968757B/en active Active
-
2017
- 2017-06-01 WO PCT/CN2017/086836 patent/WO2018072448A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1224730A1 (en) * | 1999-10-08 | 2002-07-24 | Medtronic Inc. | Fsk demodulator using a frequency conversion stage with three parallel mixers |
| CN105515615A (en) * | 2016-01-12 | 2016-04-20 | 浙江共同电子科技有限公司 | Power line carrier communication method |
| CN105812303A (en) * | 2016-03-15 | 2016-07-27 | 苏州卓智创芯电子科技有限公司 | GFSK baseband digital receiver and baseband synchronization and demodulation method of the GFSK baseband digital receiver |
Non-Patent Citations (1)
| Title |
|---|
| 华林: "UHF RFID单片集成阅读器芯片射频接收前端电路设计", 《中国优秀硕士论文全文数据库 信息科技辑》 * |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020037974A1 (en) * | 2018-08-20 | 2020-02-27 | 北京邮电大学 | Signal capturing method and apparatus |
| US11303485B2 (en) | 2018-08-20 | 2022-04-12 | Beijing University Of Posts And Telecommunications | Signal acquisition method and device |
| CN109167650A (en) * | 2018-10-18 | 2019-01-08 | 珠海市杰理科技股份有限公司 | Bluetooth receiver and bluetooth encode frame detection method |
| CN109167650B (en) * | 2018-10-18 | 2021-03-19 | 珠海市杰理科技股份有限公司 | Bluetooth receiver and method for detecting Bluetooth coding frame |
| CN113271275A (en) * | 2020-02-17 | 2021-08-17 | 茂达电子股份有限公司 | Frequency shift keying signal demodulation system and method |
| CN113271275B (en) * | 2020-02-17 | 2024-05-10 | 茂达电子股份有限公司 | Frequency shift keying signal demodulation system and method |
| CN111314256A (en) * | 2020-03-03 | 2020-06-19 | 上海航天电子有限公司 | Method for restoring PCM code stream in burst data across clock domains |
| CN111314256B (en) * | 2020-03-03 | 2022-10-18 | 上海航天电子有限公司 | Method for restoring PCM code stream in burst data across clock domains |
| CN114124632A (en) * | 2021-11-23 | 2022-03-01 | 江苏势通生物科技有限公司 | Adaptive demodulation system and adaptive demodulation method for frequency shift keying signals |
| CN114124632B (en) * | 2021-11-23 | 2024-01-23 | 江苏势通生物科技有限公司 | Adaptive demodulation system and adaptive demodulation method for frequency shift keying signal |
| CN115037431A (en) * | 2022-06-03 | 2022-09-09 | 深圳市纽瑞芯科技有限公司 | Code element synchronization method in binary digital modulation |
| CN115037431B (en) * | 2022-06-03 | 2023-07-21 | 深圳市纽瑞芯科技有限公司 | Symbol synchronization method in binary digital modulation |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107968757B (en) | 2020-12-18 |
| WO2018072448A1 (en) | 2018-04-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107968757A (en) | A kind of demodulation method and system of shift keying modulation signal | |
| CA2152781C (en) | Digital demodulator with frequency and timing control | |
| CN108512791B (en) | Satellite-borne AIS demodulation method based on timing frequency offset compensation | |
| CN1138394A (en) | Digital communications equipment using differential quaternary frequency shift keying | |
| EA031912B1 (en) | Combined amplitude-time modulation and phase modulation | |
| CN1265547A (en) | Improved phase estimation for use in reinsertion of phase-modulated signal carrier such as quadrature-amplitude modulated signal carrier | |
| US8649465B2 (en) | Methods and apparatuses for adaptive clock reconstruction and decoding in audio frequency communication | |
| CN113489664A (en) | Wireless frequency shift keying communication frequency offset compensation circuit and method | |
| CN109412632B (en) | A kind of high-speed frequency-hopping transmitting-receiving communication device based on distortion adaptive | |
| US20220103407A1 (en) | Fsk radio-frequency demodulators | |
| CN111901269B (en) | Gaussian frequency shift keying modulation method, device and system with variable modulation index | |
| CN102123122B (en) | Modulation-demodulation device and modulation-demodulation method | |
| CN106453171A (en) | Self-interference elimination method of co-frequency co-time full duplex system | |
| CN110300079A (en) | A kind of msk signal coherent demodulation method and system | |
| CN112350970A (en) | Multiphase frequency shift keying modulation and demodulation method and equipment | |
| CN101795250B (en) | Demodulation method and device of D8PSK (differential 8-ary phase shift keying) modulation signals of VDL (VHF (very high frequency) digital link) communication system | |
| CN106508104B (en) | A kind of method of extension remote measurement coherent receiver frequency offset estimation range | |
| CN102457461B (en) | Data-processing unit and signal receiver including the data-processing unit | |
| Rice et al. | A new algorithm for 16QAM carrier phase estimation using QPSK partitioning | |
| CN111431834B (en) | High-efficiency underwater current field communication method with high reliability | |
| CN105391659B (en) | Decode the circuit for the high-speed type a-signal that card is sent | |
| RU2308165C1 (en) | Device for non-coherent demodulation of frequency-manipulated signals with continuous phase | |
| CN115174325B (en) | Double-tone FSK modulation-demodulation system for wireless energy-carrying communication | |
| CN107968647A (en) | Clock recovery method and system in a kind of frequency shift keying regulating system | |
| CN105119855B (en) | A kind of modulation and demodulation method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |