CN107943196A - Super low-power consumption whole CMOS reference circuit system - Google Patents
Super low-power consumption whole CMOS reference circuit system Download PDFInfo
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- CN107943196A CN107943196A CN201711016255.7A CN201711016255A CN107943196A CN 107943196 A CN107943196 A CN 107943196A CN 201711016255 A CN201711016255 A CN 201711016255A CN 107943196 A CN107943196 A CN 107943196A
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- pipes
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- source electrode
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/262—Current mirrors using field-effect transistors only
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
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Abstract
The invention discloses a kind of super low-power consumption whole CMOS reference circuit system, including：One start-up circuit, for driving the reference circuit, startup is more stable, and system is more stable；One micro-current generation circuit, the operational amplification circuit for the reference circuit provide operating current, its core is that metal-oxide-semiconductor is operated in sub-threshold region, therefore overall work electric current is the electric current of as low as na level, and power consumption is very small；One operational amplification circuit, at utmost reduces the influence produced by curent change to circuit；One core reference circuit, produce the reference current and reference voltage of core, the precision for producing reference voltage is very high, resistance is used due to no in whole circuit, also it is no to use triode, entirely MOS transistor, so the area of overall circuit is very small, the temperature coefficient of the circuit still can be adjusted according to test case.
Description
Technical field
The present invention relates to reference voltage circuit field, more particularly to a kind of super low-power consumption whole CMOS reference circuit system.
Background technology
In the application of Internet of Things and most of wireless telecommunications, associated receiver circuitry or radiating circuit etc. are all that needs are low
Power consumption, therefore the reference circuit that can produce low-power consumption is very crucial and very necessary for whole application.Benchmark electricity
Pith of the road as analog circuit, generally requires and is worked normally within the scope of a wider temperature, therefore does not require nothing more than
It is low in energy consumption, it is also necessary to which that performance is stablized, and has preferable temperature characterisitic.Traditional mode can be set using band-gap reference circuit
Meter, but its power consumption is relatively large, and need to use resistance and triode, cause chip area larger.
The content of the invention
It is complete it is a primary object of the present invention to provide a kind of super low-power consumption to overcome the above-mentioned problems of the prior art
CMOS reference circuit systems, suitable for the circuit system of super low-power consumption.
In view of the above and other objects, the present invention provides a kind of super low-power consumption whole CMOS reference circuit system, it is at least wrapped
Include：
One start-up circuit, for driving the reference circuit, startup is more stable, and system is more stable；
One micro-current generation circuit, the operational amplification circuit for the reference circuit provide operating current, its core is metal-oxide-semiconductor work
Make in sub-threshold region, therefore overall work electric current is the electric current of as low as na level, power consumption is very small；
One operational amplification circuit, at utmost reduces the influence produced by curent change to circuit；
One core reference circuit, produces the reference current and reference voltage of core, and it is very high to produce the precision of reference voltage, also matches somebody with somebody
There is temperature system to configure port, use resistance due to no in whole circuit, be entirely MOS crystal also without triode is used
Pipe, so the area of overall circuit is very small, the temperature coefficient of the circuit still can be adjusted according to test case.
It is a feature of the present invention that the start-up circuit is by the first NMOS tube NM1, the second NMOS tube NM2 and the first capacitance
C1 is formed；One end of capacitance C1 is connected with supply voltage；The other end of capacitance C1 and the drain electrode of NM1 pipes and the grid of NM2 pipes
It is connected；The source electrode of NM1 pipes and the source electrode ground connection of NM2 pipes；
The micro-current generation circuit is by the first PMOS tube PM1, the second PMOS tube PM2, the 3rd PMOS tube PM3, the 3rd NMOS tube
NM3 and the 4th NMOS tube NM4 is formed；The source electrode of PM1 pipes and the source electrode of PM2 pipes are all connected with supply voltage VDD；PM1 pipes
Drain electrode is connected with the grid of PM1 pipes, the grid of PM2 pipes, the drain electrode of NM2 pipes and the drain electrode of NM3 pipes；The source electrode and NM4 of NM3 pipes
The drain electrode of pipe is connected with the grid of NM4 pipes；The drain electrode and the drain electrode of the grid of NM3 pipes, the grid of PM3 pipes, PM3 pipes of PM2 pipes
It is connected with the source electrode of PM3 pipes, wherein, PM3 pipes make diode use；The source electrode of NM4 pipes and the Substrate ground of PM3 pipes；
The operational amplification circuit is by the 4th PMOS tube PM4, the 5th PMOS tube PM5, the 6th PMOS tube PM6, the 5th NMOS tube
NM5, the 6th NMOS tube NM6, the 7th NMOS tube NM7 and the 8th NMOS tube NM8 are formed；The source electrode of PM4 pipes, the source electrode of PM5 pipes and
The source electrode of PM6 pipes is all connected with supply voltage VDD；The grid of PM4 pipes is connected with the grid of PM1 pipes；The drain electrode of PM4 pipes with
The drain electrode of the grid, NM5 pipes of NM5 pipes is connected with the grid of NM6 pipes；The grid of PM5 pipes and the drain electrode of PM5 pipes, the grid of PM6 pipes
The drain electrode of pole and NM7 pipes is connected；The drain electrode of PM6 pipes is connected with the drain electrode of NM8 pipes, its node label is VC；The source of NM7 pipes
Pole is connected with the drain electrode of the source electrode and NM6 pipes of NM8 pipes；The source electrode of NM5 pipes and the source electrode ground connection of NM6 pipes；
The core reference circuit is by the 7th PMOS tube PM7, the 8th PMOS tube PM8, the 9th PMOS tube PM9, the 9th NMOS tube
NM9, the tenth NMOS tube NM10, the 11st NMOS tube NM11, the 12nd NMOS tube NM12, the 13rd NMOS tube NM13, the 14th
NMOS tube NM14, the 15th NMOS tube NM15, the 16th NMOS tube NM16 and the 17th NMOS tube NM17 are formed；The source of PM7 pipes
The source electrode of pole, the source electrode of PM8 pipes and PM9 pipes is all connected with supply voltage；The grid of PM7 pipes, the grid of PM8 pipes and PM9 pipes
Grid be all connected with node VC；The drain electrode of PM7 pipes is connected with the drain electrode of the grid of NM8 pipes, the grid and NM9 pipes of NM9 pipes
Connect, its node label is VA；The drain electrode grid of NM7 pipes, the grid of NM10 pipes, the drain electrode of NM10 pipes, the grid of NM12 pipes of PM8 pipes
Pole, the drain electrode of NM12 pipes, the grid of NM13 pipes, the drain electrode of NM13 pipes, the drain electrode of grid and NM15 pipes of NM15 pipes are connected, its
Node label is VB；The source electrode of NM10 pipes is connected with the drain electrode of the grid and NM11 pipes of NM11 pipes；The source electrode of NM13 pipes with
The drain electrode of NM14 pipes is connected；The source electrode of NM15 pipes is connected with the drain electrode of NM16 pipes；The grid of NM14 pipes connects input control letter
Number CT1；The grid of NM16 pipes meets input control signal CT2；Drain electrode and the grid of NM17 pipes and the drain electrode phase of NM17 pipes of PM9 pipes
Connection, output terminal of its node as reference voltage V REF, the grid of NM1 pipes are connected with the node；Source electrode, the NM11 of NM9 pipes
The source electrode of pipe, the source electrode of NM12 pipes, the source electrode of NM14 pipes, the source electrode ground connection of the source electrode of NM16 pipes and NM17 pipes.
Brief description of the drawings
The attached drawing for forming the part of the application is used for providing a further understanding of the present invention, schematic reality of the invention
Apply example and its explanation is used to explain the present invention, do not form inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 is super low-power consumption whole CMOS reference circuit system of the present invention；
Fig. 2 is the structure diagram of PM3 pipes of the present invention.
Embodiment
With reference to shown in Fig. 1, in the following embodiments, the super low-power consumption whole CMOS reference circuit system, it is at least wrapped
Include：One start-up circuit, for driving the reference circuit, startup is more stable, and system is more stable；One micro-current generation circuit, its
Core is that metal-oxide-semiconductor is operated in sub-threshold region, therefore overall work electric current is the electric current of as low as na level, and power consumption is very small；One fortune
Amplifying circuit is calculated, at utmost reduces the influence produced by curent change to circuit；One core reference circuit, produces core
Reference current and reference voltage, it is very high to produce the precision of reference voltage, due to, resistance is not used, also not having in whole circuit
It is entirely MOS transistor, so the area of overall circuit is very small, the temperature coefficient of the circuit still may be used using triode
To be adjusted according to test case.
The start-up circuit is made of capacitance C1, NMOS tube NM1 and NM2, when power vd D is powered on, capacitance C1 both ends
Voltage will not suddenly change, therefore the grid of NM2 pipes can be coupled into high voltage, then NM2 pipes turn on, so as to there is electric current to flow through
PM1 is managed, and micro-current generation circuit is started to work, when the work of whole circuit stability and VREF one normal value of output, NM1 pipes
Grid becomes high voltage, and the conducting of NM1 pipes, low level is pulled into by the grid of NM2 pipes, so that start-up circuit is closed, it is whole to start electricity
Road also just completes startup work.
The micro-current generation circuit is by the first PMOS tube PM1, the second PMOS tube PM2, the 3rd PMOS tube PM3, the 3rd
NMOS tube NM3 and the 4th NMOS tube NM4 is formed；Diode positive as one PM3, its voltage are a threshold voltage, phase
When the sum of gate source voltage in NM3 pipes and NM4 pipes, then just force NM3 pipes to enter sub-threshold region, therefore the electric current Ib produced is
The low current of nA ranks, flows through PM4 tube grids, is providing tail current source to amplifier by current mirroring circuit, is driving operation amplifier
Circuit is started to work, which belongs to the amplifier for being operated in sub-threshold region, belong to the structure of small power consumption amplifier.
Fig. 2 is the structure diagram of PM3 pipes, and P-substrate is P type substrate, and n-WEll is the n traps of PMOS tube,
Cathode is the anode of diode, and Anode is the cathode of diode.The grid of PM3, source electrode, drain electrode are connected as diode just
Pole, substrate avoid using temperature change caused by big resistance as diode cathode, it also avoid using parasitism pnp, PM3
Voltage between grid source of the voltage of cathode-anode equal to NM3 and NM4 and, therefore NM3 pipes enter sub-threshold region.
The operational amplification circuit is by the 4th PMOS tube PM4, the 5th PMOS tube PM5, the 6th PMOS tube PM6, the 5th NMOS
Pipe NM5, the 6th NMOS tube NM6, the 7th NMOS tube NM7 and the 8th NMOS tube NM8 are formed；Amplifier uses level-one differential configuration, leads to
Overcurrent mirror structure transistor NM5 pipe and NM6 pipes as load and drive output current cause electric current I1 and I2 to balance, its
The load of current-mirror structure further improves voltage gain, reduces power source change dependence.
The core reference circuit is by the 7th PMOS tube PM7, the 8th PMOS tube PM8, the 9th PMOS tube PM9, the 9th NMOS
Pipe NM9, the tenth NMOS tube NM10, the 11st NMOS tube NM11, the 12nd NMOS tube NM12, the 13rd NMOS tube NM13, the tenth
Four NMOS tube NM14, the 15th NMOS tube NM15, the 16th NMOS tube NM16 and the 17th NMOS tube NM17 are formed；Wherein CT1
It is input control signal with CT2, high level or low level can be arranged in system level as needed；The operation amplifier
Circuit causes node VA voltages to be equal to node VB, and therefore, negative temperature characteristic, transistor NM11 is presented in the voltage on transistor NM9
On voltage present positive temperature characterisitic, transistor NM10, NM12, NM13, NM15 and NM17 pass through adjusting equivalent to passive resistance
NM10 pipes, NM12 pipes, the physical dimension of NM17 and NM9 pipes, the area of NM11 pipes can realize temperature-compensating.In the actual manufacture of chip
During, pipe sizing and characteristic cause temperature coefficient uneven it is possible that some deviations, such as or with temperature
Rise and raise, if this occurs, the input level value of CT1 and CT2 in the present invention can be adjusted to reach more preferable
Temperature coefficient.Such as when designing circuit, two input signal CT1 and CT2, one be high level another be low level,
Temperature coefficient temperature is balance at this time, is increased when test finds VREF voltages as temperature raises, then can be by CT1
Be both configured to low level with CT2, when test find VREF voltages with temperature raises and when reducing, then can by CT1 and
CT2 is both configured to high level, and temperature coefficient is finely adjusted in this way.NM13 is consistent with the pipe sizing of NM15, this
The amplitude of downward of being reconciled on sample is just as, and the default value of CT1 and CT2, one is high level, and one is low level, no matter
CT1 is high level or CT2 is high level, what its temperature coefficient result was just as.As CT1 and CT2 at the same time for high level or
When person is low level at the same time, initiative offset will occur for its temperature coefficient, and whether CT1 and CT2 need to adjust, it should according to temperature
Spend depending on test result.
The present invention proposes a kind of super low-power consumption whole CMOS reference circuit system, compared with other circuits, does not make in circuit
It is also simpler without using triode, structure with resistance.The circuit is designed using 0.18 μm of CMOS technology, as CT1 and CT2 mono-
When for high level one being low level, the output voltage of 900mV can be provided, temperature coefficient is 18ppm/ DEG C, electricity during 1.8V
Flow for 20nA, the performance of circuit is greatly improved under conditions of limited area.
Although the present invention is illustrated using specific embodiment, the present invention's is not intended to limit to the explanation of embodiment
Scope.One skilled in the art is by reference to explanation of the invention, without departing substantially from the spirit and scope of the present invention
In the case of, easily carry out various modifications or embodiment can be combined, these also should be regarded as protection scope of the present invention.
Claims (5)
1. super low-power consumption whole CMOS reference circuit system, including：One start-up circuit, for driving the reference circuit, starts more
Stablize, system is more stable；One micro-current generation circuit, the operational amplification circuit for the reference circuit provide operating current, its
Core is that metal-oxide-semiconductor is operated in sub-threshold region, therefore overall work electric current is the electric current of as low as na level, and power consumption is very small；One fortune
Amplifying circuit is calculated, at utmost reduces the influence produced by curent change to circuit；One core reference circuit, using cascade
Structure, the precision of the reference voltage of generation is also very high, and resistance is used due to no in whole circuit, also no to use three poles
Pipe, is entirely MOS transistor, so the area of overall circuit is very small.
2. the full COMS reference circuits system of super low-power consumption as claimed in claim 1, it is characterised in that：The start-up circuit is by
One NMOS tube NM1, the second NMOS tube NM2 and the first capacitance C1 are formed；One end of capacitance C1 is connected with supply voltage VDD；Electricity
The grid for holding the other end of C1 with the drain electrode of NM1 pipes and NM2 pipes is connected；The source electrode of NM1 pipes and the source electrode ground connection of NM2 pipes.
3. low-power consumption COMS reference circuits as claimed in claim 1, it is characterised in that：The micro-current generation circuit is by first
PMOS tube PM1, the second PMOS tube PM2, the 3rd PMOS tube PM3, the 3rd NMOS tube NM3 and the 4th NMOS tube NM4 are formed；PM1 is managed
Source electrode and the source electrodes of PM2 pipes be all connected with supply voltage VDD；The drain electrode of PM1 pipes and grid, the grid of PM2 pipes of PM1 pipes
The drain electrode of pole, NM2 pipes is connected with the drain electrode of NM3 pipes；The source electrode of NM3 pipes is connected with the drain electrode of NM4 pipes and the grid of NM4 pipes
Connect；The drain electrode of PM2 pipes is connected with the source electrode of the grid of NM3 pipes, the grid of PM3 pipes, the drain electrode of PM3 pipes and PM3 pipes, wherein,
PM3 pipes make diode use；The source electrode of NM4 pipes and the Substrate ground of PM3 pipes.
4. low-power consumption COMS reference circuits as claimed in claim 1, it is characterised in that：The operational amplification circuit is by the 4th
PMOS tube PM4, the 5th PMOS tube PM5, the 6th PMOS tube PM6, the 5th NMOS tube NM5, the 6th NMOS tube NM6, the 7th NMOS tube
NM7 and the 8th NMOS tube NM8 is formed；The source electrode of the source electrode of PM4 pipes, the source electrode of PM5 pipes and PM6 pipes all with supply voltage VDD phases
Connection；The grid of PM4 pipes is connected with the grid of PM1 pipes；Drain electrode and NM6 of the drain electrode of PM4 pipes with the grid, NM5 pipes of NM5 pipes
The grid of pipe is connected；The drain electrode of the grid of PM5 pipes and PM5 pipes, the drain electrode of the grid and NM7 pipes of PM6 pipes are connected；PM6 is managed
Drain electrode be connected with the drain electrode of NM8 pipes, its node label is VC；The leakage of the source electrode of NM7 pipes and the source electrode of NM8 pipes and NM6 pipes
Pole is connected；The source electrode of NM5 pipes and the source electrode ground connection of NM6 pipes.
5. low-power consumption COMS reference circuits as claimed in claim 1, it is characterised in that：The core reference circuit is by the 7th
PMOS tube PM7, the 8th PMOS tube PM8, the 9th PMOS tube PM9, the 9th NMOS tube NM9, the tenth NMOS tube NM10, the 11st NMOS
Pipe NM11, the 12nd NMOS tube NM12, the 13rd NMOS tube NM13, the 14th NMOS tube NM14, the 15th NMOS tube NM15,
16 NMOS tube NM16 and the 17th NMOS tube NM17 are formed；The source electrode of the source electrode of PM7 pipes, the source electrode of PM8 pipes and PM9 pipes all with
Supply voltage is connected；The grid of the grid of PM7 pipes, the grid of PM8 pipes and PM9 pipes is all connected with node VC；The leakage of PM7 pipes
The drain electrode of the grid of pole and NM8 pipes, the grid and NM9 pipes of NM9 pipes is connected, its node label is VA；The drain electrode NM7 of PM8 pipes
The grid of pipe, the grid of NM10 pipes, the drain electrode of NM10 pipes, the grid of NM12 pipes, the drain electrode of NM12 pipes, NM13 pipes grid,
The drain electrode of NM13 pipes, the drain electrode of the grid and NM15 pipes of NM15 pipes are connected, its node label is VB；The source electrode of NM10 pipes with
The drain electrode of the grid of NM11 pipes and NM11 pipes is connected；The source electrode of NM13 pipes is connected with the drain electrode of NM14 pipes；The source of NM15 pipes
Pole is connected with the drain electrode of NM16 pipes；The grid of NM14 pipes meets input control signal CT1；The grid of NM16 pipes connects input control letter
Number CT2；The drain electrode of PM9 pipes is connected with the drain electrode of the grid and NM17 pipes of NM17 pipes, its node is as reference voltage V REF's
Output terminal, the grid of NM1 pipes are connected with the node；The source electrode of NM9 pipes, the source electrode of NM11 pipes, the source electrodes of NM12 pipes, NM14 pipes
The source electrode ground connection of source electrode, the source electrode of NM16 pipes and NM17 pipes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711016255.7A CN107943196A (en) | 2017-10-25 | 2017-10-25 | Super low-power consumption whole CMOS reference circuit system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711016255.7A CN107943196A (en) | 2017-10-25 | 2017-10-25 | Super low-power consumption whole CMOS reference circuit system |
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| CN107943196A true CN107943196A (en) | 2018-04-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201711016255.7A Pending CN107943196A (en) | 2017-10-25 | 2017-10-25 | Super low-power consumption whole CMOS reference circuit system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108445954A (en) * | 2018-05-30 | 2018-08-24 | 丹阳恒芯电子有限公司 | A kind of low voltage reference circuit |
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