CN107942240B

CN107942240B - Function test method and device for DSP module in FPGA chip

Info

Publication number: CN107942240B
Application number: CN201711130799.6A
Authority: CN
Inventors: 蒯金; 周忠斌
Original assignee: Shenzhen Pango Microsystems Co Ltd
Current assignee: Shenzhen Pango Microsystems Co Ltd
Priority date: 2017-11-15
Filing date: 2017-11-15
Publication date: 2020-03-31
Anticipated expiration: 2037-11-15
Also published as: CN107942240A

Abstract

The invention discloses a function test method and a function test device for a DSP module in an FPGA chip, and belongs to the technical field of FPGA chips. The function test method comprises the following steps: the method comprises the steps of carrying out the same function configuration on each DSP module in an FPGA chip, and reading input excitation to each DSP module through an MEM module in the FPGA chip; the output result of each DSP module is respectively subjected to exclusive-OR comparison with the expected output result stored in the MEM module to obtain a plurality of groups of multi-bit exclusive-OR results of each DSP module; and sequentially carrying out feedback OR operation on the multiple groups of multi-bit XOR results of each DSP module to sequentially feed back the previous group of OR operation results and the next group of OR operation results, so that the multiple groups of multi-bit XOR results are finally reduced to one bit to be output to obtain the test result of each DSP module. The invention can reduce the requirement on the test condition to the utmost extent, and can complete the function test of all DSP modules in the FPGA chip only by using the MEM module in the FPGA chip.

Description

Function test method and device for DSP module in FPGA chip

Technical Field

The invention relates to the technical field of FPGA chips, in particular to a function test method and a function test device for a DSP module in an FPGA chip.

Background

With the rapid development of integrated circuits, an FPGA (Field-Programmable Gate Array) chip is gradually developed from an electronic design peripheral device to the core of a digital system in more than twenty years, and with the progress of semiconductor process technology, the design technology of the FPGA chip has made a leap development and breakthrough, achieving the characteristics of high density, high confidentiality, low power consumption, low cost, system integration, dynamic reconfiguration and the like, and the FPGA chip has been widely applied in the fields of communication, aerospace, consumer electronics and the like. In recent years, with the rapid development of some data Processing services such as information technology, internet of things, smart cities, artificial intelligence and the like, the advantage of the FPGA chip in the aspect of data Processing becomes more and more obvious, so that the DSP (Digital Signal Processing) function in the FPGA chip becomes more and more important.

However, while the capability of the DSP in the FPGA chip to process data is getting stronger, the design of the DSP module in the FPGA chip is getting more complex, and since the functional correctness of the DSP module in the FPGA chip after tape-out directly affects the data processing capability of the FPGA chip, it is very important how to quickly complete the functional test of all the DSP modules in each FPGA chip under limited test conditions, and it is related to whether to complete the quick screening of the FPGA chip, so as to improve the production efficiency of the FPGA chip.

Disclosure of Invention

The invention mainly aims to provide a function test method of a DSP module in an FPGA chip, aiming at reducing the requirement on test conditions to the maximum extent and completing the function test of all DSP modules in the FPGA chip only by using an MEM (memory) module in the FPGA chip.

In order to achieve the above object, the present invention provides a method for testing functions of a DSP module in an FPGA chip, the method comprising the steps of: the method comprises the steps of carrying out the same function configuration on each DSP module in an FPGA chip, and reading input excitation to each DSP module through an MEM module in the FPGA chip; performing exclusive-or comparison on the output result of each DSP module and the expected output result stored in the MEM module to obtain a plurality of groups of multi-bit exclusive-or results of each DSP module; and sequentially carrying out feedback type OR operation on the multiple groups of multi-bit XOR results of each DSP module to sequentially feed back the previous group of OR operation results and the next group of OR operation results, so that the multiple groups of multi-bit XOR results are finally reduced to one bit to be output to obtain the test result of each DSP module.

Optionally, the step of performing the same function configuration on each DSP module inside the FPGA chip and reading the input stimuli into each DSP module through the MEM module inside the FPGA chip specifically includes: performing the same function configuration on each DSP module, and connecting the corresponding inputs of all DSP modules in the FPGA chip and the output of the MEM module together by using internal wiring resources in the FPGA chip; and after the FPGA chip is started to be in an awakening state, the MEM module reads input excitation to each DSP module.

Optionally, the functions of the DSP module include an I/O (input/output) characteristic function, a preader (pre-add) characteristic function, a Mult (multiply) characteristic function, and a postladder characteristic function.

Optionally, the function testing method further includes the following steps: and performing OR operation on the test results of all the DSP modules to obtain a DSP function test result of the FPGA chip.

Optionally, the function testing method further includes the following steps: and scanning the test result of each DSP module in sequence through a shift register chain so as to scan the DSP module with abnormal function.

Optionally, the shift register chain comprises a plurality of shift registers in one-to-one correspondence with each of the DSP modules.

In addition, the invention also provides a function testing device of the DSP module in the FPGA chip, which comprises: the input excitation unit is used for carrying out the same function configuration on each DSP module in the FPGA chip and reading input excitation to each DSP module through an MEM module in the FPGA chip; an exclusive-or comparison unit, configured to perform exclusive-or comparison on the output result of each DSP module and an expected output result stored in the MEM module, respectively, to obtain multiple sets of multi-bit exclusive-or results of each DSP module; and the primary processing unit is used for sequentially carrying out feedback OR operation on the multi-group multi-bit XOR result of each DSP module so as to sequentially feed back the former group OR operation result and the latter group OR operation result, so that the multi-group multi-bit XOR result is finally reduced to one bit to be output to obtain the test result of each DSP module.

Optionally, the functions of the DSP module include an I/O characteristic function, a preader characteristic function, a Mult characteristic function, and a postladder characteristic function.

Optionally, the function testing apparatus further includes a secondary processing unit, configured to perform an or operation on the test results of all the DSP modules to obtain a function test result of the FPGA chip.

Optionally, the function testing apparatus further includes an exception positioning unit, configured to scan a test result of each DSP module in sequence through a shift register chain, so as to scan out the DSP module with an exception function; the shift register chain comprises a plurality of shift registers which correspond to the DSP modules one by one.

The invention provides a function testing method and a function testing device for DSP modules in an FPGA chip, which utilize the internal programmable characteristic of the FPGA chip, and read and excite the inputs of all the DSP modules in the FPGA chip into each DSP module through an MEM module by connecting the corresponding inputs of all the DSP modules in the FPGA chip with the output of the MEM module. And then, the output result of each DSP module is respectively subjected to exclusive-OR comparison with the expected output result stored by the MEM module to obtain a plurality of groups of multi-bit exclusive-OR results of each DSP module. And finally, performing feedback type OR operation on the multi-group multi-bit XOR result of each DSP module bit by bit, so that the multi-group multi-bit XOR result is finally reduced to one bit to be output, and the test result of each DSP module is obtained. Therefore, the requirements on the test conditions can be reduced to the maximum extent, and the function test of all DSP modules in the FPGA chip can be completed only by means of the MEM module in the FPGA chip, so that the functional correctness of all DSP modules in the FPGA chip is ensured, and when the actual FPGA chip has problems, the functional errors of the DSP modules in the FPGA chip can be rapidly positioned.

Drawings

Fig. 1 is a flow chart of a method for testing a function of a DSP module in an FPGA chip according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a functional test structure of a DSP module in the FPGA chip of the present invention.

FIG. 3 is a schematic diagram illustrating a DSP test unit in the functional test structure shown in FIG. 2.

Fig. 4 is a flowchart of a method for testing a function of a DSP module in an FPGA chip according to a second embodiment of the present invention.

Fig. 5 is a flowchart of a method for testing a function of a DSP module in an FPGA chip according to a third embodiment of the present invention.

FIG. 6 is a scan diagram of the shift register chain scanning the test results of each DSP module according to the present invention.

Fig. 7 is a connection block diagram of a function testing apparatus for a DSP module in an FPGA chip according to a fourth embodiment of the present invention.

The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.

Detailed Description

It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

In the following description, suffixes such as "module", "component", or "unit" used to denote elements are used only for facilitating the explanation of the present invention, and have no specific meaning in itself. Thus, "module", "component" or "unit" may be used mixedly.

Example one

As shown in fig. 1, an embodiment of the present invention provides a method for testing a function of a DSP module in an FPGA chip, where the method for testing a function includes the following steps:

step S110: and performing the same function configuration on each DSP module in the FPGA chip, and reading input excitation to each DSP module through an MEM module in the FPGA chip.

Specifically, when we want to perform function testing on all DSP modules in the FPGA chip, each DSP module needs to be configured with the same function, so as to perform corresponding function testing. Meanwhile, due to the programmable characteristic inside the FPGA chip, the inputs corresponding to all the DSP modules in the FPGA chip and the output of the MEM module can be connected together through the wiring resources inside the FPGA chip, that is, as shown in fig. 2. Therefore, when the DSP module in the FPGA chip is subjected to function Test, only one excitation input interface is needed to be connected to the input excitation generated after the Test Pattern Generation (TPG) of the Test platform, and then the function Test of all the DSP modules in the FPGA chip can be started. When the FPGA chip to be subjected to the function test is started to be in an awakening state, the MEM module in the FPGA chip reads the input excitation generated by the TPG into each DSP module so as to perform the function test on each DSP module.

The functions of the DSP module in the FPGA chip include an I/O (input/output) characteristic function, a preader (pre-load) characteristic function, a Mult (multiply) characteristic function, and a postladder characteristic function, where the I/O characteristic function of the DSP module is specifically embodied that the I/O (input/output) of the DSP module has independent control signal and configuration information characteristics, and under different control signals and configuration modes, the input excitation read by the MEM module or the output generated by the DSP module can be changed accordingly to obtain the input and output expected by us. The Preadder characteristic function of the DSP module is embodied in that the DSP module has a Preadder (pre-adding) logical operation function and can realize 18+/-18 or two 9+/-9 logical operations. The Mult characteristic function of the DSP module is embodied as that the DSP has a Mult logical operation function, and can implement one 18 × 18 or two 9 × 9 logical operations. The function of the DSP module with the postscaler characteristic is embodied as that the DSP module has a postscaler logical operation function, and can implement one 48-bit add/subtract/accumulator or two 24-bit add/subtract/accumulators.

The Test Pattern Generation (TPG) Test platform mainly drives a clock and a reset signal through an excitation file, or drives the clock and the reset signal by using a signal source and a crystal oscillator, and during testing, it is required to ensure that the driving time is enough to read input excitation in the MEM module and ensure complete output comparison. Because the method generates the input excitation by reading the data stored in the MEM module and the output is compared in real time, when the TPG generates a counter of 10 bits, only the clock period is ensured to be between 1024 and 1500.

Step S120: and respectively carrying out exclusive-OR comparison on the output result of each DSP module and the expected output result stored in the MEM module to obtain a plurality of groups of multi-bit exclusive-OR results of each DSP module.

Specifically, after the MEM module reads the input stimuli to each DSP module, all the DSP modules in the FPGA chip can be functionally tested to respectively test the I/O characteristic function, the preader characteristic function, the Mult characteristic function, and the postladder characteristic function of the DSP module. Since the same function configuration is already performed on each DSP module in the FPGA chip before the MEM module reads the input stimuli into each DSP module, at this time, each DSP module performs corresponding logic processing on the read input stimuli according to the current function configuration to obtain a corresponding output result. The output results can be divided into a plurality of groups, and the output results can be different according to different input stimuli read by the current DSP module.

In the exclusive-or comparison, if the output result is not the same as the expected output result stored in the MEM module, the exclusive-or result is 1 (i.e., a high level signal is output), and if the output result is the same as the expected output result stored in the MEM module, the exclusive-or result is 0 (i.e., a high level signal is output). Thus, as shown in fig. 3, by performing an exclusive or comparison (XOR) of the output result with the expected output result stored in the MEM module, it is possible to confirm whether each DSP module functions normally by detecting the output signal.

When the I/O characteristic function of the DSP module is tested, the MEM module in the FPGA chip reads input excitation to the input port of the DSP module, and then the output result of the output port of the DSP module and the expected output result read from the MEM module are sent to a response mechanism (ORA) module for exclusive-OR comparison, so that whether the I/O characteristic function of the DSP module is normal or not can be known.

When the Preadder characteristic function of the DSP module is tested, the MEM module in the FPGA chip reads an input port of Preadder logic input and excited to the DSP module, and then an output result generated by the Preadder logic and an expected output result read from the MEM module are sent to a response mechanism (ORA) module for exclusive-OR comparison, so that whether the Preadder characteristic function of the DSP module is normal or not can be known.

When the Mult characteristic function of the DSP module is tested, the output generated by the input excitation read by the MEM module and the Preader logic is sent to the input port of the Mult logic, and then the output result generated by the Mult logic and the expected output result read by the MEM module are sent to a response mechanism (ORA) module for exclusive-OR comparison, so that whether the Mult characteristic function of the DSP module is normal or not can be known.

When the Postadder characteristic function of the DSP module is tested, the input excitation read by the MEM module and the output generated by the Mult logic are sent to the input port of the Postadder logic, and then the output result generated by the Postadder logic and the expected output result read by the MEM module are sent to a response mechanism (ORA) module for exclusive-OR comparison, so that whether the Postadder characteristic function of the DSP module is normal or not can be known.

Therefore, the four functions of each DSP module in the FPGA chip are verified by a uniform method, and all the characteristics of the DSP modules and the related functions thereof can be covered. Meanwhile, each DSP module performs corresponding logic processing on the read input excitation according to the current functional configuration, and the obtained corresponding output results can be divided into multiple groups, so that after the output results of each DSP module are respectively subjected to XOR comparison with the expected output results stored by the MEM module, the multiple groups of multi-bit XOR results of each DSP module are finally obtained.

Step S130: and sequentially carrying out feedback OR operation on the multiple groups of multi-bit XOR results of each DSP module to sequentially feed back the previous group of OR operation results and the next group of OR operation results, so that the multiple groups of multi-bit XOR results are finally reduced to one bit to be output to obtain the test result of each DSP module.

Specifically, since each DSP module is subjected to a function test, which at least covers four types of functions of the DSP module for verification, after the output result of each DSP module is subjected to xor comparison with the expected output result stored in the MEM module, a plurality of sets of multi-bit xor results are finally obtained, at this time, the test result of each DSP cannot be directly obtained from the plurality of sets of multi-bit xor results, and the plurality of sets of multi-bit xor results are sequentially subjected to feedback or operation to feed back the previous set of or operation results to the next set of or operation results, so that the plurality of sets of multi-bit xor results are finally reduced to one bit for output, so as to obtain the test result of each DSP module.

As shown in fig. 3, the result obtained by performing an OR operation on the previous group (multi-bit xor result) is fed back to perform an OR Operation (OR) on the subsequent group (multi-bit xor result) through a register. In the or operation, as long as any input has a 1 (i.e., a high level signal is input), the output result is 1 (i.e., a high level signal is output), so that as long as a certain bit in the multi-bit xor result is a high level signal (which represents that a certain function in the DSP module is abnormal), the test result is 1 (i.e., a high level signal is output), which represents that the DSP module has a functional abnormality. If and only if all the multi-bit exclusive-or results are low level signals (indicating that all functions in the DSP module are normal), the test result is 0 (i.e., outputting a low level signal), and at this time, the DSP module is indicated to be normal in function. Therefore, whether the function of the corresponding DSP module is abnormal can be known by detecting one bit of output signals of each DSP module.

Example two

As shown in fig. 4, a second embodiment of the present invention provides a method for testing a function of a DSP module in an FPGA chip, where the method for testing a function includes the following steps:

step S210: and performing the same function configuration on each DSP module in the FPGA chip, and reading input excitation to each DSP module through an MEM module in the FPGA chip.

Step S220: and respectively carrying out exclusive-OR comparison on the output result of each DSP module and the expected output result stored in the MEM module to obtain a plurality of groups of multi-bit exclusive-OR results of each DSP module.

Step S230: and sequentially carrying out feedback OR operation on the multiple groups of multi-bit XOR results of each DSP module to sequentially feed back the previous group of OR operation results and the next group of OR operation results, so that the multiple groups of multi-bit XOR results are finally reduced to one bit to be output to obtain the test result of each DSP module.

Step S240: and performing OR operation on the test results of all the DSP modules to obtain the DSP function test result of the FPGA chip.

Specifically, when we perform fast screening on the FPGA chip, we only need to know whether a certain DSP module is abnormal in function in the FPGA chip, and do not need to specifically know which DSP module is abnormal in function. At this time, as shown in fig. 1, the OR Operation (OR) may be performed on the test results of all the DSP modules, and since the OR operation is performed, if any input has 1 (i.e., a high level signal is input), the output result is 1 (i.e., a high level signal is output), so that if a certain bit of the test results of all the DSP modules is a high level signal (which represents a case where a certain DSP module has a functional abnormality), the test results are all 1 (i.e., a high level signal is output), and at this time, the DSP functional abnormality exists in the FPGA chip. If and only if the test results of all the DSP modules are low level signals (representing that all the DSP modules in the FPGA chip are normal in function), the test result is 0 (i.e., outputting a low level signal), and at this time, it represents that the DSP function of the FPGA chip is normal. Therefore, whether the DSP function of the FPGA chip is abnormal or not can be known through one-bit output, and the FPGA chip can be rapidly screened.

EXAMPLE III

As shown in fig. 5, a second embodiment of the present invention provides a method for testing a function of a DSP module in an FPGA chip, where the method for testing a function includes the following steps:

step S310: and performing the same function configuration on each DSP module in the FPGA chip, and reading input excitation to each DSP module through an MEM module in the FPGA chip.

Step S320: and respectively carrying out exclusive-OR comparison on the output result of each DSP module and the expected output result stored in the MEM module to obtain a plurality of groups of multi-bit exclusive-OR results of each DSP module.

Step S330: and sequentially carrying out feedback OR operation on the multiple groups of multi-bit XOR results of each DSP module to sequentially feed back the previous group of OR operation results and the next group of OR operation results, so that the multiple groups of multi-bit XOR results are finally reduced to one bit to be output to obtain the test result of each DSP module.

Step S340: and scanning the test result of each DSP module in sequence through the shift register chain so as to scan out the DSP module with abnormal function.

Specifically, if a specific DSP module in the FPGA chip is to be located, the problem of abnormal function may be solved by sequentially scanning the test result of each DSP module through a shift register chain, as shown in fig. 6, where the shift register chain includes a plurality of shift registers corresponding to each DSP module one to one. The test result of each DSP module is scanned in sequence through the shift register chain, namely each DSP module is scanned in sequence through the corresponding shift register, so that when an abnormal condition occurs in a certain DSP module, the abnormal condition is recorded by the corresponding shift register, and therefore, the problem of the function abnormality of the specific DSP module in the FPGA chip can be quickly positioned by checking the record of the shift register chain.

Example four

As shown in fig. 7, a functional testing apparatus 100 for a DSP module in an FPGA chip according to a fourth embodiment of the present invention includes an input excitation unit 110, an exclusive-or comparison unit 120, a first-level processing unit 130, a second-level processing unit 140, and an exception locating unit 150.

The input excitation unit 110 is mainly used for performing the same function configuration on each DSP module inside the FPGA chip, and reading the input excitation to each DSP module through the MEM module inside the FPGA chip. Specifically, the input driving unit 110 mainly drives the clock and the reset signal through the driving file, or drives the clock and the reset signal by using the signal source and the crystal oscillator, and during the test, it is required to ensure that the driving time is enough to read the input excitation in the MEM module and ensure the complete output comparison. Because the method generates the input excitation by reading the data stored in the MEM module and the output is compared in real time, when the input excitation unit 110 generates a counter of 10 bits, only the clock period is required to be guaranteed to be between 1024 and 1500.

When functional tests are to be performed on all the DSP modules in the FPGA chip, each DSP module needs to be configured with the same function so as to perform corresponding functional tests. Meanwhile, due to the programmable characteristic inside the FPGA chip, the inputs corresponding to all the DSP modules in the FPGA chip and the output of the MEM module can be connected together through the wiring resources inside the FPGA chip, that is, as shown in fig. 2. Thus, when the FPGA chip to be subjected to the function test is started to be in the wake-up state, the input excitation unit 110 can read the input excitation to each DSP module through the MEM module in the FPGA chip, so as to perform the function test on each DSP module.

The xor comparing unit 120 is mainly configured to perform xor comparison between the output result of each DSP module and the expected output result stored in the MEM module, so as to obtain multiple sets of multi-bit xor results of each DSP module. Specifically, since the input excitation unit 110 performs the same function configuration on each DSP module in the FPGA chip before reading the input excitation into each DSP module through the MEM module, at this time, each DSP module performs corresponding logic processing on the read input excitation according to the current function configuration to obtain a corresponding output result. The output results can be divided into a plurality of groups, and the output results can be different according to different input stimuli read by the current DSP module.

When testing the I/O characteristic function of the DSP module, the xor comparing unit 120 reads the input stimuli to the input port of the DSP module through the MEM module in the FPGA chip, and then sends the output result of the output port of the DSP module and the expected output result read from the MEM module to the response mechanism (ORA) module for xor comparison, so as to know whether the I/O characteristic function of the DSP module is normal.

When testing the preader characteristic function of the DSP module, the exclusive-or comparing unit 120 reads the input stimulus to the input port of the preader logic of the DSP module through the MEM module in the FPGA chip, and then sends the output result generated by the preader logic and the expected output result read from the MEM module to the response mechanism (ORA) module for exclusive-or comparison, so as to know whether the preader characteristic function of the DSP module is normal.

When testing the Mult feature function of the DSP module, the exclusive-or comparing unit 120 sends the input stimuli read by the MEM module and the output generated by the preader logic to the input port of the Mult logic, and then sends the output result generated by the Mult logic and the expected output result read by the MEM module to the response mechanism (ORA) module for exclusive-or comparison, so as to know whether the Mult feature function of the DSP module is normal.

When testing the posaddr feature function of the DSP module, the xor comparing unit 120 sends the input stimuli read by the MEM module and the output generated by the Mult logic to the input port of the posaddr logic, and then sends the output result generated by the posaddr logic and the expected output result read by the MEM module to the response mechanism (ORA) module for xor comparison, so as to know whether the posaddr feature function of the DSP module is normal.

In this way, the xor comparing unit 120 verifies the four types of functions of each DSP module in the FPGA chip by a uniform method, and can cover all the characteristics of the DSP module and the related functions thereof. Meanwhile, each DSP module performs corresponding logic processing on the read input stimuli according to the current functional configuration, and the obtained corresponding output results can be divided into multiple groups, so that the xor comparison unit 120 performs xor comparison on the output results of each DSP module and the expected output results stored in the MEM module, and finally obtains multiple groups of multi-bit xor results of each DSP module.

The primary processing unit 130 is mainly configured to perform a feedback or operation on the multiple sets of multi-bit xor results of each DSP module bit by bit, so as to sequentially feed back the previous or operation result and perform an or operation on the next bit, so that the multiple sets of multi-bit xor results are finally reduced to one bit for output, and a test result of each DSP module is obtained. Specifically, since the xor comparing unit 120 performs the function test on each DSP module, which at least needs to verify four types of functions covering the DSP module, after the output result of each DSP module is xor-compared with the expected output result stored in the MEM module, a multi-group multi-bit xor result is finally obtained, at this time, we cannot directly obtain the test result of each DSP from the multi-group multi-bit xor result, and also need to perform bit-by-bit feedback or operation on the multi-group multi-bit xor result through the primary processing unit 130 to sequentially feed back the previous group or operation result and the next group for or operation, so that the multi-group multi-bit xor result is finally reduced to one bit for output, so as to obtain the test result of each DSP module.

The secondary processing unit 140 is mainly used for performing or operation on the test results of all the DSP modules to obtain a function test result of the FPGA chip. Specifically, when we perform fast screening on the FPGA chip, we only need to know whether a certain DSP module is abnormal in function in the FPGA chip, and do not need to specifically know which DSP module is abnormal in function. At this time, as shown in fig. 1, the second-stage processing unit 140 performs an OR Operation (OR) on the test results of all the DSP modules, and since the OR operation is performed, if any input has a 1 (i.e., a high level signal is input), the output result is 1 (i.e., a high level signal is output), and thus, if a certain bit of the test results of all the DSP modules has a high level signal (which represents a case where a certain DSP module has a functional abnormality), the test results are all 1 (i.e., a high level signal is output), and at this time, the FPGA chip has a DSP functional abnormality. If and only if the test results of all the DSP modules are low level signals (representing that all the DSP modules in the FPGA chip are normal in function), the test result is 0 (i.e., outputting a low level signal), and at this time, it represents that the DSP function of the FPGA chip is normal. Therefore, whether the DSP function of the FPGA chip is abnormal or not can be known through one-bit output, and the FPGA chip can be rapidly screened.

The exception positioning unit 150 is mainly used for scanning the test result of each DSP module in sequence through the shift register chain to scan out the DSP module with an exception function. As shown in fig. 6, the shift register chain includes a plurality of shift registers corresponding to each DSP module. Specifically, if a problem that a specific DSP module in the FPGA chip is abnormal in function needs to be located, the abnormal location unit 150 needs to be used, and the abnormal location unit 150 sequentially scans the test result of each DSP module through the shift register chain, that is, sequentially scans each DSP module through the corresponding shift register, so that when an abnormal condition occurs in a scanned DSP module, the corresponding shift register records the abnormal condition, and thus, the problem that a specific DSP module in the FPGA chip is abnormal in function can be quickly located by checking the record of the shift register chain.

The function testing method and the function testing device for the DSP modules in the FPGA chip provided by the embodiment of the invention utilize the internal programmable characteristic of the FPGA chip, and read and excite the inputs of all the DSP modules in the FPGA chip into each DSP module through the MEM module by connecting the corresponding inputs of all the DSP modules in the FPGA chip with the output of the MEM module. And then, the output result of each DSP module is respectively subjected to exclusive-OR comparison with the expected output result stored by the MEM module to obtain a plurality of groups of multi-bit exclusive-OR results of each DSP module. And finally, performing feedback type OR operation on the multi-group multi-bit XOR result of each DSP module bit by bit, so that the multi-group multi-bit XOR result is finally reduced to one bit to be output, and the test result of each DSP module is obtained. Therefore, the requirements on the test conditions can be reduced to the maximum extent, and the function test of all DSP modules in the FPGA chip can be completed only by means of the MEM module in the FPGA chip, so that the functional correctness of all DSP modules in the FPGA chip is ensured, and when the actual FPGA chip has problems, the functional errors of the DSP modules in the FPGA chip can be rapidly positioned.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.

Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.

The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims

1. A function test method of a DSP module in an FPGA chip is characterized by comprising the following steps:

the method comprises the steps of carrying out the same function configuration on each DSP module in an FPGA chip, and reading input excitation to each DSP module through an MEM module in the FPGA chip;

performing exclusive-or comparison on the output result of each DSP module and the expected output result stored in the MEM module to obtain a plurality of groups of multi-bit exclusive-or results of each DSP module;

sequentially carrying out feedback type OR operation on the multiple groups of multi-bit XOR results of each DSP module to sequentially feed back the previous group of OR operation results and the next group of OR operation results, and finally reducing the multiple groups of multi-bit XOR results to one-bit output to obtain the test result of each DSP module;

the step of performing the same function configuration on each DSP module inside the FPGA chip and reading the input stimuli to each DSP module through the MEM module inside the FPGA chip specifically includes:

performing the same function configuration on each DSP module, and connecting the corresponding inputs of all DSP modules in the FPGA chip and the output of the MEM module together by using internal wiring resources in the FPGA chip;

and after the FPGA chip is started to be in an awakening state, the MEM module reads input excitation to each DSP module.

2. The functional test method of claim 1, wherein the functions of the DSP module include an I/O characteristic function, a preader characteristic function, a Mult characteristic function, and a postladder characteristic function.

3. The functional test method of claim 1, further comprising the steps of:

and performing OR operation on the test results of all the DSP modules to obtain a DSP function test result of the FPGA chip.

4. The functional test method of claim 1, further comprising the steps of:

and scanning the test result of each DSP module in sequence through a shift register chain so as to scan the DSP module with abnormal function.

5. The functional test method of claim 4, wherein the shift register chain comprises a plurality of shift registers in one-to-one correspondence with each of the DSP modules.

6. The utility model provides a function test device of DSP module in FPGA chip which characterized in that, function test device includes:

the FPGA chip comprises an input excitation unit, an MEM module and a plurality of DSP modules, wherein the input excitation unit is used for performing same function configuration on each DSP module in the FPGA chip and reading input excitation to each DSP module through the MEM module in the FPGA chip, specifically, performing the same function configuration on each DSP module and connecting the corresponding inputs of all the DSP modules in the FPGA chip and the output of the MEM module by using internal wiring resources in the FPGA chip, and reading the input excitation to each DSP module through the MEM module after the FPGA chip is started to be in a wake-up state;

an exclusive-or comparison unit, configured to perform exclusive-or comparison on the output result of each DSP module and an expected output result stored in the MEM module, respectively, to obtain multiple sets of multi-bit exclusive-or results of each DSP module;

and the primary processing unit is used for sequentially carrying out feedback OR operation on the multi-group multi-bit XOR result of each DSP module so as to sequentially feed back the former group OR operation result and the latter group OR operation result, so that the multi-group multi-bit XOR result is finally reduced to one bit to be output to obtain the test result of each DSP module.

7. The function test apparatus of claim 6, wherein the functions of the DSP module include an I/O characteristic function, a Preader characteristic function, a Mult characteristic function, and a Postader characteristic function.

8. The functional test device according to claim 6, further comprising a secondary processing unit for performing an or operation on the test results of all the DSP modules to obtain the functional test result of the FPGA chip.

9. The functional test device according to claim 6, further comprising an exception positioning unit for scanning the test result of each of the DSP modules in turn through a shift register chain to scan out the DSP module with an exception function; the shift register chain comprises a plurality of shift registers which correspond to the DSP modules one by one.