CN107924936A - 具有二维分布的场效应晶体管单元的场效应晶体管 - Google Patents
具有二维分布的场效应晶体管单元的场效应晶体管 Download PDFInfo
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Abstract
一种场效应晶体管(FET),所述场效应晶体管具有:多个FET单元,所述多个FET单元具有被布置在衬底的表面上的多个源极焊盘、多个漏极焊盘以及多个栅电极;所述FET单元中的每一个FET单元具有所述栅电极的其中一个相应的栅电极,所述相应的栅电极被布置在所述源极焊盘的其中一个源极焊盘与所述漏极焊盘的其中一个漏极焊盘之间;被连接至所述FET单元中的每一个FET单元的栅电极的栅极触点;被连接至所述FET单元中的每一个FET单元的漏极焊盘的漏极触点;被连接至所述FET单元中的每一个FET单元的源极焊盘的源极触点。所述FET单元在表面上呈二维阵列布置。
Description
技术领域
本公开总体上涉及场效应晶体管(FET),尤其涉及用于这些FET的改进布局。
背景技术
如在本领域中已知的,具有多个FET单元的线性阵列的场效应晶体管(FET)被用于许多场合。每一个FET单元具有源极、漏极以及位于源极和漏极之间的栅极,栅极用于控制载流子沿着源极和漏极之间的沟道的流动。还应该理解到,在任何电路应用中,源极和漏极可以颠倒;在任一电路应用中,栅极控制载流子在源极和漏极之间的流动。
又如在本领域中已知的,在一些FET中,栅极是互连至位于衬底的顶部表面上的共用栅极触点的平行指状栅极。类似地,各个漏极被连接至共用漏极触点电极,源极通过跨越栅极指状部并且或者跨越漏极或者跨越源极的空气桥连接至共用源极触点,其中空气桥在它们的端部处通过导电过孔连接至位于衬底的底部表面上的共用漏极或源极触点(未示出),导电过孔在空气桥的端部和底部表面上的触点之间竖直穿过衬底。图1示出了具有跨越漏极的空气桥的一个这种FET。如图2A所示,许多这种FET单元通常在功率放大型单片微波集成电路(MMIC)的输出级中呈线性阵列地堆叠在一起。这些FET单元的线性堆叠决定了MMIC的线性L尺寸大小。
发明内容
根据本公开,提供了一种场效应晶体管(FET),所述场效应晶体管具有:多个FET单元,所述多个FET单元具有被布置在衬底的表面上的多个源极焊盘、多个漏极焊盘以及多个栅电极;所述FET单元中的每一个FET单元具有所述栅电极的其中一个相应的栅电极,所述相应的栅电极被布置在所述源极焊盘的其中一个源极焊盘与所述漏极焊盘的其中一个漏极焊盘之间;被连接至所述FET单元中的每一个FET单元的栅电极的栅极触点;被连接至所述FET单元中的每一个FET单元的漏极焊盘的漏极触点;被连接至所述FET单元中的每一个FET单元的源极焊盘的源极触点。所述(多个)FET单元在表面上呈二维阵列布置。
本发明人已经认识到:FET单元的线性布置会产生散热的“群聚(bunching)”,并且会在FET中产生高的沟道温度。本发明人通过将这些单元呈二维阵列地布置来解决这个问题。
在一个实施例中,FET单元呈U形排列布置。
在一个实施例中,所述单元中的一部分沿着一条线布置,并且所述单元中的另一部分沿着相交线布置。
在一个实施例中,提供了一种场效应晶体管(FET),所述场效应晶体管具有:多个指状栅电极,所述多个指状栅电极被电互连至沿着共用栅极触点的边缘相继排布的点,所述指状栅电极中的第一部分沿着竖直方向延伸,并且所述指状栅电极中的第二部分沿着与所述竖直方向相交的方向延伸。
在一个实施例中,与所述竖直方向相交的所述方向是水平方向。
在一个实施例中,所述多个指状栅电极中的第三部分;所述第一部分和所述第二部分被连接至所述共用栅极触点的相对边缘。
在一个实施例中,所述多个指状栅电极中的第三部分被电互连至沿着所述共用栅极触点相继排布的点,并且沿着所述竖直方向延伸;所述第一部分被连接至沿着所述共用栅极触点的所述边缘的一部分的点,并且所述第二部分被连接至沿着所述共用栅极触点的所述边缘的相对部分的点。
通过这种布置,FET的FET单元被布置成三个区段,其中FET栅极被竖直地、例如沿着竖直或y维地排列成两个区段,并且水平地排列成一个区段。通过形成这三个区段,所产生的热量具有更大的非共用表面区域(unshared surface area)以便在其上扩散并由此消散。这种布局优化了栅极和漏极指状部的相位匹配,使得功率和效率最大化。为了使功率最大化,通常需要使每个FET单元的从增益输入到漏极输出的***相位在10度以内。无需额外的直流电流而使功率最大化,由此也提高了效率。通过减小源极电感来使增益最大化。总的源极电感由接地的过孔以及位于衬底顶部的互连金属限定。在传统的空气桥中,位于空气桥两端的竖直导电过孔仅提供两个过孔,在此,例如在U形的实施例中,存在四个过孔,它们极大地减小了FET的整体源极电感。此外,由于这种布局允许较小的竖直尺寸以及较小的整体半导体材料,由此降低了MMIC的成本。对水平和竖直延伸的栅极的组合的使用提供了一种具有三个分立区段的FET,这三个分立区段被连接以降低源极电感。
在附图和以下的描述中阐述了本公开的一个或多个实施例的细节。根据描述和附图以及根据权利要求,本公开的其它特征、目的和优点将是显而易见的。
附图说明
图1是根据现有技术的场效应晶体管(FET)的俯视图;
图2A是图1的根据现有技术的FET(在此为八个)的线性阵列的俯视平面图;
图2B示出了由每个FET所产生的热在图2A的根据现有技术的线性阵列中的八个FET上的热特征或空间位置;
图3A是根据本公开的场效应晶体管(FET)的平面图;
图3B是图3A的根据本公开的FET的一部分的横截面图,该横截面沿着图3A的线3B-3B截取;
图3C是图3A的根据本公开的FET的透视图;
图4A是图1的根据本公开的FET(在此为八个)的线性阵列的俯视图;以及
图4B示出了由每个FET所产生的热在图4A的根据本公开的线性阵列中的八个FET上的热特征或空间位置。
在各个附图中,相似的附图标记表示相似的元件。
具体实施方式
现在参考图3A至图3C,场效应晶体管(FET)10被示出为具有多个(在此为12个)FET单元121-1212,FET单元121-1212中的每一个FET单元分别具有:源极S;漏极D;以及栅极G1-G12,其中每个栅极G1-G12是细长的指状栅极、被布置在源极S和漏极D之间以控制载流子沿着源极S和漏极D之间的沟道的流动;图3B示出了FET单元121-124。在此,FET 10利用光刻化学蚀刻工艺形成。具体而言,如图3A所示,FET单元121-1212中的每一个FET单元具有位于半导体衬底15的上部平坦表面13上的十二个栅电极G1-G12的其中一个相应的栅电极,其中该半导体衬底15例如为具有氮化镓(GaN)的衬底,该十二个栅电极G1-G12分别与该半导体衬底15的表面13肖特基接触。如图3A所示,FET 10包括:与半导体衬底15的表面13欧姆接触的六个漏极焊盘201-206;以及与半导体衬底15的表面13欧姆接触的七个源极焊盘221-227。应当指出,每个栅极指状部G1-G12共用由漏极焊盘201-206的其中一个漏极焊盘提供的漏极(D)以及由源极焊盘221-227的其中一个相邻的漏极焊盘提供的源极(S)。因此,源极焊盘221给FET单元121提供源极(S),源极焊盘222给FET单元122及123提供源极(S);源极焊盘223给FET单元124及125提供源极(S);源极焊盘224给FET单元126及127提供源极(S);源极焊盘225给FET单元128及129提供源极(S);源极焊盘226给FET单元1210及1211提供源极(S);源极焊盘227给FET单元1212提供源极(S)。类似地,漏极焊盘201给FET单元121及122提供漏极(D);漏极焊盘202给FET单元123及124提供漏极(D);漏极焊盘203给FET单元125及126提供漏极(D);漏极焊盘204给FET单元127及128提供漏极(D);漏极焊盘205给FET单元129及1210提供漏极(D);漏极焊盘206给FET单元1211及1212提供漏极(D)。因此,在FET单元121-1212中的每一个FET单元的源极(S)和漏极(D)之间布置有十二个栅极G1-G12的其中一个栅极。因此,如图3A所示,栅极G1被布置在源极焊盘221和漏极焊盘201之间;栅极G2被布置在源极焊盘222和漏极焊盘201之间;栅极G3被布置在源极焊盘222和漏极焊盘202之间;栅极G4被布置在源极焊盘223和漏极焊盘202之间;栅极G5被布置在源极焊盘223和漏极焊盘203之间;栅极G6被布置在源极焊盘224和漏极焊盘203之间;栅极G7被布置在源极焊盘224和漏极焊盘204之间;栅极G8被布置在源极焊盘225和漏极焊盘204之间;栅极G9被布置在源极焊盘225和漏极焊盘205之间;栅极G10被布置在源极焊盘226和漏极焊盘205之间;栅极G11被布置在源极焊盘226和漏极焊盘206之间;栅极G12被布置在源极焊盘227和漏极焊盘206之间。
如图3A所示,FET 10包括:栅极触点14,该栅极触点14被连接至FET单元121-1212中的每个FET单元的栅极G1-G12;漏极触点16,该漏极触点16被连接至漏极焊盘201-206中的每一个漏极焊盘。源极焊盘221-227通过空气桥26电互连,空气桥26在图3C中被更清晰地示出。如图3A至图3C所示,源极触点18(图3A至图3C)被布置在衬底15(图3B)的底部上,并且通过穿过该衬底15的导电过孔28连接至源极焊盘221、223、225以及227。
具体而言,并且参考图3B,单元14在X-Y平面(图3A和图3B)上呈二维阵列布置在基板15的上表面13上。指状栅电极G1-G12被电互连至沿着共用栅极触点14的边缘相继排布的点P。应当指出,由指状栅电极G1-G4组成的第一部分30沿着竖直方向或Y方向(图3A)延伸,由指状栅电极G5-G8组成的第二部分32沿着与该竖直方向相交的方向延伸,在此该竖直方向例如为水平方向或X方向。应当指出,由多个指状栅电极G9-G12组成的第三部分34沿着竖直方向或-Y方向(图3A)延伸。该第一部分30和该第三部分34被连接至共用栅极触点14的相对边缘,并且在相反的方向上延伸。因此,在这个示例中,FET 10是U形FET 10。
现在参考图2和图4A,应当指出,与图1的FET相比,其中每个具有十二个FET单元的八个FET 10(图3A)的阵列的竖向(沿着Y轴)尺寸占据较小的竖向(Y轴)尺寸。还应当指出,在将图3A的八个FET 10的阵列的热特征与图1中的FET的阵列的热特征(图2B)作比较时,图3A的FET 10的阵列的热量二维(X方向和Y方向,图4B)地分布,因此所产生的热量具有更大的非共用表面区域以便在其上扩散并由此消散。
已经对本公开的多个实施例进行了描述。然而,应当理解到,在不脱离本公开的精神和范围的情况下,可以作出各种修改。例如,除了U形FET单元外,也可以使用FET单元在其中二维地分布的其它形状,例如V形FET单元、杯形单元、凹形单元、抛物线形单元。此外,在任何电路应用中,源极和漏极可以颠倒;在任一电路应用中,栅极控制载流子在源极和漏极之间的流动。
现在应当认识到,根据本公开的场效应晶体管(FET)包括:具有被布置在衬底的表面上的多个源极焊盘、多个漏极焊盘以及多个栅电极的多个FET单元;所述FET单元中的每一个FET单元具有所述栅电极的其中一个相应的栅电极,所述相应的栅电极被布置在所述源极焊盘的其中一个源极焊盘与所述漏极焊盘的其中一个漏极焊盘之间;被连接至所述FET单元中的每一个FET单元的栅电极的栅极触点;被连接至所述FET单元中的每一个FET单元的漏极焊盘的漏极触点;被连接至所述FET单元中的每一个FET单元的源极焊盘的源极触点,其中,所述FET单元在表面上呈二维阵列布置。所述FET可以包括以下特征中的一个或多个、独立于另一个特征或者与另一个特征组合,这些特征包括:FET单元呈非线性阵列布置;FET单元呈U形排列布置;或者所述单元中的一部分沿着一条线布置,并且所述单元中的另一部分沿着相交线布置。
现在还应当认识到,根据本公开的场效应晶体管(FET)包括:多个指状栅电极,所述多个指状栅电极被电互连至沿着共用栅极触点的边缘相继排布的点,所述指状栅电极中的第一部分沿着竖直方向延伸,并且所述指状栅电极中的第二部分沿着与所述竖直方向相交的方向延伸。FET包括以下特征中的一个或多个、独立于另一个特征或者与另一个特征组合,这些特征包括:与所述竖直方向相交的所述方向是水平方向;所述第一部分和所述第二部分被连接至所述共用栅极触点的相对边缘;所述多个指状栅电极中的第三部分被电互连至沿着所述共用栅极触点相继排布的点,并且沿着所述竖直方向延伸;所述第一部分被连接至沿着所述共用栅极触点的所述边缘的一部分的点,并且所述第三部分被连接至沿着所述共用栅极触点的所述边缘的相对部分的点。
因而,其它实施例落在下述权利要求的范围内。
Claims (8)
1.一种场效应晶体管(FET),包括:
具有被布置在衬底的表面上的多个源极焊盘、多个漏极焊盘以及多个栅电极的多个FET单元;所述FET单元中的每一个FET单元具有所述栅电极的其中一个相应的栅电极,所述相应的栅电极被布置在所述源极焊盘的其中一个源极焊盘与所述漏极焊盘的其中一个漏极焊盘之间;被连接至所述FET单元中的每一个FET单元的栅电极的栅极触点;
被连接至所述FET单元中的每一个FET单元的漏极焊盘的漏极触点;
被连接至所述FET单元中的每一个FET单元的源极焊盘的源极触点;
其中,所述FET单元在表面上呈二维阵列布置。
2.根据权利要求1所述的场效应晶体管(FET),其特征在于,所述FET单元呈非线性阵列布置。
3.根据权利要求1所述的场效应晶体管(FET),其特征在于,所述FET单元呈U形排列布置。
4.根据权利要求1所述的场效应晶体管(FET),其特征在于,所述FET单元中的一部分沿着一条线布置,并且所述FET单元中的另一部分沿着相交线布置。
5.一种场效应晶体管(FET),包括:
多个指状栅电极,所述多个指状栅电极被电互连至沿着共用栅极触点的边缘相继排布的点,所述指状栅电极中的第一部分沿着竖直方向延伸,并且所述指状栅电极中的第二部分沿着与所述竖直方向相交的方向延伸。
6.根据权利要求5所述的场效应晶体管(FET),其特征在于,与所述竖直方向相交的所述方向是水平方向。
7.根据权利要求5所述的场效应晶体管,其特征在于,所述第一部分和所述第二部分被连接至所述共用栅极触点的相对边缘。
8.根据权利要求5所述的场效应晶体管,其特征在于,所述多个指状栅电极中的第三部分被电互连至沿着所述共用栅极触点相继排布的点,并且沿着所述竖直方向延伸;所述第一部分被连接至沿着所述共用栅极触点的所述边缘的一部分的点,并且所述第三部分被连接至沿着所述共用栅极触点的所述边缘的相对部分的点。
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US11574854B2 (en) * | 2020-04-08 | 2023-02-07 | National Research Council Of Canada | Distributed inductance integrated field effect transistor structure |
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