CN107918596B - SOC chip and radio frequency signal processing method - Google Patents
SOC chip and radio frequency signal processing method Download PDFInfo
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- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7817—Specially adapted for signal processing, e.g. Harvard architectures
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
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- G06F1/32—Means for saving power
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- G06Q20/00—Payment architectures, schemes or protocols
- G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
- G06Q20/32—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using wireless devices
- G06Q20/327—Short range or proximity payments by means of M-devices
- G06Q20/3278—RFID or NFC payments by means of M-devices
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- H—ELECTRICITY
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- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/02—Power saving arrangements
- H04W52/0209—Power saving arrangements in terminal devices
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention discloses an SOC chip and a radio frequency signal processing method, wherein the SOC chip comprises: the system comprises a non-access module coprocessor and a non-access communication module, wherein the non-access communication module is electrically connected with the non-access module coprocessor and comprises a preliminary wake-up module and a clock data recovery module; the preliminary wake-up module is electrically connected with the non-connected module coprocessor and is used for detecting the field intensity of the radio frequency field where the SOC chip is located, and sending a first wake-up instruction to the non-connected module coprocessor when the field intensity is detected to be larger than a preset value; a non-access module coprocessor electrically connected with the clock data recovery module; the clock data recovery module is used for entering a working state according to a first wake-up instruction, extracting a clock signal of an input radio frequency signal and sending a wake-up instruction signal to the non-connected module coprocessor according to the clock signal; and the non-connected module coprocessor is also used for determining whether to wake up the SOC chip according to the wake-up indication signal. The power consumption of the SOC chip is reduced.
Description
Technical Field
The embodiment of the invention relates to a wireless communication technology, in particular to an SOC chip and a radio frequency signal processing method.
Background
With the continuous development of wireless communication technology, the application of the payment mode of NFC (Near Field Communication ) is more and more widespread, and the NFC front-end chip is integrated in the intelligent terminal such as the intelligent mobile phone and the intelligent bracelet, so that the intelligent terminal has functions of NFC payment and the like, and the convenience of user payment is improved.
However, when the radio frequency front end chip is arranged on the intelligent terminal, with the improvement of the complexity of the application environment, in order to meet the payment requirement of the radio frequency chip, an operating system is added in the radio frequency chip to cooperate with a host to operate, but due to the increase of the operating system and the like, the power consumption of the radio frequency chip is overlarge, and the user experience is poor.
Disclosure of Invention
The invention provides an SOC chip and a radio frequency signal processing method, which are used for reducing the power consumption of the radio frequency chip.
In a first aspect, an embodiment of the present invention provides an SOC chip including: a non-access module coprocessor and a non-access communication module, wherein,
the non-connection communication module is electrically connected with the non-connection module coprocessor and comprises a preliminary awakening module and a clock data recovery module;
the preliminary wake-up module is electrically connected with the non-connected module coprocessor and is used for detecting the field intensity of the radio frequency field where the SOC chip is located, and sending a first wake-up instruction to the non-connected module coprocessor when the field intensity is detected to be larger than a preset value;
The non-connected module coprocessor is electrically connected with the clock data recovery module and is used for sending the first wake-up instruction to the clock data recovery module;
the clock data recovery module is used for entering a working state according to the first wake-up instruction, extracting a clock signal of an input radio frequency signal, and sending a wake-up instruction signal to the non-connected module coprocessor according to the clock signal;
the non-connected module coprocessor is further used for determining whether to wake up the SOC chip according to the wake-up indication signal.
In a second aspect, an embodiment of the present invention further provides a radio frequency signal processing method, where the method includes:
acquiring an input radio frequency signal and acquiring the signal strength of the input radio frequency signal;
if the signal intensity is detected to be larger than a preset value, a first wake-up instruction is generated, and the SOC chip is electrified according to the first wake-up instruction;
and extracting a clock signal of the input radio frequency signal, judging whether the clock signal is in a stable state according to a preset rule, generating a wake-up instruction according to a judging result, and determining whether to wake up the SOC chip according to the wake-up instruction.
According to the embodiment of the invention, the primary wake-up module and the clock data recovery module are used for respectively detecting the field intensity of the input radio frequency signal and the clock signal, and the secondary wake-up mechanism is arranged, so that the SOC chip can be substantially waken only when the SOC chip is in a stable radio frequency field, the problems of frequent false start and overlarge power consumption of the SOC chip caused by higher sensitivity of the SOC chip or more external noise signals are solved, and the power consumption of the SOC chip is reduced.
Drawings
FIG. 1 is a schematic diagram of an SOC chip according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an SOC chip according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a non-communication module according to a first embodiment of the present invention;
fig. 4 is a flowchart of a radio frequency signal processing method according to a second embodiment of the present invention;
fig. 5 is a flowchart of a radio frequency signal processing according to a second embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Example 1
Fig. 1 is a schematic structural diagram of an SOC chip according to an embodiment of the present invention, where the SOC chip may be integrated in an intelligent terminal such as a smart phone, a bracelet, or a smart watch, and may be used as a radio frequency analog tag to implement a secure and reliable NFC (Near Field Communication ) payment function.
Referring to fig. 1, the SOC (System on Chip) Chip specifically includes: a non-interfacing module coprocessor 110 and a non-interfacing communication module 120.
The non-access communication module 120 is electrically connected with the non-access module coprocessor 110 and comprises a preliminary wake-up module 121 and a clock data recovery module 122;
the preliminary wake-up module 121 is electrically connected with the non-connected module coprocessor 110 and is used for detecting the field intensity of the radio frequency field where the SOC chip is located, and sending a first wake-up instruction to the non-connected module coprocessor 110 when the field intensity is detected to be larger than a preset value;
the non-access module coprocessor 110 is electrically connected with the clock data recovery module 122 and is used for sending a first wake-up instruction to the clock data recovery module 122;
the clock data recovery module 122 is configured to enter an operating state according to the first wake-up instruction, extract a clock signal of an input radio frequency signal, and send a wake-up instruction signal to the non-access module coprocessor 110 according to the clock signal;
The non-access module coprocessor 110 is further configured to determine whether to wake up the SOC chip according to the wake-up indication signal.
In this embodiment, the preliminary wake-up module may be connected to a terminal antenna, and may acquire a radio frequency input signal, and detect, by using the radio frequency input signal, a field strength of a radio frequency field where the SOC chip is located. For example, if the field strength is greater than the preset value, the SOC chip is indicated to be located in the radio frequency field, and the SOC chip is primarily awakened, otherwise, the SOC chip is indicated not to be located in the radio frequency field, and the state of the SOC chip not awakened is continuously maintained.
In this embodiment, when detecting that the SOC chip is located in the radio frequency field, the preliminary wake-up module 121 sends a first wake-up instruction to the non-connected module coprocessor 110, and the non-connected module coprocessor 110 receives the first wake-up instruction and sends the first wake-up instruction to each module of the SOC chip, so as to perform preliminary wake-up on each module of the SOC chip, where preliminary wake-up refers to performing power-up processing on each module, and illustratively, each module may complete output wake-up in hundreds of microseconds.
After the clock data recovery module 122 is primarily awakened, it receives an input rf signal, extracts a clock signal of the input rf signal, detects whether the clock signal is a clock signal with clutter, i.e. determines whether the clock signal is a stable clock signal, and determines an awakening indication signal according to a detection result, where the clutter signal may be a noise signal. The wake-up indication signal may be a second wake-up signal or a cancel wake-up signal, for example, if a clutter signal exists in the clock signal, the cancel wake-up signal is generated, and wake-up of the SOC chip is cancelled; if no clutter signal exists in the clock signal, a second wake-up signal is generated, and secondary wake-up is carried out on the SOC chip.
According to the technical scheme, the primary wake-up module and the clock data recovery module are used for respectively detecting the field intensity and the clock signal of the input radio frequency signal, the secondary wake-up mechanism is set, the SOC chip can be substantially waken only when the SOC chip is in the stable radio frequency field, the problems that the SOC chip is frequently started by mistake and the power consumption is overlarge due to the fact that the sensitivity of the SOC chip is high or the external noise signals are large are solved, and the power consumption of the SOC chip is reduced are solved.
Optionally, the preliminary wake-up module 121 includes a field strength detection circuit 1211 and a power management unit 1212; wherein,
the field strength detection circuit 1211 is electrically connected with the power management unit 1212 and is used for detecting the field strength of the input radio frequency signal, and sending a first starting instruction to the power management unit 1212 when detecting that the field strength of the input radio frequency signal is greater than a preset value;
the power management unit 1212 is electrically connected to the non-access module coprocessor 110, and the user enters an operating state according to the first start instruction and sends a first wake-up instruction to the non-access module coprocessor 110.
In this embodiment, the field intensity of the input radio frequency signal is detected by the field intensity detection circuit 1211. The power management unit 1212 is configured to perform power-on management on the SOC chip, and after being started according to the first start instruction, send a first wake-up instruction to the non-connected module coprocessor 110 to perform preliminary wake-up on each module of the SOC chip, that is, when the SOC chip does not enter the radio frequency field, each module of the SOC chip is in a non-power-on state, so that power consumption of each module when not in the radio frequency field is reduced, and power consumption of the SOC chip is further reduced.
Optionally, the clock data recovery module 122 is specifically configured to: acquiring frequency information and amplitude information of a clock signal, and determining whether the frequency information meets a first preset condition and whether the amplitude information meets a second preset condition; if yes, a second wake-up signal is generated, and if not, a cancel wake-up signal is generated.
The clock data recovery module 122 determines whether the SOC chip is within a stable rf field by identifying the frequency signal and the amplitude information of the clock signal. In this embodiment, the first preset condition may be that the frequency information is within a preset frequency range and has regularity, for example, the frequency information has periodicity or no irregular mutation exists. The second preset condition may be that the amplitude information is within a preset amplitude range and has regularity, for example, the amplitude information has periodicity or no irregular mutation exists.
The non-interface module coprocessor 110 is specifically configured to: waking up the SOC chip according to the second wake-up signal, and processing the input radio frequency signal; or, carrying out power-down processing on the SOC chip according to the cancel wake-up signal.
In this embodiment, the non-access module coprocessor 110 does not receive the second wake-up instruction within a preset time after receiving the first wake-up instruction, or determines that the SOC chip does not enter a stable rf field when receiving the cancel wake-up signal, and performs power-down processing on the SOC chip. Wherein the preset time may be a preset millisecond.
In this embodiment, whether the SOC chip is woken up is determined by accurately inputting whether the radio frequency signal is a stable signal, instead of only based on whether the radio frequency field is performed, so that the situation that the SOC chip is not started is reduced, and power consumption caused by false start is reduced.
In this embodiment, the SOC chip further includes a CPU (Central Processing Unit ) core 130, a peripheral bus (Advanced Peripheral Bus, APB) 150, an advanced high performance bus (Advanced High Performance Bus, AHB) 140, and an AHB to APB bus bridge 160. The CPU core is used for responding to communication information of external equipment and is connected with the AHB bus, the AHB bus and the APB bus are connected based on an AHB to APB bus bridge, the AHB bus can be connected with a plurality of high-speed peripherals, and the APB bus can be connected with a plurality of low-speed peripherals. Referring to fig. 2, fig. 2 is a schematic structural diagram of an SOC chip according to an embodiment of the present invention.
Optionally, the system further includes a global clock management module 170, electrically connected to the AHB bus 140, configured to generate a modulated clock signal according to the reference clock signal and a configuration file sent by the CPU core, and adjust a clock frequency of the APB bus according to the modulated clock signal, and an operating state of a peripheral device electrically connected to the APB bus, where the configuration file includes operating clock information of the APB bus and the peripheral device.
The reference clock signal is preset in the global clock management module 170, and may be related to physical properties of each peripheral device, for example. The configuration file is determined by the CPU core in real time according to the running states of the APB bus and the peripheral devices. The global clock management module 170 combines the configuration information and the reference clock signals to generate modulated clock signals of the APB bus and each peripheral device, and adjusts the frequency of PCLK of the APB bus and the operating state of the peripheral device connected to the APB bus according to the modulated clock signals through the AHB to APB bus bridge 160, wherein the operating state includes an enable state and an off state.
It should be noted that, the global clock management module 170 and the CPU core are both powered up according to the first wake-up signal, and powered down according to the cancel wake-up signal.
In this embodiment, the global clock management module is configured to control the clock frequency of the APB bus and the working state of the peripheral connected to the APB bus, so that each peripheral is turned off in a non-working state, and power consumption caused by that each peripheral is in an enabled state for a long time is reduced.
Optionally, the CPU core 130 is a 16/32bit mixed instruction CPU core.
The 16/32bit mixed instruction CPU core has the following two dimensions: the method comprises the steps of 16bit instructions and 32bit instructions, wherein the 16bit instructions have small running power consumption and low running speed, and correspondingly, the 32bit instructions have large running power consumption and high running speed. The CPU core 130 determines different operating dimensions based on different operating states. The CPU core 130 obtains current operating parameters, which may include, but are not limited to, an address range and an operand length. Illustratively, if the address range is less than the first threshold or the operand length is less than the second threshold, the CPU core 130 executes a 16bit instruction; if the address range is greater than or equal to the first threshold value and the operand length is greater than or equal to the second threshold value, the CPU core 130 executes a 32bit instruction.
In this embodiment, the operation dimension of the CPU core is determined according to the current operation parameter, and the operation frequency of the 16bit instruction is greater than the operation frequency of the 32bit instruction, so that the operation speed and the operation power consumption are both considered, and the total operation power consumption is reduced.
Optionally, the non-communication module 120 further comprises a variable gain amplifier 123, an indication circuit 124 and an analog demodulator 125. Referring to fig. 3, fig. 3 is a schematic structural diagram of a non-communication module according to a first embodiment of the present invention. Wherein,
a variable gain amplifier 123 for amplifying an input radio frequency signal according to a current gain in an awake state and outputting a carrier signal;
the indicating circuit 124 is electrically connected with the variable gain amplifier 123 and the non-connected module coprocessor respectively, and is used for extracting a first voltage of the carrier signal, generating an indicating signal according to the first voltage and an internal reference voltage, and sending the indicating signal to the non-connected module coprocessor;
the analog demodulator 125 is electrically connected with the variable gain amplifier 123 and the non-connection module coprocessor, and is used for analyzing the carrier signal and sending the generated analysis instruction to the non-connection module coprocessor;
the non-module coprocessor 110 is electrically connected with the CPU core 130 based on the APB bus 150 and the AHB bus 140, and is further configured to send an instruction signal and an analysis instruction to the CPU core 130, where the APB bus 150 and the AHB bus 140 are connected through an AHB to APB bus bridge 160;
The CPU core 130 is configured to generate a gain adjustment signal according to the indication signal, send the gain adjustment signal to the non-access module coprocessor 110, and generate a return parameter according to a corresponding parsing instruction when the indication signal meets a preset condition;
the non-access module coprocessor 110 is electrically connected to the variable gain amplifier 123, and is further configured to send a gain adjustment signal to the variable gain amplifier 123, so that the variable gain amplifier 123 adjusts the current gain, and performs signal amplification on the input radio frequency signal according to the first amplification gain generated by the adjustment.
In this embodiment, the variable gain amplifier 123 has a function of variable gain, and can amplify the input rf signal to different degrees according to different amplification gains. The input radio frequency signal may be, for example, a radio frequency signal transmitted by a reader, carrying interaction instructions. Where the current gain refers to the gain stored in the variable gain amplifier 123 when the input radio frequency signal is input to the variable gain amplifier 123.
When receiving an input rf signal, the variable gain amplifier 123 amplifies the rf signal according to the current gain to generate a carrier signal, which also carries the interaction instruction of the input rf signal. The output of the variable gain amplifier 123 is connected to the input of the indication circuit 124, and the carrier signal is sent to the indication circuit 124, and the indication circuit 124 extracts a first voltage of the carrier signal, where the first voltage may be an envelope of the carrier signal. Alternatively, the indication circuit 124 may be an RSSI (Received Signal Strength Indication ) indicator. The indication circuit 124 operates on the principle that the first voltage of the carrier signal is compared with the internal reference voltage, and a 2bit indication signal is generated based on the comparison result. For example, if the indication signal generated by the indication circuit 124 is 01 or 10, the carrier signal is indicated to be in a normal state, and it is further known that the input rf signal is in a normal state, and the current gain of the variable gain amplifier 123 does not need to be adjusted; if the indication signal generated by the indication circuit 124 is 00, the carrier signal becomes smaller, and it is further known that the input rf signal becomes smaller and the current gain of the variable gain amplifier 123 needs to be increased; if the indication signal generated by the indication circuit 124 is 11, it indicates that the carrier signal is large, and it is further known that the input rf signal is large, and the current gain of the variable gain amplifier 123 needs to be reduced.
The non-access module coprocessor 110 receives the indication signal sent by the indication circuit 124 and sends the indication signal to the CPU core 130, where the transmission path of the indication signal is the non-access module coprocessor 110, the APB bus 150, the AHB to APB bus bridge 160, the AHB bus 140, and the CPU core 130 in sequence.
The CPU core 130 receives the instruction signal, generates a gain adjustment signal according to the instruction signal, and sends the gain adjustment signal to the non-access module coprocessor 110, where the transmission path of the gain adjustment signal is the CPU core 130, the AHB bus 140, the AHB to APB bus bridge 160, the APB bus 150, and the non-access module coprocessor 110.
The non-access module coprocessor 110 sends the gain adjustment signal to the variable gain amplifier 123, wherein the gain adjustment signal includes a gain increase signal, a gain decrease signal, and a gain hold signal. If the gain adjustment signal is a gain increase signal or a gain decrease signal, the variable gain amplifier 123 adjusts the current gain according to the gain adjustment signal, and re-amplifies the input rf signal according to the adjusted gain, and repeats the above steps until the indication circuit 124 generates an indication signal of 01 or 10.
In this embodiment, the gain adjustment of the variable gain amplifier is performed iteratively, so that different first amplification gains are determined for different input radio frequency signals, the problem that the input radio frequency signals cannot be processed or the processing error is large due to overlarge or undersize is solved, the radio frequency signals sent by radio frequency devices with different distances can be received and processed, the receiving sensitivity and the anti-interference capability of the radio frequency signals are improved, and the size requirement of the terminal antenna can be reduced.
The input end of the analog demodulator 125 is connected to the input end of the variable gain amplifier 123, and receives the carrier signal sent by the variable gain amplifier 123, and can parse the carrier signal, extract the parsing command of the carrier signal, and send the parsing command to the non-access module coprocessor 110.
The non-access module coprocessor 110 may send the parse instruction to the CPU core 130 when the instruction signal meets a preset condition. The preset condition of the indication signal may be 01 or 10, that is, the indication signal corresponding to the gain maintaining signal satisfies the preset condition. The transmission path of the analysis command is the same as the transmission path of the instruction signal.
The CPU core 130 receives the parsing instruction and generates a return parameter, where the return parameter is a response parameter of the parsing instruction, and if the parsing instruction is an instruction for reading a card, the return parameter is current card data information. The CPU core 130 sends the generated return parameters to the non-interface module coprocessor 110.
Optionally, the SOC chip further includes a memory, for storing relevant data of the SOC chip, where the relevant data includes current card data information, and the memory is connected to the AHB bus 140, and when the CPU core 130 generates return data, the return data is sent to the memory for verification, and is sent to the non-connected module coprocessor 110 when the verification is successful, and a transmission path of the return parameter is the CPU core 130, the AHB bus 140, the memory, the AHB bus 140, the AHB to APB bus bridge 160, the APB bus 150, and the non-connected module coprocessor 110.
In this embodiment, the indication circuit compares the first voltage of the carrier signal amplified by the variable gain amplifier with the internal reference voltage to generate the adjustment indication signal of the variable gain amplifier, so that the control circuit controls the variable gain amplifier to adjust the amplification gain of the variable gain amplifier, thereby determining suitable amplification gains for the input radio frequency signals with different magnitudes, and improving the receiving sensitivity and anti-interference capability of the radio frequency front end chip on the radio frequency signals.
Optionally, the non-communication module 120 further includes: a data synchronization module 126 and an amplifier 127. Referring to fig. 3, wherein,
the CPU core 130 is further configured to generate a state control signal according to the indication signal, and send the state control signal to the clock data recovery module 122 based on the non-access module coprocessor 110;
the clock data recovery module 122 is electrically connected to the variable gain amplifier 123, and is configured to receive a state control signal, switch an operating state according to the state control signal, and extract a clock signal of a carrier signal in an enabled state, send the clock signal to the non-access module coprocessor 110, and generate an amplifier control signal homologous to the clock signal, where the operating state includes an enabled state and a suspended state;
The non-access module coprocessor 110 is further configured to generate return data according to the clock signal and the return parameter;
the data synchronization module 126 is electrically connected with the clock data recovery module 122 and the non-connected module coprocessor 110 respectively, and is used for synchronizing the clock signal and the return data to generate a modulation signal;
the amplifier 127 is electrically connected to the clock data recovery module 122 and the data synchronization module 126, and is configured to amplify the modulated signal, generate an output rf signal, and dissipate energy after outputting the output rf signal according to the amplifier control signal.
In this embodiment, the CPU core 130 receives the indication signal and generates a state control signal according to the indication signal, where the state control signal is used to control the working state of the clock data recovery module 122. For example, the state control signal may be composed of a logic "0" and a logic "1", for example, the clock data recovery module 122 may be in a suspend state when the state control signal is set to "0", and the clock data recovery module 122 may be in an enable state when the state control signal is set to "1". Wherein, when the indication signal is 01 or 10, the state control signal may be set to "1", and when the indication signal is 11 or 00, the state control signal may be set to "0".
The clock data recovery module 122 receives the state control signal, switches the operation state according to the state control signal, does not receive the carrier signal sent by the variable gain amplifier 123 if the state is in the pause state, receives the carrier signal if the state is in the enable state, and extracts the clock signal of the carrier signal.
The non-access module coprocessor 110 receives the clock signal sent by the clock data recovery module 122 and the return parameters sent by the CPU core 130, loads the return parameters on the clock signal, and generates return data, wherein the return data is a carrier signal carrying the return parameters.
The data synchronization module 126 synchronizes the clock signal with the return data, eliminates time delays in the return data, and co-frequency the generated modulated signal with the clock signal.
In this embodiment, since the clock signal needs to pass through a multi-stage program in the process of generating the return data by the non-access module coprocessor 110, the generated return data is likely to have delay, and in order to avoid an error caused by time delay, the return data is synchronized with the clock signal, and a modulation signal with the same frequency as the clock signal is generated. And determining the amplified adjustment signal as an output radio frequency signal.
In this embodiment, the working state of the clock data recovery module 122 is controlled by the state control signal, that is, the state can be enabled only after the amplification gain adjustment of the variable gain amplifier is completed, so that the problem that the signal is disordered due to the fact that the output radio frequency signal generated in the amplification gain adjustment process of the variable gain amplifier is acquired by the terminal antenna again is avoided, and the interference of irrelevant signals is reduced.
In this embodiment, the amplifier 127 is configured to amplify the modulated signal, so that the generated output rf signal has a higher sensitivity, which improves the output sensitivity of the rf signal and can reduce the size requirement of the terminal antenna.
In this embodiment, the amplifier control signal is homologous to the clock signal of the carrier signal, and is used to control the amplifier 127, and when the amplifier 127 finishes transmitting the output rf signal, the energy remained in the amplifier 127 is dissipated, so as to avoid the influence of the residual energy on the subsequent transmission of the output rf signal.
Optionally, the CPU core 130 is further configured to obtain a first amplification gain of the variable gain amplifier 123 when the signal meets a preset condition, determine a second amplification gain according to the first amplification gain, and send the second amplification gain to the non-access module coprocessor 110, where the second amplification gain is matched with the first amplification gain;
The non-interface module coprocessor 110 is electrically connected to the amplifier 127, and is further configured to send the second amplification gain to the amplifier 127, so that the amplifier 127 amplifies the modulated signal according to the second amplification gain.
In this embodiment, the amplification gain of the amplifier 127 is adjustable, and the second amplification gain of the amplifier 127 is related to the first amplification gain of the variable gain amplifier 123. Optionally, a corresponding list or a corresponding functional relationship between the first amplification gain and the second amplification gain is set in the CPU core 130, and the second amplification gain can be fast and truly set according to the first amplification gain. Optionally, the second amplification gain is positively correlated with the first amplification gain. Illustratively, if the first amplification gain of the variable gain amplifier 123 is close, it indicates that the distance between the external communication device such as a card reader and the terminal where the SOC chip is located is small, the rf field strength is large, and it is further known that the amplification capability of the amplifier 127 should be reduced; accordingly, if the first amplification gain of the variable gain amplifier 123 is larger, it indicates that the external communication device such as a card reader is farther from the terminal where the SOC chip is located, and the rf field strength is smaller, which further indicates that the amplification capability of the amplifier 127 should be improved.
In this embodiment, the distance between the external communication device and the terminal where the SOC chip is located is represented by the first amplification gain, and the second amplification gain matched with the distance is determined, so that the generated output radio frequency signal is matched with the distance, the problem that the output radio frequency signal determined by the fixed gain is too large or too small and exceeds the communication distance of the external communication device is solved, and the applicability of the output radio frequency signal is improved.
Optionally, the SOC chip further includes a security module 180, where the security module 180 is electrically connected to the APB bus 150, and is configured to receive an analysis instruction sent by the non-module coprocessor 110 based on the APB bus 150, perform security verification on the analysis instruction, generate verification information, and send the verification information to the non-module coprocessor 110 based on the APB bus 150;
the non-access module coprocessor 110 is further configured to combine the return parameter with the clock signal of the carrier signal to generate return data when the verification information is successful, and discard the return parameter when the verification information is failed.
In this embodiment, in order to improve the security of communication between the rf front-end chip and the external device, security verification needs to be performed on the analysis instruction, where the security module 180 is used for security verification on the analysis instruction, and communicates with the non-access module coprocessor 110 through the APB bus 150.
The security module 180 receives the analysis instruction sent by the non-access module coprocessor 110, and feeds back verification information after verification, where if the feedback information is verification success, the non-access module coprocessor 110 performs an operation of combining the return parameter with the clock signal of the carrier signal to generate the return data, and if the feedback information is verification failure, the control circuit 140 interrupts the response to the input radio frequency signal and discards the return parameter.
In the embodiment, the safety of communication between the SOC chip and the external equipment is improved through safety verification of the analysis instruction.
Optionally, the SOC chip further includes a communication interface, which is connected to the APB bus 150 and is used to encode transmission data, and the communication interface may be a proprietary GPIO (General Purpose Input Output, general purpose input/output) interface, or may be a SWP (Single Wire Protocol single wire protocol) interface, for example. The communication interface is arranged to encode the transmission data, so that the safety and reliability of the data transmission between the radio frequency front end chip and the external safety module are improved, and the problems of data loss or leakage and the like in the data transmission process are avoided.
Example two
Fig. 4 is a flowchart of a radio frequency signal processing method provided by the second embodiment of the present invention, where the present embodiment is applicable to a case where an SOC chip in an intelligent terminal processes radio frequency signals, and the method may be performed by the SOC chip provided by the embodiment of the present invention. The method specifically comprises the following steps:
S210, acquiring an input radio frequency signal and acquiring the signal strength of the input radio frequency signal.
In this embodiment, the field intensity of the radio frequency field where the SOC chip is located is represented by the signal intensity of the input radio frequency signal.
And S220, if the signal intensity is detected to be larger than the preset value, generating a first wake-up instruction, and powering up the SOC chip according to the first wake-up instruction.
If the detected signal intensity is larger than the preset value, the SOC chip is indicated to be in a radio frequency field, and preliminary awakening is carried out on the SOC chip through a first awakening instruction, wherein the preliminary awakening refers to power-on processing of each module of the SOC chip.
S230, extracting a clock signal of an input radio frequency signal, judging whether the clock signal is in a stable state according to a preset rule, generating a wake-up instruction according to a judging result, and determining whether to wake up the SOC chip according to the wake-up instruction.
And determining whether the radio frequency field where the SOC chip is positioned is a stable radio frequency field by further judging whether the clock signal of the input radio frequency signal is in a stable state. The radio frequency field comprises a stable radio frequency field and a clutter radio frequency field, wherein the stable radio frequency field refers to a radio frequency field sent by external communication equipment such as a card reader, and the clutter radio frequency field refers to a radio frequency field formed by noise signals.
Optionally, step S230 includes: acquiring frequency information and amplitude information of a clock signal, and determining whether the frequency information meets a first preset condition and whether the amplitude information meets a second preset condition;
if yes, generating a second wake-up signal, waking up the SOC chip according to the second wake-up signal, and processing the input radio frequency signal;
if not, generating a cancel wake-up signal, and powering down the SOC chip according to the cancel wake-up signal.
In this embodiment, whether the radio frequency field where the SOC chip is located is a stable radio frequency field is determined by the frequency information and the amplitude information of the clock signal. And when the power-on state is not in the stable radio frequency field, the power-off processing is carried out on the SOC chip, so that the power consumption caused by the power-on state of the SOC chip is reduced.
Optionally, referring to fig. 5, fig. 5 is a flowchart of a radio frequency signal processing according to a second embodiment of the present invention, where the processing an input radio frequency signal includes:
s310, acquiring an input radio frequency signal and determining a first amplification gain of the input radio frequency signal.
Wherein, for each input radio frequency signal, a corresponding first amplification gain is determined, wherein the first amplification gain may be determined by a plurality of iterative adjustments, and the receiving sensitivity of the radio frequency signal is improved by adjusting the first amplification gain.
Optionally, step S310 includes: amplifying an input radio frequency signal according to the current gain to generate a carrier signal; extracting a first voltage of a carrier signal, comparing the first voltage with an internal reference voltage, and determining an indication signal according to a comparison result; and generating a gain adjusting signal according to the indicating signal, adjusting the current gain according to the gain adjusting signal, and determining the first amplification gain.
Optionally, the gain adjustment signal includes a gain increase signal, a gain decrease signal, and a gain hold signal, and the determining the amplification gain includes: if the gain adjusting signal is a gain increasing signal, the first amplifying gain is the sum of the current gain and the reference gain, and the indicating signal is redetermined; if the gain adjusting signal is a gain reducing signal, the first amplification gain is the difference between the current gain and the reference gain, and the indication signal is redetermined; if the gain adjustment signal is a gain maintaining signal, the adjustment of the current gain is stopped, and the current gain is determined as a first amplification gain.
The reference gain refers to the gain variation at each gain adjustment. In this embodiment, when the gain adjustment signal is detected as the gain hold signal, it is determined that the gain adjustment is completed, and the carrier signal generated by the determined amplification gain processing is subjected to subsequent processing.
S320, signal amplification is carried out on the input radio frequency signal according to the amplification gain, and a carrier signal is generated.
S330, extracting an analysis instruction carried by the carrier signal, and generating a return parameter according to the analysis instruction.
S340, combining the return parameter with the clock signal of the carrier signal to generate an output radio frequency signal.
Optionally, S340 includes: combining the return parameter with the clock signal of the carrier signal to generate return data; synchronizing the return data with a clock signal of the carrier signal to generate a modulated signal; and amplifying the modulated signal to generate and output a radio frequency signal.
In this embodiment, the modulated signal is amplified, so that the generated output radio frequency signal has higher sensitivity, and the output sensitivity of the radio frequency signal is improved.
Optionally, before the signal amplification is performed on the modulated signal, the method further includes: determining a second amplification gain according to the first amplification gain, wherein the second amplification gain is matched with the first amplification gain; and amplifying the modulated signal according to the second amplification gain.
In this embodiment, the distance between the external communication device and the terminal where the SOC chip is located is represented by the first amplification gain, and the second amplification gain matched with the distance is generated, so that the generated output radio frequency signal is matched with the distance, which solves the problem that the output radio frequency signal determined by the fixed gain is too large or too small and exceeds the communication distance of the external communication device, and improves the applicability of the output radio frequency signal.
Optionally, before combining the return parameter with the clock signal of the carrier signal to generate the output radio frequency signal, the method further includes: transmitting the analysis instruction to the safety module, carrying out safety verification on the analysis instruction, and receiving feedback information of the safety module; if the feedback information is successful in verification, combining the return parameter with the clock signal of the carrier signal; if the feedback information is verification failure, discarding the parameters.
In this embodiment, through the security verification of the analysis instruction, the security of the communication between the radio frequency front end chip and the external device is improved.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (10)
1. An SOC chip is characterized by comprising a non-connection module coprocessor and a non-connection communication module, wherein,
the non-connection communication module is electrically connected with the non-connection module coprocessor and comprises a preliminary awakening module and a clock data recovery module;
the preliminary wake-up module is electrically connected with the non-connected module coprocessor and is used for detecting the field intensity of the radio frequency field where the SOC chip is located, and sending a first wake-up instruction to the non-connected module coprocessor when the field intensity is detected to be larger than a preset value;
the non-connected module coprocessor is electrically connected with the clock data recovery module and is used for sending the first wake-up instruction to the clock data recovery module;
the clock data recovery module is used for entering a working state according to the first wake-up instruction, extracting a clock signal of an input radio frequency signal, and sending a wake-up instruction signal to the non-connected module coprocessor according to the clock signal;
the non-connected module coprocessor is further used for determining whether to wake up the SOC chip according to the wake-up indication signal;
the SOC chip further comprises a CPU core, and the non-communication module further comprises a variable gain amplifier, an indicating circuit and an analog demodulator; wherein,
The variable gain amplifier is used for amplifying an input radio frequency signal according to the current gain in an awake state and outputting a carrier signal;
the indicating circuit is respectively and electrically connected with the variable gain amplifier and the non-connected module coprocessor, and is used for extracting the first voltage of the carrier signal, generating an indicating signal according to the first voltage and the internal reference voltage, and sending the indicating signal to the non-connected module coprocessor;
the analog demodulator is electrically connected with the variable gain amplifier and the non-connected module coprocessor, and is used for analyzing the carrier signal and sending the generated analysis instruction to the non-connected module coprocessor;
the non-module coprocessor is electrically connected with the CPU core based on an APB bus and an AHB bus and is also used for sending the indication signal and the analysis instruction to the CPU core, wherein the APB bus and the AHB bus are connected through an AHB to APB bus bridge;
the CPU core is used for generating a gain adjusting signal according to the indicating signal, sending the gain adjusting signal to the non-connected module coprocessor and generating a return parameter according to a corresponding analysis instruction when the indicating signal meets a preset condition;
The non-connected module coprocessor is electrically connected with the variable gain amplifier and is also used for sending the gain adjustment signal to the variable gain amplifier so that the variable gain amplifier adjusts the current gain and amplifies the input radio frequency signal according to a first amplification gain generated by adjustment;
the CPU core is further configured to obtain a first amplification gain of the variable gain amplifier when the indication signal meets a preset condition, determine a second amplification gain according to the first amplification gain, and send the second amplification gain to the non-access module coprocessor, where the second amplification gain is matched with the first amplification gain;
the non-connection module coprocessor is electrically connected with the amplifier and is further used for sending the second amplification gain to the amplifier so that the amplifier can amplify the modulation signal according to the second amplification gain.
2. The SOC chip of claim 1, wherein the preliminary wake-up module includes a field strength detection circuit and a power management unit; wherein,
the field intensity detection circuit is electrically connected with the power management unit and is used for detecting the field intensity of an input radio frequency signal, and when detecting that the field intensity of the input radio frequency signal is larger than a preset value, the field intensity detection circuit sends a first starting instruction to the power management unit;
The power management unit is electrically connected with the non-connected module coprocessor, and a user enters a working state according to the first starting instruction and sends a first wake-up instruction to the non-connected module coprocessor.
3. The SOC chip of claim 1, wherein the clock data recovery module is specifically configured to:
acquiring frequency information and amplitude information of the clock signal, and determining whether the frequency information meets a first preset condition or not and whether the amplitude information meets a second preset condition or not;
if yes, generating a second wake-up signal, and if not, generating a cancel wake-up signal;
correspondingly, the non-connected module coprocessor is specifically configured to:
waking up the SOC chip according to the second wake-up signal, and processing the input radio frequency signal; or alternatively, the first and second heat exchangers may be,
and carrying out power-down processing on the SOC chip according to the wake-up cancellation signal.
4. The SOC chip of claim 1, wherein the non-on communication module further comprises: a data synchronization module and an amplifier; wherein,
the CPU core is further used for generating a state control signal according to the indication signal, and sending the state control signal to a clock data recovery module based on the non-access module coprocessor;
The clock data recovery module is electrically connected with the variable gain amplifier, and is used for receiving the state control signal, switching the working state according to the state control signal, extracting the clock signal of the carrier signal in the enabling state, sending the clock signal to the non-access module coprocessor, and generating an amplifier control signal homologous to the clock signal, wherein the working state comprises an enabling state and a pause state;
the non-connected module coprocessor is further used for generating return data according to the clock signal and the return parameters;
the data synchronization module is respectively and electrically connected with the clock data recovery module and the non-connected module coprocessor and is used for synchronizing the clock signal and the return data to generate a modulation signal;
the amplifier is respectively and electrically connected with the clock data recovery module and the data synchronization module, and is used for amplifying the modulation signal to generate an output radio frequency signal and dissipating energy after the output radio frequency signal is output according to the amplifier control signal;
the SOC chip further comprises a safety module, wherein the safety module is electrically connected with the APB bus and is used for receiving an analysis instruction sent by the non-connected module coprocessor based on the APB bus, carrying out safety verification on the analysis instruction, generating verification information and sending the verification information to the non-connected module coprocessor based on the APB bus;
And the non-access module coprocessor is further used for combining the return parameters with the clock signals of the carrier signals to generate return data when the verification information is verification success, and discarding the return parameters when the verification information is verification failure.
5. The SOC chip of claim 1 further comprising a global clock management module electrically coupled to the AHB bus for generating a modulated clock signal based on a reference clock signal and a configuration file sent by the CPU core, and for adjusting a clock frequency of the APB bus based on the modulated clock signal, and an operating state of a peripheral device electrically coupled to the APB bus, wherein the configuration file includes operating clock information of the APB bus and the peripheral device.
6. The SOC chip of any of claims 4-5, wherein the CPU core is a 16/32bit mixed instruction CPU core.
7. A method of radio frequency signal processing, comprising:
acquiring an input radio frequency signal and acquiring the signal strength of the input radio frequency signal;
if the signal intensity is detected to be larger than a preset value, a first wake-up instruction is generated, and the SOC chip is electrified according to the first wake-up instruction;
Extracting a clock signal of the input radio frequency signal, judging whether the clock signal is in a stable state according to a preset rule, generating a wake-up instruction according to a judging result, and determining whether to wake up the SOC chip according to the wake-up instruction;
processing the input radio frequency signal includes:
acquiring an input radio frequency signal and determining a first amplification gain of the input radio frequency signal;
amplifying the input radio frequency signal according to the amplification gain to generate a carrier signal;
extracting an analysis instruction carried by the carrier signal, and generating a return parameter according to the analysis instruction;
combining the return parameter with the clock signal of the carrier signal to generate an output radio frequency signal, comprising:
combining the return parameter with the clock signal of the carrier signal to generate return data;
synchronizing the return data with a clock signal of the carrier signal to generate a modulation signal;
amplifying the modulated signal to generate an output RF signal and outputting
Before the signal amplification is performed on the modulated signal, the method further comprises:
determining a second amplification gain according to the first amplification gain, wherein the second amplification gain is matched with the first amplification gain;
And carrying out signal amplification on the modulation signal according to the second amplification gain.
8. The method of claim 7, wherein extracting the clock signal of the input radio frequency signal, determining whether the clock signal is in a steady state according to a preset rule, generating a wake-up instruction according to a determination result, and determining whether to wake up the SOC chip according to the wake-up instruction, comprises:
acquiring frequency information and amplitude information of the clock signal, and determining whether the frequency information meets a first preset condition or not and whether the amplitude information meets a second preset condition or not;
if yes, generating a second wake-up signal, waking up the SOC chip according to the second wake-up signal, and processing the input radio frequency signal;
if not, generating a cancel wake-up signal, and performing power-down processing on the SOC chip according to the cancel wake-up signal.
9. The method of claim 7, wherein acquiring an input radio frequency signal and determining a first amplification gain of the input radio frequency signal comprises:
amplifying the input radio frequency signal according to the current gain to generate a carrier signal;
Extracting a first voltage of the carrier signal, comparing the first voltage with an internal reference voltage, and determining an indication signal according to a comparison result;
and generating a gain adjusting signal according to the indicating signal, adjusting the current gain according to the gain adjusting signal, and determining the first amplification gain.
10. The method of claim 7, wherein combining the return parameter with the clock signal of the carrier signal, prior to generating an output radio frequency signal, further comprises:
transmitting the analysis instruction to a safety module, carrying out safety verification on the analysis instruction, and receiving feedback information of the safety module;
if the feedback information is successful in verification, combining the return parameter with the clock signal of the carrier signal;
and discarding the parameters if the feedback information is verification failure.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110083396A (en) * | 2019-04-19 | 2019-08-02 | 京东方科技集团股份有限公司 | Transport box, movement system and its information display control method |
| CN110399331A (en) * | 2019-08-07 | 2019-11-01 | 北京智芯微电子科技有限公司 | The method of clock signal noise is reduced in SOC chip and SOC chip |
| CN111263339B (en) * | 2020-01-14 | 2021-06-04 | 荣耀终端有限公司 | Wireless communication method and device with wireless communication function |
| CN112558750A (en) * | 2020-12-22 | 2021-03-26 | 广州粒子微电子有限公司 | Method and device for waking up chip |
| CN112506577B (en) * | 2021-02-05 | 2022-05-20 | 北京紫光青藤微***有限公司 | Wake-up system, near field communication device and wake-up method |
| CN112666405A (en) * | 2021-03-16 | 2021-04-16 | 北京紫光青藤微***有限公司 | Method and device for field intensity detection and communication equipment |
| CN117130671A (en) * | 2023-01-16 | 2023-11-28 | 荣耀终端有限公司 | System wake-up method, electronic equipment and computer readable storage medium |
| CN117094340B (en) * | 2023-10-17 | 2023-12-15 | 中诚华隆计算机技术有限公司 | Method for improving NFC recognition efficiency of SOC chip |
| CN117119568B (en) * | 2023-10-25 | 2023-12-29 | 中诚华隆计算机技术有限公司 | Method for reducing unnecessary wake-up NFC recognition process of SOC chip |
| CN117114025B (en) * | 2023-10-25 | 2023-12-29 | 中诚华隆计算机技术有限公司 | Method for reducing energy consumption of SOC (system on chip) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1689346A (en) * | 2002-10-22 | 2005-10-26 | 诺基亚有限公司 | Method and device for transponder aided wake-up of a low power radio device |
| CN1965488A (en) * | 2004-04-23 | 2007-05-16 | 密克罗奇普技术公司 | Programmable selective wake-up for radio frequency transponder |
| CN101373981A (en) * | 2007-08-24 | 2009-02-25 | 上海兆富通信技术有限公司 | Wireless searching and positioning apparatus based on wireless awakening technology and energy consumption control method thereof |
| CN102625423A (en) * | 2011-03-10 | 2012-08-01 | 深圳市华奥通通信技术有限公司 | Wireless communication system and wake up method thereof |
| CN105657804A (en) * | 2016-03-03 | 2016-06-08 | 上海大学 | Self-adaptive monitor matching anti-interference method of wireless sensor network |
| CN106937368A (en) * | 2015-12-31 | 2017-07-07 | 深圳友讯达科技股份有限公司 | The secondary wake/sleep method of low power loss communication node, node and system |
| CN207489012U (en) * | 2017-11-14 | 2018-06-12 | 上海坤锐电子科技有限公司 | A kind of SOC chip |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9544004B2 (en) * | 2010-03-12 | 2017-01-10 | Sunrise Micro Devices, Inc. | Power efficient communications |
| US20170064625A1 (en) * | 2015-09-01 | 2017-03-02 | Qualcomm Incorporated | Coordinating receiver wakeup times used for wireless wide area networks and wireless local area networks |
-
2017
- 2017-11-14 CN CN201711123113.0A patent/CN107918596B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1689346A (en) * | 2002-10-22 | 2005-10-26 | 诺基亚有限公司 | Method and device for transponder aided wake-up of a low power radio device |
| CN1965488A (en) * | 2004-04-23 | 2007-05-16 | 密克罗奇普技术公司 | Programmable selective wake-up for radio frequency transponder |
| CN101373981A (en) * | 2007-08-24 | 2009-02-25 | 上海兆富通信技术有限公司 | Wireless searching and positioning apparatus based on wireless awakening technology and energy consumption control method thereof |
| CN102625423A (en) * | 2011-03-10 | 2012-08-01 | 深圳市华奥通通信技术有限公司 | Wireless communication system and wake up method thereof |
| CN106937368A (en) * | 2015-12-31 | 2017-07-07 | 深圳友讯达科技股份有限公司 | The secondary wake/sleep method of low power loss communication node, node and system |
| CN105657804A (en) * | 2016-03-03 | 2016-06-08 | 上海大学 | Self-adaptive monitor matching anti-interference method of wireless sensor network |
| CN207489012U (en) * | 2017-11-14 | 2018-06-12 | 上海坤锐电子科技有限公司 | A kind of SOC chip |
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| Publication number | Publication date |
|---|---|
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