CN107908585A - A kind of PCIE BOX plates for surpassing calculation function with PCIe card and GPU - Google Patents
A kind of PCIE BOX plates for surpassing calculation function with PCIe card and GPU Download PDFInfo
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- CN107908585A CN107908585A CN201711242538.3A CN201711242538A CN107908585A CN 107908585 A CN107908585 A CN 107908585A CN 201711242538 A CN201711242538 A CN 201711242538A CN 107908585 A CN107908585 A CN 107908585A
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- pcie
- gpu
- card
- box plates
- surpassing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4081—Live connection to bus, e.g. hot-plugging
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Bus Control (AREA)
Abstract
A kind of PCIE BOX plates for surpassing calculation function with PCIe card and GPU of the present application, the PCIE BOX plates include Neo Scale high speed connectors, PCA9555, TPS2363, CPLD chip and PCIE Slot, it can realize that PCIE warm connection functions, Switch switching PCIEX8 can insert GPU card into PCIEX16 circuits and realize that data accelerate computing, EMC plates BMC chip to improve operation efficiency by SMBUS monitoring bus BOX board functions.
Description
Technical field
The present invention relates to server B OX plate design fields, and in particular to a kind of that there is PCIe card and GPU to surpass calculation function
PCIEBOX plates.
Background technology
In traditional server B OX plates, if 16 groups of PCIE (Peripheral Component of the system integration
Interconnect Express high speed serialization computer expansion bus standard) signal, and support hot plug and there is 300W
GPU (the Graphics Processing Unit graphics processors) cards of high power consumption, then this BOX plates design method is to mainboard
The cabling of layout and signal proposes very big challenge, and the especially requirement to BOX plate integrated levels is higher and higher.
Because BOX plates are in principle diagram design, layout designs, it is necessary to strictly observe signal lead specification requirement, so
It just can ensure that signal quality, ensure the realization of board design function；But highdensity layout cabling, reduce the use of board
Space.This have impact on the quality of signal to a certain extent, reduce the performance of board.So integrate 16 groups of PCIE signals and branch
Hold the GPU card of hot plug and high power consumption BOX plates can there are heat dissipation effect is bad, loss is big there are high density motherboard layout cabling
The problems such as.
The pin above problem, a kind of PCIE BOX plates for surpassing calculation function with PCIe card and GPU of the present application, for 16
Group PCIE device and the GPU equipment of high power consumption requirement, devise 16 PCIE Slot, compatible X2, X4, the card of X8, at the same time
Switching, the GPU card of compatible X16 can be carried out by switch on plank, which is calculated using hardware module to substitute software
Method, by the intrinsic rapid charater of hardware, substantially increases operation efficiency, at the same can also solve well front-end architecture,
The problem of loss, heat dissipation and board layout's cabling.
The content of the invention
A kind of PCIE BOX plates for surpassing calculation function with PCIe card and GPU of the present application.PCIE of the present invention
BOX plates include PCA9555, TPS2363, CPLD chip and PCIE Slot, make CPLD (Complex by hardware circuit
Programmable Logic Device Complex Programmable Logic Devices) chip communicates with PCIE Slot, it is possible to achieve it is inserted in
PCIe card warm connection function on PCIE Slot；By being inserted in the CDPF cables of Neo Scale high speed connectors, Ke Yiyu
PCIE Expand cartoon letters, transmit the PCIE signal of X16, and the relevant signal of some hot plugs.
In addition, EMC (Expand Manage Control management controls expansion board) plate passes through Power Conn
(Connection connectors) communicates with BOX, provides 12V electricity for BOX plates, PowerConn is also to be connected by cable, Ke Yiman
The high GPU card of sufficient power consumption；There are 3 groups of SMBUS buses on Power Conn connectors, it is real by chip PCA9546, PCA9548
Existing data exchange, for monitoring BOX plate temperatures, voltage and some PCIe card attributes, it is achieved thereby that being supervised to the intelligence of BOX plates
Control.
Specifically, a kind of PCIE BOX plates for surpassing calculation function with PCIe card and GPU, its feature is claimed in the application
It is, which includes：Neo Scale high speed connectors, PCA9555, TPS2363, CPLD chip and PCIE
Slot, makes CPLD chips communicate with PCIE Slot by hardware circuit, for the PCIe card hot plug being inserted on PCIE Slot
Function；By being inserted in the CDPF cables of Neo Scale high speed connectors, it can transmit X16's with PCIE Expand cartoon letters
PCIE signal.
The PCIE BOX plates as described above for surpassing calculation function with PCIe card and GPU, are further characterized in that, EMC plates lead to
Cross PowerConn connectors to communicate with BOX, 12V electricity is provided for BOX plates.
The PCIE BOX plates as described above for surpassing calculation function with PCIe card and GPU, are further characterized in that, Power
There are 3 groups of SMBUS buses on Conn connectors, realized by chip PCA9546, chip PCA9548 to BOX plates difference physically
Location equipment, voltage, temperature realize monitoring.
The PCIE BOX plates as described above for surpassing calculation function with PCIe card and GPU, are further characterized in that, the PCIE
Signal of the BOX plates using a Switch connected two PCIE X8 signals composition X16.
The PCIE BOX plates as described above for surpassing calculation function with PCIe card and GPU, are further characterized in that, are forming
After X16 signals, GPU card is plugged, can realize that the data of X16GPU cards accelerate calculation function under the instruction running of operating system.
The as described above PCIE BOX plates for surpassing calculation function with PCIe card and GPU, are further characterized in that, CPLD can be with
8bit GPIO data are sent by I2C links to communicate with BMC chip.
Brief description of the drawings
Fig. 1, present invention specific implementation structure diagram
Fig. 2, BOX and PCIE Expand cards, EMC plates connection block diagram
Fig. 3, PCIE hot plug conspectus
Fig. 4, GPU card data accelerate operating structure schematic diagram
Fig. 5, EMC board monitoring BOX plate structure schematic diagrams
Embodiment
Below by one embodiment to PCIE BOX plates concrete structure explanation of the present invention.
The specific embodiment that PCIE BOX plate techniques of the present invention are realized (Switch5- as shown in Figure 1
Switch8 is not shown)；BOX is connected block diagram as shown in Figure 2 with PCIE Expand cards, EMC plates.
The power supply of BOX plates mainly includes P12V, P3V3, P3V3_STBY.P12V electricity is come from EMC plates；P12V_STBY
The P12V obtained using soft start circuits, P12V produce P3V3, P3V3_STBY electricity by power supply chip.
The major function of BOX plates has three, and specially PCIE warm connection functions, Switch switch PCIEX8 into PCIEX16
Circuit can insert GPU card and realize that data accelerate computing, EMC plates BMC (Baseboard Management Controller substrates
Management Controller) chip passes through SMBUS monitoring bus BOX board functions.Analyze one by one below：
1st, PCIE warm connection functions
As shown in Figure 3, PCIE hot plugs circuit includes PCA9555 chips, TPS2363 chips, CPLD chips.
PCA9555 is mainly used for decoding one group of I2C signal of CPU, and such as SMB_CLK, the SMB_DATA in the design, control feedback heat is inserted
Pull out function.TPS2363 is power supply chip, and predominantly PCIE device provides PCIE_P12V, PCIE_P3V3, PCIE_P3V3_STBY
The Enable signals of electricity.Electric electrifying timing sequence on CPLD major control planks, and some logic controls.9DB833 chips are
Clock chip, 100M clock differential pairs are provided for PCIE device.Warm connection function realizes that signal logic is sequentially in PCIE BOX plates
It is analyzed as follows：
A) when carrying out hot plug to PCIE device, the button of warm connection function is pressed, can send a bottom at this time has
The BTN# signals of effect can also detect the PCIE PRST# of PCIE device to CPLD, CPLD, then do in code and sent out with logical operation
Go out Hot Plug Attn SW# and give PCA9555 chips；
B) PCA9555 chips receive Hot Plug Attn SW#, the PCIE PRST# that CPLD is sent, and can also send PCIE
PWREN SW HP# give CPLD chips；
C) CPLD detects PCIE PWREN SW HP#, and logical operation can be done in code, sends chip TPS2363's
Enable signals；
D) power supply chip TPS2363 sends PCIE device PCIE_P12V, PCIE_P3V3, PCIE_P3V3_STBY electricity
Enable signals, power to PCIE device, while can send out PCIE PWRGD# to CPLD, and PCIE PWRFLT# are to PCA9555；
E) CPLD detects PCIE PWRGD#, and logical operation can be done in code, sends the Enable letters of chip 9DB833
Number；
F) 9DB833 chips send PCIE device 100M clock differential pairs；
G) information can be issued CPU by PCA9555 by I2C, and operating system issues instructions to CPU, is issued by I2C
PCA9555, decoding send PWR LED#, and Attn LED# drivings LED is bright, when CPU detects the corresponding deposits of PCIE PWRFLT#
Device is effective, and warm connection function fails at this time.
2nd, GPU card data accelerate calculation function
PCIE BOX plates design the card for being mainly used for X8, but the groove of X16 is used on hardware, and the groove of X16 does not connect
Relevant PCIE signal.In order to realize the data of X16GPU cards accelerate calculation function, the present invention in BOX plates use one
Switch is the signal of connected two PCIE X8 signals composition X16, and specifically as shown in Figure 4, a PCIE X8 signal, leads to
The corresponding PCIE signal of PCIE slot grooves where switch is switched to another PCIE X8 is crossed, is thus constituted
X16PCIEslot signals, after plugging GPU card, realize that data accelerate computing under the instruction running of operating system.
CPLD chips are mainly used for detecting PCEI X8PRST#, CEI X16PRST# signals, when not inserting GPU card, CPLD
It is effective to detect PCEI X8PRST#, PCEI X16PRST# are invalid, and CPLD will not send the Enable signals of Switch；When slotting
When entering GPU card, CPLD detects that PCEI X8PRST# are invalid, and PCEI X16PRST# are effective, and CPLD sends the Enable of Switch
Signal, realizes the switching of PCIE X8 to PCIE X16.
3rd, EMC board monitorings BOX functions
As shown in Figure 5,3 groups of SMBUS buses on EMC plates, SMBUS3, SMBUS4, SMBUS5 pass through chip
PCA9546, chip PCA9548 are realized realizes monitoring to BOX plate difference physical address equipment, voltage, temperature.
PCA9546 can switch 4 groups of I2C according to address difference；PCA9548 can switch 8 groups of I2C.The CLK of every group of I2C,
DATA and the CLK for the equipment to be monitored, DATA are connected.
SMBUS3, SMBUS4 can monitor the information of 16 PCIE devices.
Control chip ADM1276 can be started with monitoring clock chip 9DB833, SoftStart by crossing SMBUS5, FRU's
I2C can read BOX plates so address of devices.
PSOC (Programmable System-On-Chip on pieces programmable system) passes through temperature sensor, voltage
Sensor collects voltage, and temperature issues EMC plate BMC chips by I2C links.
CPLD can also send 8bit GPIO by I2C links, and (General Purpose Input Output are general defeated
Entering/export) data communicate with BMC chip.
It should be evident that illustrated above is only the specific embodiment of the present invention, for the common skill in this area
For art personnel, without creative efforts, other technical solutions can also be obtained according to above-described embodiment,
And the equivalent variations made in the scope of protection of the invention should all be fallen within the scope of protection of the present invention, and belong to the present invention
The scope of protection.
BOX plates designing scheme of the present invention, is evaluated by project team, can be effectively realized through actual test
PCIE hot plugs, GPU card data accelerate computing and EMC board monitoring BOX functions, effectively utilize board space, and on BOX plates
Signal stabilization, performance are high.
Claims (6)
1. a kind of PCIE BOX plates for surpassing calculation function with PCIe card and GPU, it is characterised in that the PCIE BOX plates include：
Neo Scale high speed connectors, PCA9555, TPS2363, CPLD chip and PCIE Slot, make CPLD by hardware circuit
Chip communicates with PCIE Slot, for the PCIe card warm connection function being inserted on PCIE Slot；By being inserted in NeoScale high
The CDPF cables of fast connector, with PCIE Expand cartoon letters, can transmit the PCIE signal of X16.
2. surpassing the PCIE BOX plates of calculation function with PCIe card and GPU as claimed in claim 1, it is further characterized in that, EMC
Plate is communicated by Power Conn connectors with BOX, and 12V electricity is provided for BOX plates.
3. surpassing the PCIE BOX plates of calculation function with PCIe card and GPU as claimed in claim 2, it is further characterized in that,
There are 3 groups of SMBUS buses on PowerConn connectors, realize different to BOX plates by chip PCA9546, chip PCA9548
Physical address equipment, voltage, temperature realize monitoring.
4. surpassing the PCIE BOX plates of calculation function with PCIe card and GPU as claimed in claim 3, it is further characterized in that, should
Signal of the PCIE BOX plates using a Switch connected two PCIE X8 signals composition X16.
5. surpassing the PCIE BOX plates of calculation function with PCIe card and GPU as claimed in claim 4, it is further characterized in that,
After forming X16 signals, GPU card is plugged, can realize that the data of X16 GPU cards accelerate computing under the instruction running of operating system
Function.
6. surpassing the PCIE BOX plates of calculation function with PCIe card and GPU as claimed in claim 5, it is further characterized in that,
CPLD can send 8 bit GPIO data by I2C links and communicate with BMC chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711242538.3A CN107908585A (en) | 2017-11-30 | 2017-11-30 | A kind of PCIE BOX plates for surpassing calculation function with PCIe card and GPU |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711242538.3A CN107908585A (en) | 2017-11-30 | 2017-11-30 | A kind of PCIE BOX plates for surpassing calculation function with PCIe card and GPU |
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| Publication Number | Publication Date |
|---|---|
| CN107908585A true CN107908585A (en) | 2018-04-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201711242538.3A Pending CN107908585A (en) | 2017-11-30 | 2017-11-30 | A kind of PCIE BOX plates for surpassing calculation function with PCIe card and GPU |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110377539A (en) * | 2019-06-25 | 2019-10-25 | 苏州浪潮智能科技有限公司 | A kind of data transmission method, device and medium based on high speed signal switching chip |
| CN110442389A (en) * | 2019-08-07 | 2019-11-12 | 北京技德***技术有限公司 | A kind of shared method using GPU of more desktop environments |
| CN111897398A (en) * | 2020-08-11 | 2020-11-06 | 曙光信息产业(北京)有限公司 | Heterogeneous computing expansion device and electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110377539A (en) * | 2019-06-25 | 2019-10-25 | 苏州浪潮智能科技有限公司 | A kind of data transmission method, device and medium based on high speed signal switching chip |
| CN110442389A (en) * | 2019-08-07 | 2019-11-12 | 北京技德***技术有限公司 | A kind of shared method using GPU of more desktop environments |
| CN110442389B (en) * | 2019-08-07 | 2024-01-09 | 北京技德***技术有限公司 | Method for sharing GPU (graphics processing Unit) in multi-desktop environment |
| CN111897398A (en) * | 2020-08-11 | 2020-11-06 | 曙光信息产业(北京)有限公司 | Heterogeneous computing expansion device and electronic equipment |
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Application publication date: 20180413 |