CN213276459U

CN213276459U - Server mainboard and server

Info

Publication number: CN213276459U
Application number: CN202022753197.XU
Authority: CN
Inventors: 柳胜杰; 杨晓君; 李书通; 孙瑛琪; 李晶晶
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2020-11-25
Filing date: 2020-11-25
Publication date: 2021-05-25
Anticipated expiration: 2030-11-25

Abstract

The utility model provides a server mainboard, this server mainboard include mainboard, first central processing unit and second central processing unit, and first central processing unit and second central processing unit interconnect through 4 x16 GOP of group. The system also comprises a PCIE slot group connected with the first central processing unit and a first data selector connected with the first central processing unit, wherein the first data selector is also connected with the PCIE slot group. The mainboard is also provided with a BMC chip connected with the first data selector, and the GPIO on the BMC chip is connected with the first data selector through the CPLD chip. Four groups of x16 GOPs are adopted to interconnect the first central processing unit and the second central processing unit, so that the transmission rate of the GOPs between the double CPUs in the double-path CPU mainboard is improved. According to actual requirements, SATA hard disks or PCIE cards can be plugged in the PCIE slot group. The SMBUS of the BMC chip is interconnected with the SMBUS interface on the PCIE slot group, and the BMC chip can monitor the card inserting state of the PCIE slot group through a remote web access window.

Description

Server mainboard and server

Technical Field

The utility model relates to a computer technology field especially relates to a server mainboard and server.

Background

The dual-path CPU main board is produced mainly for meeting the professional application requirements of a server, a graphic workstation and the like, so that the workstation main board is greatly different from a common main board, and system compatibility, BIOS function extension and the like are designed for the fields of the server, the graphic workstation and the like. Dual CPU motherboards typically use a server processor that supports dual CPU. The main board is logically a single computer, and an operating system can directly call the resources of two CPUs. If the single-path CPU main board of two ordinary computers is used, more problems are faced. Such as: there is not more display cards of space installation, two ordinary ATX mainboard connection lines are complicated and have a large amount of repeated hardware, need two power supplies to supply power, the space is compact for a long time operation simultaneously and is influenced stability. The data transmission efficiency between the double CPUs of the existing double-path CPU mainboard is low. The main board is provided with slots specially used for installing the SATA hard disk and the PCIE card, the slots cannot be compatible with each other, and the slots specially used for installing the SATA hard disk and the PCIE card occupy a larger area of the main board. And the SATA hard disk and the PCIE card are only connected with the CPU and cannot be remotely monitored.

SUMMERY OF THE UTILITY MODEL

The utility model provides a server mainboard and server for improve the transmission rate of GOP between the two CPU in the two-way CPU mainboard, realize a data selector on the two-way CPU mainboard.

In a first aspect, the present invention provides a server motherboard, which comprises a motherboard, and a first central processing unit and a second central processing unit arranged on the motherboard, wherein the first central processing unit and the second central processing unit are interconnected via 4 groups of x16 GOPs. The server mainboard further comprises a PCIE slot group arranged on the mainboard and connected with the first central processing unit, and a first data selector arranged on the mainboard and connected with the first central processing unit, wherein the first data selector is further connected with the PCIE slot group. The mainboard is also provided with a BMC chip connected with the first data selector, and the GPIO on the BMC chip is connected with the first data selector through the CPLD chip.

In the scheme, four groups of x16 GOPs are adopted to interconnect the first central processing unit and the second central processing unit, so that the transmission rate of the GOPs between the two CPUs on the two-way CPU mainboard can reach 12.8GT/S at most, and the transmission rate of the GOPs between the two CPUs in the two-way CPU mainboard is improved. Through the PCIE slot group which is compatible with the SATA hard disk or the PCIE card in plug-in connection and is arranged on the mainboard, the SATA hard disk or the PCIE card can be plugged in the PCIE slot group according to actual requirements, and the same mainboard can flexibly support various different configurations. Through adopting the BMC chip to be connected with PCIE slot group and first central processing unit through first data selector, the SMBUS of BMC chip interconnects with the SMBUS interface on the PCIE slot group, is convenient for the BMC chip to monitor the plug-in card state of PCIE slot group through long-range web access window.

In one particular embodiment, the PCIE slot group includes a plurality of PCIE x16 slots. One PCIE x16 slot of the plurality of PCIE x16 slots is connected to the first data selector through a PCIE x1 signal, and the one PCIE x16 slot is connected to the first central processor through a PCIE x15 signal. Other PCIE x16 slots of the plurality of PCIE x16 slots are all connected with the first central processing unit through PCIE x16 signals. So that the same mainboard can flexibly support various different configurations according to actual requirements in a mode of inserting the multifunctional adapter plate on the slot group.

In a specific embodiment, the motherboard is further provided with a UART chip, and the first central processing unit is further connected with the BMC chip through the UART chip. And the UART chip is also connected with a first Header, and the BMC chip is also connected with a second Header through an RS232 chip. The Local UART debugging mode can be realized, and the SOL (Serial over LAN) function can also be realized through the BMC chip, namely after the serial port information of the first central processing unit can be sent to the BMC chip, the SOL function is realized through the BMC chip, and when a remote web window which logs in the BMC chip opens an SOL interface, the serial port information of the first central processing unit can be seen, so that the remote debugging function is realized.

In a specific embodiment, the first central processing unit can transmit the thermal _ trip signal to the first Header through the CPLD chip, and the first central processing unit can transmit the Tdie temperature signal to the second Header; the first central processor can also transmit a thermal _ trip signal to the BMC chip through the CPLD chip. The temperature control module or the BMC chip of the test system can sense the temperature and other parameters of the central processing unit.

In a specific embodiment, the BMC chip is connected to the Jumper via an I2C bus, the Jumper is connected to the first central processing unit via an AMPL interface, and the Jumper is further connected to the first Header. Therefore, the heat dissipation module of the first central processing unit can be controlled to be adjusted according to different strategies.

In a specific implementation manner, the motherboard is further provided with a second data selector connected with the first central processing unit through the SPI interface, and the BMC chip is further connected with the second data selector through the SPI interface. The mainboard is also provided with a BIOS ROM chip connected with the second data selector through the SPI interface, and the function of remotely burning the BIOS ROM chip by the BMC chip is realized. Still be provided with the TCM/TPM security chip of being connected through SPI interface and first central processing unit on the mainboard, and TCM/TPM security chip still passes through SPI interface connection with second data selector for first central processing unit passes through SPI interface connection's TCM/TPM module can make the mainboard support the security module function.

In a specific embodiment, the BMC chip is further interconnected with a network PHY chip via an RMII/RGMII interface, the network PHY chip being connected to a first RJ45 network interface; the mainboard is also provided with an I350 chip, and the BMC chip is also connected with a second RJ45 network interface through the I350 chip. The BMC chip can receive external control commands through the network interface.

In a specific embodiment, the main board is further provided with a JTAG Header and a third data selector, and the JTAG Header is connected to the third data selector through a JTAG interface; the third data selector is also respectively connected with the BMC chip and the first central processing unit through a JTAG interface, and a GPIO on the BMC chip is also connected with the third data selector. Local JTAG debugging or remote JTAG debugging through a BMC chip can be realized.

In a specific embodiment, the motherboard is further provided with a power supply adjuster, the power supply adjuster is respectively connected with the first central processing unit and the second central processing unit, and the power supply adjuster is further connected with the CPLD chip, so that the CPLD chip controls the power supply modules of the first central processing unit and the second central processing unit to be powered up and down.

In a second aspect, the present invention further provides a server, which includes any one of the above server mainboards. By adopting four groups of x16 GOPs to interconnect the first central processing unit and the second central processing unit, the transmission rate of the GOPs between the two CPUs on the two-way CPU mainboard can reach 12.8GT/S at most, and the transmission rate of the GOPs between the two CPUs in the two-way CPU mainboard is improved. Through the PCIE slot group which is compatible with the SATA hard disk or the PCIE card in plug-in connection and is arranged on the mainboard, the SATA hard disk or the PCIE card can be plugged in the PCIE slot group according to actual requirements, and the same mainboard can flexibly support various different configurations. Through adopting the BMC chip to be connected with PCIE slot group and first central processing unit through first data selector, the SMBUS of BMC chip interconnects with the SMBUS interface on the PCIE slot group, is convenient for the BMC chip to monitor the plug-in card state of PCIE slot group through long-range web access window.

Drawings

Fig. 1 is a schematic block diagram of a server motherboard according to an embodiment of the present invention;

fig. 2 is a schematic connection diagram of a first cpu and a second cpu according to an embodiment of the present invention;

fig. 3 is a schematic connection diagram of a first central processing unit, a first data selector, and a BMC chip according to an embodiment of the present invention;

fig. 4 is a schematic connection diagram of a first central processing unit, a BMC chip and two headers according to an embodiment of the present invention;

fig. 5 is a schematic diagram of the transmission of the first central processing unit, the BMC chip and two Header temperature signals according to the embodiment of the present invention;

fig. 6 is a schematic diagram illustrating a connection between a first cpu, a second data selector, and a BIOS ROM according to an embodiment of the present invention;

fig. 7 is a schematic diagram illustrating a connection between a BMC chip and two RJ45 network interfaces according to an embodiment of the present invention;

fig. 8 is a schematic diagram of JTAG debugging according to an embodiment of the present invention;

fig. 9 is a schematic diagram of another JTAG debug provided by an embodiment of the present invention;

fig. 10 is a schematic diagram of another JTAG debug provided by an embodiment of the present invention;

fig. 11 is a schematic diagram of a BMC chip controlling the power-up or Reset of the CPU according to an embodiment of the present invention;

fig. 12 is a schematic connection diagram of a DDR memory according to an embodiment of the present invention.

Reference numerals:

10-mainboard 11-first central processing unit 12-second central processing unit

21-PCIE slot group 22-first data selector 23-BMC chip 24-CPLD chip

31-UART chip 32-first Header 33-second Header34-RS232 chip 35-Jumper

41-BIOS ROM chip 42-TCM/TPM security chip 43-second data selector

51-first RJ45 network interface 52-second RJ45 network interface 53-I350 chip

61-JTAG Header 62-third data selector 63-Power regulator

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

For the convenience of understanding the utility model provides a server mainboard, first explain the utility model provides an application scene of server mainboard that the embodiment of the utility model provides is provided in the server, this server mainboard is applied to as the hardware that realizes each function of server. The server motherboard will be described in detail with reference to the drawings.

Referring to fig. 1, fig. 2 and fig. 3, an embodiment of the present invention provides a server motherboard including a motherboard 10, and a first central processing unit 11 and a second central processing unit 12 disposed on the motherboard 10, wherein the first central processing unit 11 and the second central processing unit 12 are interconnected through 4 groups of x16 GOPs. The server motherboard further includes a PCIE slot group 21 disposed on the motherboard 10 and connected to the first central processing unit 11, and a first data selector 22 disposed on the motherboard 10 and connected to the first central processing unit 11, where the first data selector 22 is further connected to the PCIE slot group 21. The main board 10 is further provided with a BMC chip 23 connected to the first data selector 22, and the GPIO on the BMC chip 23 is connected to the first data selector 22 through the CPLD chip 24.

In the above scheme, four groups of x16 GOPs are used to interconnect the first central processing unit 11 and the second central processing unit 12, so that the highest transmission rate of GOPs between two CPUs on the two-way CPU board 10 can reach 12.8GT/S, and the transmission rate of GOPs between two CPUs in the two-way CPU board 10 is improved. Through the PCIE slot group 21 which is compatible with the SATA hard disk or the PCIE card in plug-in connection and is arranged on the mainboard 10, the SATA hard disk or the PCIE card can be plugged in the PCIE slot group 21 according to actual requirements, and the same mainboard 10 can flexibly support various different configurations. By adopting the BMC chip 23 to be connected with the PCIE slot group 21 and the first central processing unit 11 through the first data selector 22, the SMBUS bus of the BMC chip 23 is interconnected with the SMBUS interface on the PCIE slot group 21, so that the BMC chip 23 can monitor the card insertion state of the PCIE slot group 21 through the remote web access window. The configuration of each hardware described above will be described in detail with reference to the drawings.

Referring to fig. 1 and 2, the server motherboard includes a motherboard 10, and the motherboard 10 is a printed circuit board capable of being configured with devices such as a central processing unit. The main board 10 is provided with a first central processing unit 11 and a second central processing unit 12, and the first central processing unit 11 and the second central processing unit 12 are interconnected through 4 groups of x16 GOPs, so that the transmission rate of the GOPs between the two CPUs on the two-way CPU main board 10 can reach 12.8GT/S at most, and the transmission rate of the GOPs between the two CPUs in the two-way CPU main board 10 is improved. When the first central processing unit 11 and the second central processing unit 12 are disposed on the motherboard 10, two CPU slots may be disposed on the motherboard 10, and the first central processing unit 11 and the second central processing unit 12 are respectively mounted on the two CPU slots. The two CPU slots may be sockets or slots. When the first central processing unit 11 and the second central processing unit 12 are disposed, the first central processing unit 11 may be a main central processing unit, and the second central processing unit 12 may be a sub-central processing unit. Specifically, when the models of the first central processing unit 11 and the second central processing unit 12 are selected, two pieces of the Hai-Fi 7100/7200CPU chips can be selected as the first central processing unit 11 and the second central processing unit 12. When the first CPU 11 and the second CPU 12 are specifically connected, the first CPU 11 and the second CPU 12 may be selected to be interconnected by 4 groups of x16 GOPs, and the highest rate is 12.8GT/S, and the connection relationship is shown in fig. 2, so as to improve the transmission rate of GOPs between the two CPUs in the two-way CPU board 10.

Referring to fig. 1 and fig. 3, a PCIE slot group 21 connected to the first central processing unit 11 and a first data selector 22 connected to the first central processing unit 11 are further disposed on the main board 10, and the first data selector 22 is further connected to the PCIE slot group 21. The PCIE slot group 21 is used to connect an SATA hard disk or a PCIE card in an inserting manner. According to actual requirements, a SATA hard disk or a PCIE card can be plugged into the PCIE slot group 21, so that the same motherboard 10 can flexibly support various different configurations.

Referring to fig. 1 and 3, a BMC chip 23 connected to the first data selector 22 is further disposed on the motherboard 10, a GPIO on the BMC chip 23 is connected to the first data selector 22 through a CPLD chip 24, and an SMBUS bus of the BMC chip 23 is interconnected with an SMBUS interface on the PCIE slot group 21. By adopting the BMC chip 23 to be connected with the PCIE slot group 21 and the first central processing unit 11 through the first data selector 22, the SMBUS bus of the BMC chip 23 is interconnected with the SMBUS interface on the PCIE slot group 21, so that the BMC chip 23 can monitor the state of the PCIE slot group 21 through a remote web access window.

Taking fig. 3 as an example, the PCIE slot group 21 may include a plurality of PCIE x16 slots, specifically, the number of PCIE x16 slots may be 2, 3, 4, 5, 6, and the like. As shown in fig. 3, one PCIE x16 slot of the PCIE x16 slots is connected to the first data selector 22 through PCIE x1 signals, and the one PCIE x16 slot is connected to the first central processor 11 through PCIE x15 signals. The other PCIE x16 slots of the plurality of PCIE x16 slots are all connected to the first central processor 11 through PCIE x16 signals. So that the same main board 10 can flexibly support various different configurations according to actual requirements in a form of inserting the multifunctional adapter board into the slot group.

Specifically, the x16 signal connected by the Slot1 and the Slot3 Slot comes from the COMB PHY (function configurable interface) of the first central processing unit 11, and can be converted into 4 XGBE network interfaces, 4 SATA interfaces and 1 x8 PCIE Slot by inserting a multifunctional patch board into the Slot. When the multifunctional adapter board is not inserted, 1 PCIE direct card of x16/x8/x4/x2/x1 is supported, and the card with other PCIE widths can be supported by inserting the Riser card, such as 2 PCIE x8 slots or 1 x8, 2 x4 PCIE slots and the like, so that the same mainboard 10 can flexibly support various different configurations according to actual requirements. The x16 signal connected with the Slot2 and the Slot4 Slot comes from a PCIE PHY of a CPU, only supports a PCIE protocol, supports 1 PCIE direct card of x16/x8/x4/x2/x1, and can support other PCIE width cards such as 2 PCIE x8 slots or 1 x8, 2 x4 PCIE slots and the like through a Riser card.

The system comprises a PCIE signal used for connecting a Slot4, a group of x1 signals are switched through a first data selector 22, the Slot4 can be selected to be connected, the card inserting function is realized, the system can also be connected to a BMC chip 23, the display of an onboard BMC chip 23 and the functions of ikvm (keyboard Video Mouse over IP) are realized, and therefore the picture displayed by the VGA of the system can be seen in a remote web access window of the BMC chip 23, and the current VGA picture can be remotely monitored.

Referring to fig. 4, a UART chip 31 may be further disposed on the motherboard 10, and the first central processor 11 may be connected to the BMC chip 23 through the UART chip 31. The UART chip 31 is further connected to a first Header32, and the BMC chip 23 is further connected to a second Header33 through the RS232 chip 34. The Local UART debugging mode can be realized, and the SOL (Serial over LAN) function can also be realized through the BMC chip 23, namely after the serial port information of the first central processing unit 11 can be sent to the BMC chip 23, the SOL function is realized through the BMC chip 23, when a remote web window of the BMC chip 23 is logged on and an SOL interface is opened, the serial port information of the first central processing unit 11 can be seen, and therefore the remote debugging function is realized.

Referring to the schematic diagram of the interactive interface connection of the temperature control system shown in fig. 5, the first central processing unit 11 can transmit thermal _ trip signal to the first Header32 through the CPLD chip 24, and the first central processing unit 11 can transmit Tdie temperature signal to the second Header 33; the first central processor 11 can also transmit a thermal _ trip signal to the BMC chip 23 through the CPLD chip 24. By adopting the connection mode, the first central processing unit 11 respectively connects the temperature-related signal, the thermal _ trip and the Tdie temperature signal, and the Tman temperature transmitted by the AMPL interface to the first Header32, the second Header33 and the BMC chip 23, so that the temperature control module or the BMC chip 23 of the test system can sense the temperature and other parameters of the central processing unit.

With continued reference to fig. 5, the BMC chip 23 may also be connected to the Jumper35 (Jumper) via an I2C bus, the Jumper35 is connected to the first central processor 11 via an AMPL interface, and the Jumper35 is also connected to the first Header 32. So that the heat dissipation module of the first central processing unit 11 can be controlled to adjust according to different strategies.

Referring to fig. 6, a second data selector 43 connected to the first central processor 11 through the SPI interface may be further provided on the motherboard 10, and the BMC chip 23 is further connected to the second data selector 43 through the SPI interface. The motherboard 10 is further provided with a BIOS ROM chip 41 connected to the second data selector 43 through an SPI interface, so that the BMC chip 23 remotely burns the BIOS ROM chip 41. In specific application, the interfaces of the first central processor 11 and the SPI0(DI/DO/HOLD _ L/WP _ L/CS0) of the BMC chip 23 are switched by the second data selector 43, and the second data selector 43 is connected to the first central processor 11 by default. After the motherboard 10 is powered on and started, the first central processing unit 11 captures firmware from the BIOS ROM chip 41 to initialize the motherboard 10, and when the first central processing unit 11 on the motherboard 10 does not need to start the BIOS, the BMC chip 23 can control the second data selector 43 to switch the SPI path to connect with the BMC chip 23 through the GPIO, so as to remotely burn the BIOS ROM chip 41. After the BMC chip 23 finishes burning, the GPIO is controlled to switch the BIOS ROM chip 41 to connect to the first central processor 11, and after the motherboard 10 is restarted, the first central processor 11 starts the motherboard 10 from the BIOS ROM chip 41, thereby implementing the function of remotely burning the BIOS by the BMC chip 23.

With continued reference to fig. 6, a TCM/TPM security chip 42 connected to the first central processing unit 11 through an SPI interface may be further disposed on the motherboard 10, and the TCM/TPM security chip 42 is further connected to the second data selector 43 through the SPI interface, so that the TCM/TPM module connected to the first central processing unit 11 through the SPI interface enables the motherboard 10 to support the security module function.

Referring to fig. 7, the BMC chip 23 may also be interconnected to a network PHY chip via an RMII/RGMII interface, the network PHY chip being connected to a first RJ45 network interface 51; the main board 10 is further provided with an I350 chip 53, and the BMC chip 23 is further connected to a second RJ45 network interface 52 through the I350 chip 53. So that the BMC chip 23 can accept external control commands through the network interface. Specifically, the motherboard 10 may use the ASPEED AST2500 BMC chip 23 as a management system to perform startup, shutdown, and restart control on the motherboard 10 system, and monitor firmware burning, system errors, alarms, temperature, voltage, and the like, in which the BMC chip 23 may receive external control commands through two RJ45 network interfaces.

Referring to fig. 1, a JTAG Header61 and a third data selector 62 may also be disposed on the main board 10, and the JTAG Header61 is connected to the third data selector 62 through a JTAG interface; the third data selector 62 is further connected to the BMC chip 23 and the first central processor 11 through a JTAG interface, respectively, and the GPIO on the BMC chip 23 is further connected to the third data selector 62. Local JTAG debugging may be implemented or remote JTAG debugging may be performed through the BMC chip 23. Specifically, when JTAG debugging is performed, reference is made to schematic diagrams shown in fig. 8 to 10. Fig. 8 is a schematic connection diagram for debugging TCK and TMS of JTAG, fig. 9 is a schematic connection diagram for debugging TRST and DBREQ of JTAG, and fig. 10 is a schematic connection diagram for debugging TDI and TDO of JTAG.

Referring to fig. 1 and 11, a power regulator 63(VR) may also be disposed on the motherboard 10, the power regulator 63 is respectively connected to the first central processing unit 11 and the second central processing unit 12, and the power regulator 63 is further connected to the CPLD chip 24, so that the CPLD chip 24 controls the power supply modules of the first central processing unit 11 and the second central processing unit 12 to be powered up and down. The mainboard 10 adopts the CPLD chip 24 to carry out power-on and power-off control on the power supply regulator 63(VR), and the power supply regulator 63 for supplying power to the central processing unit and the power-on and power-off time sequence of signals input to the central processing unit can be flexibly adjusted through logic codes, so that the requirements of the power-on and power-off sequence of the central processing unit are met. The BMC chip 23 performs power-on/power-off control on the motherboard 10, and the Reset control circuit controls the PWR BTN signal and the RST BTN signal of the central processing unit through the BMC chip 23 as shown in fig. 11 below, so as to implement power-on and power-off control on the motherboard 10.

Referring to fig. 12, each of the first cpu 11 and the second cpu 12 has 4 DDR channels, each Channel is connected to 2 DIMMs, and a single cpu supports 8 DDR4 memory slots. The motherboard 10 supports 16 DDR4 memory slots altogether, the memory frequency can reach 3200MHz at most, and RDIMM and LRDIMM are supported. The connection relationship is as shown in the following FIG. 12, each central processor mounts 8 DDR4 DIMM slots, supports UDIMM/RDIMM/LRDIMM/NVDIMM, and supports DDR 4-2667.

Referring to fig. 1, the second central processor 12 supports 8 SATA3.0 hard disks. The main board 10 is also designed with a USB3.0 interface to directly interconnect with the first central processing unit 11.

By adopting four groups of x16 GOPs to interconnect the first central processing unit 11 and the second central processing unit 12, the transmission rate of the GOPs between the two CPUs on the two-way CPU mainboard 10 can reach 12.8GT/S at most, and the transmission rate of the GOPs between the two CPUs in the two-way CPU mainboard 10 is improved. Through the PCIE slot group 21 which is compatible with the SATA hard disk or the PCIE card in plug-in connection and is arranged on the mainboard 10, the SATA hard disk or the PCIE card can be plugged in the PCIE slot group 21 according to actual requirements, and the same mainboard 10 can flexibly support various different configurations. By adopting the BMC chip 23 to be connected with the PCIE slot group 21 and the first central processing unit 11 through the first data selector 22, the SMBUS bus of the BMC chip 23 is interconnected with the SMBUS interface on the PCIE slot group 21, so that the BMC chip 23 can monitor the card insertion state of the PCIE slot group 21 through the remote web access window.

In a second aspect, the present invention further provides a server, referring to fig. 1, fig. 2 and fig. 3, the server includes any one of the above server motherboards. By adopting four groups of x16 GOPs to interconnect the first central processing unit 11 and the second central processing unit 12, the transmission rate of the GOPs between the two CPUs on the two-way CPU mainboard 10 can reach 12.8GT/S at most, and the transmission rate of the GOPs between the two CPUs in the two-way CPU mainboard 10 is improved. Through the PCIE slot group 21 which is compatible with the SATA hard disk or the PCIE card in plug-in connection and is arranged on the mainboard 10, the SATA hard disk or the PCIE card can be plugged in the PCIE slot group 21 according to actual requirements, and the same mainboard 10 can flexibly support various different configurations. By adopting the BMC chip 23 to be connected with the PCIE slot group 21 and the first central processing unit 11 through the first data selector 22, the SMBUS bus of the BMC chip 23 is interconnected with the SMBUS interface on the PCIE slot group 21, so that the BMC chip 23 can monitor the card insertion state of the PCIE slot group 21 through the remote web access window.

The above description is only for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A server board, comprising:

a main board;

the first central processing unit and the second central processing unit are arranged on the mainboard and are interconnected through 4 groups of x16 GOPs;

the PCIE slot group is arranged on the mainboard and connected with the first central processing unit;

the first data selector is arranged on the mainboard and connected with the first central processing unit, and the first data selector is also connected with the PCIE slot group;

the BMC chip is arranged on the mainboard and connected with the first data selector, and the GPIO on the BMC chip is connected with the first data selector through a CPLD chip.

2. The server motherboard of claim 1 wherein the set of PCIE slots comprises a plurality of PCIE x16 slots;

one PCIE x16 slot of the plurality of PCIE x16 slots is connected to the first data selector through a PCIE x1 signal, and the one PCIE x16 slot is connected to the first central processor through a PCIE x15 signal;

other PCIE x16 slots of the plurality of PCIE x16 slots are connected with the first central processing unit through PCIE x16 signals.

3. The server motherboard of claim 1, wherein the motherboard further comprises a UART chip, and the first central processor is further connected to the BMC chip via the UART chip;

and the UART chip is also connected with a first Header, and the BMC chip is also connected with a second Header through an RS232 chip.

4. The server motherboard of claim 3 wherein said first central processor is capable of transmitting a thermal _ trip signal to said first Header via said CPLD chip, said first central processor being capable of transmitting a Tdie temperature signal to said second Header;

the first central processor can also transmit a thermal _ trip signal to the BMC chip through the CPLD chip.

5. The server motherboard of claim 4 wherein the BMC chip is coupled to a Jumper via an I2C bus, the Jumper coupled to the first central processor via an AMPL interface, the Jumper further coupled to the first Header.

6. The server mainboard of claim 1, wherein the mainboard is further provided with a second data selector connected with the first central processing unit through an SPI interface, and the BMC chip is further connected with the second data selector through an SPI interface;

the main board is also provided with a BIOS ROM chip connected with the second data selector through an SPI interface;

the main board is also provided with a TCM/TPM security chip connected with the first central processing unit through an SPI interface, and the TCM/TPM security chip is also connected with the second data selector through an SPI interface.

7. The server motherboard of claim 1 wherein the BMC chip is further coupled to a first RJ45 network interface via a COMB PHY interface;

the main board is further provided with an I350 chip, and the BMC chip is further connected with a second RJ45 network interface through the I350 chip.

8. The server main board according to claim 1, wherein the main board is further provided with a JTAG Header and a third data selector, and the JTAG Header is connected to the third data selector through a JTAG interface;

the third data selector is further connected with the BMC chip and the first central processing unit through a JTAG interface respectively, and a GPIO on the BMC chip is further connected with the third data selector.

9. The server motherboard of claim 1 further comprising a power regulator, wherein the power regulator is connected to the first cpu and the second cpu, and the power regulator is further connected to the CPLD chip.

10. A server, comprising a server board according to any one of claims 1 to 9.