CN107888336B - Satellite-borne ADS-B signal header detection system and method - Google Patents
Satellite-borne ADS-B signal header detection system and method Download PDFInfo
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- CN107888336B CN107888336B CN201711081745.5A CN201711081745A CN107888336B CN 107888336 B CN107888336 B CN 107888336B CN 201711081745 A CN201711081745 A CN 201711081745A CN 107888336 B CN107888336 B CN 107888336B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
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- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
- H04L69/161—Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
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Abstract
The invention provides a system and a method for detecting a satellite-borne ADS-B signal header, wherein the system comprises: the envelope extraction module is used for carrying out envelope extraction on the baseband signals of the received two paths of orthogonal signals to obtain envelope signals; the AGC module is connected with the output end of the envelope extraction module and is used for carrying out automatic gain control on the envelope signal; the filtering module is connected with the output end of the AGC module and is used for filtering the envelope signal processed by the AGC module; the digital phase-locked loop is connected with the output end of the filtering module and used for realizing the tracking of the local clock on the signal processed by the filtering module and outputting bit synchronization pulse; and the header frame detection module is used for acquiring header data according to the position of the bit synchronization pulse, carrying out frame synchronization with a preset header data format, and if the frame synchronization can be locked, the frame detection is passed to obtain a header frame. The problem that the sensitivity of the traditional ADS-B receiver is not enough is solved.
Description
Technical Field
The invention relates to the field of digital signal processing, in particular to a system and a method for detecting a satellite-borne ADS-B signal header.
Background
The broadcast type automatic correlation monitoring (ADS-B) adopts omnidirectional broadcast to play the air position information, air speed information, identity information, working condition and state information, etc. the airplane automatically sends 1090MHz frequency signals to the airplane, vehicle and ground receiving equipment. The ADS-B signal receiver can realize air-to-air monitoring and air-to-ground monitoring, and can also realize other functions, such as: the mutual positions of the aircrafts in the air are automatically identified, and the safety distance is kept; the ground receiving station can monitor and command the aircraft flying by the air route.
The coverage radius of the satellite-borne ADS-B receiver can reach 3000km, which is a great advantage compared with the coverage radius of the ground receiver of 160 km. The global coverage is improved from about 10% to 100% at present when the ADS-B system is carried on the satellite.
To realize a satellite-borne ADS-B receiver, the following technical difficulties mainly exist:
the on-board transmitter system does not make corresponding improvements to accommodate the on-board satellite system resulting in low satellite received power and therefore, the receiver sensitivity needs to be improved to detect and resolve the information. Theoretically, under on-board conditions, the receiver sensitivity must reach-109 dbm to achieve complete reception of signals within the coverage area of the satellite antenna. At present, the highest sensitivity requirement of D0-260B on an ADS-B receiver of class A is only-84 dbm (index for realizing 90% signal reception without interference), which is 25db different from the actual satellite-borne environment requirement. Therefore, the existing ADS-B receiver cannot meet the requirements.
Disclosure of Invention
The invention aims to solve the technical problem of providing a system and a method for detecting the header of a satellite-borne ADS-B signal, and solving the problem of insufficient sensitivity of the traditional ADS-B receiver.
In order to solve the above problem, the present invention provides a system for detecting a header of an ADS-B signal on a satellite, including:
the envelope extraction module is used for carrying out envelope extraction on the baseband signals of the received two paths of orthogonal signals to obtain envelope signals;
the AGC module is connected with the output end of the envelope extraction module and is used for carrying out automatic gain control on the envelope signal;
the filtering module is connected with the output end of the AGC module and is used for filtering the envelope signal processed by the AGC module;
the digital phase-locked loop is connected with the output end of the filtering module and used for realizing the tracking of the local clock on the signal processed by the filtering module and outputting bit synchronization pulse;
and the header frame detection module is used for acquiring header data according to the position of the bit synchronization pulse, carrying out frame synchronization with a preset header data format, and if the frame synchronization can be locked, the frame detection is passed to obtain a header frame.
According to an embodiment of the present invention, further comprising:
the DF check module is used for judging the acquired data value of the DF bit in the header frame which is detected to pass by the header frame detection module, and if the acquired data value is equal to the default data format of the DF bit, the DF check module passes;
and the power consistency detection module is used for carrying out consistency detection on the power of the bit data which is 1 in the header frame and passes the verification of the DF verification module so as to enable the fluctuation to be within a certain threshold range.
According to an embodiment of the present invention, the envelope module obtains two orthogonal baseband signals i (k) and q (k) after sampling by the ADC, and performs modulo operation on i (k) and q (k):
an envelope signal s (k) is obtained.
According to one embodiment of the invention, the AGC module comprises: a divider, an accumulator and an IIR loop filter;
the divider realizes automatic gain control on signal intensity according to an automatic gain control coefficient fed back by the IIR loop filter and outputs a controlled envelope signal;
the accumulator receives the envelope signal, estimates the signal intensity and outputs the estimated value to the IIR loop filter;
and the IIR loop filter receives the estimated value, carries out noise filtering on the estimated value and outputs an automatic gain control coefficient.
According to one embodiment of the invention, the filtering module comprises:
self-phaseA filter for performing autocorrelation operation on the envelope signal S (k) processed by the AGC module to obtain a signal S1(k) And calculating a formula:
cross-correlation filter for the signal S output from the autocorrelation filter1(k) Performing cross-correlation operation to obtain signal S2(k) And calculating a formula:
S2(k)＝(S1(k-1)coef(1)+S1(k-2)coef(2)+…+S1(k-n) coef (n)), coef (1), coef (1), … coef (n) are preset matching coefficients;
and the narrow-band filter is used for filtering the signal output by the cross-correlation filter, and the pass band of the narrow-band filter is the bandwidth of the signal.
According to one embodiment of the invention, the digital phase locked loop comprises: the device comprises a homodromous integrator, a quadrature integrator, a first sample holder, a second sample holder, a phase discriminator and a controller;
the homodromous integrator and the orthogonal integrator respectively integrate the envelope signals subjected to filtering processing and respectively output a signal b and a signal c; the integration time of the homodromous integrator and the quadrature integrator is the code element period T and is controlled by the bit synchronization pulse, so that the integration interval of the homodromous integrator is superposed with the interval of the bit synchronization pulse, and the integration interval of the quadrature integrator just spans between the middle points of two adjacent bit synchronization pulses;
the first sampling holder and the second sampling holder are respectively connected with the output ends of the homodromous integrator and the orthogonal integrator and are respectively used for sampling and holding the signal b and the signal c and prolonging the duration time to a code element period time T to obtain a signal e and a signal f;
the phase discriminator is used for detecting the phases of the signal e and the signal f to determine the phase lead or lag of the bit synchronization pulse, outputting a leading pulse k when the phase of the bit synchronization pulse is leading, and outputting a lagging pulse j when the phase of the bit synchronization pulse is lagging;
the controller is used for controlling the phase of the bit synchronization pulse to move backwards and controlling the phase of the bit synchronization pulse to move forwards according to the phase discrimination result of the phase discriminator.
According to one embodiment of the invention, the phase detector comprises:
a transition edge detector connected to the output of the first sample-and-hold device for detecting the transition edge of the signal e and generating a narrow pulse signal g at each transition;
an exclusive-or gate connected to the output ends of the first and second sample-and-hold units, for performing exclusive-or operation on the signal e and the signal f, and outputting a signal h;
the first AND gate receives the narrow pulse signal g and the inverted signal of the signal h, and performs an AND operation on the narrow pulse signal g and the inverted signal of the signal h to output a lagging pulse j;
and the second AND gate receives the narrow pulse signal g and the signal h, and performs an AND operation on the narrow pulse signal g and the signal h to output a leading pulse k.
According to one embodiment of the invention, the system further comprises a crystal oscillator and a converter; the crystal oscillator outputs a clock signal; the converter receives the clock signal, down-converts the clock signal and generates a pulse sequence clk _ d1 and a pulse sequence clk _ d2 which are staggered with each other by one clock cycle and have the frequency of a preset multiple of the data frequency;
when the controller detects the leading pulse k or the lagging pulse j, a high level signal is generated, and a pulse signal in the pulse sequence clk _ d1 or a pulse signal in the pulse sequence clk _ d2 is output.
According to one embodiment of the invention, the device further comprises a frequency divider and a pulse shaper; the frequency divider is connected with the output end of the controller, and the pulse former is connected with the output end of the frequency divider; the pulse signal output by the controller passes through the frequency divider and the pulse former and then outputs a bit synchronization pulse.
According to an embodiment of the present invention, a digital filter is further included, and is connected between the phase detector and the controller, the digital filter includes:
the random loitering filter receives the leading pulse and the lagging pulse output by the phase discriminator, and respectively filters and counts the leading pulse and the lagging pulse and outputs the filtered leading pulse and the lagging pulse;
the first divider is used for receiving the counting result and the leading pulse output by the random loitering filter, clearing the sporadic leading pulse according to the counting result and outputting a first clear signal;
the second divider is used for receiving the counting result and the lagging pulse output by the random loitering filter, clearing the scattered lagging pulse according to the counting result and outputting a first clearing signal;
the input end of the third AND gate receives the leading pulse and the first zero clearing signal, and the input end of the third AND gate is connected with the leading pulse and the first zero clearing signal in an AND mode so as to output the leading pulse when the leading pulse is not zero clearing;
and the input end of the fourth AND gate receives the lag pulse and the second zero clearing signal, and the lag pulse is output when the lag pulse is not zero clearing by taking the two phases together.
The invention also provides a method for detecting the header of the satellite-borne ADS-B signal, which comprises the following steps:
s1: carrying out envelope extraction on baseband signals of the received two paths of orthogonal signals to obtain envelope signals;
s2: performing automatic gain control on the envelope signal;
s3: carrying out filtering processing on the envelope signal subjected to the automatic gain control processing;
s4: tracking the signal processed by the filtering module by the local clock and outputting a tracked bit synchronization pulse;
s5: and acquiring data according to the position of the bit synchronization pulse, carrying out frame synchronization with a preset header data format, and if the frame synchronization can be locked, passing the frame detection to obtain a header frame.
S6: judging the acquired data value of the DF bit in the header frame which passes the detection, and if the acquired data value is equal to the data format of the default DF bit, checking to pass;
s7: and carrying out consistency detection on the power of the bit data of 1 in the header frame passing the verification so as to enable the fluctuation to be within a certain threshold range.
After the technical scheme is adopted, compared with the prior art, the invention has the following beneficial effects:
1. the amplitude control function of AGC is provided, and higher dynamic requirements can be met;
2. compared with the traditional method without clock recovery, the clock tracking recovery method adopting the integral phase-locked loop has about 3db of gain, thereby greatly improving the detection range of the receiver;
3. the digital filter is adopted to suppress clock jitter, and the anti-interference function is achieved under the condition of low signal-to-noise ratio.
Drawings
Fig. 1 is a block diagram of a structure of a satellite-borne ADS-B signal header detection system according to an embodiment of the present invention;
fig. 2 is a block diagram of an AGC module according to an embodiment of the present invention;
FIG. 3 is a block diagram of a digital PLL according to an embodiment of the present invention;
fig. 4 is a block diagram of a digital filter according to an embodiment of the invention.
Fig. 5 is a flowchart illustrating a method for detecting a header of a satellite-borne ADS-B signal according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather construed as limited to the embodiments set forth herein.
Referring to fig. 1, in one embodiment, an on-board ADS-B signal header detection system includes: an envelope extraction module N1, an AGC module N2, a filtering module, a digital phase locked loop N6 and a header frame detection module N8.
The satellite-borne ADS-B signal header detection system can be realized based on a digital circuit of an FPGA (field programmable gate array), the processed signal can be a digital baseband signal sampled by an ADC (analog-to-digital converter), optionally, the sampling rate is 32MHz, and the bandwidth of the baseband signal is 1.5 MHz.
The envelope extraction module N1 is configured to perform envelope extraction on the baseband signals of the two paths of received orthogonal signals to obtain an envelope signal.
Preferably, the I/Q two-path orthogonal signals are subjected to modulo operation, so as to extract the envelope s (k) of the baseband signal. Specifically, the envelope extraction module N1 obtains two orthogonal baseband signals i (k) and q (k) sampled by the ADC, and performs modulo operation on i (k) and q (k):
an envelope signal s (k) is obtained. The envelope extraction module N1 may thus also be regarded as a modulo module.
For the root number operation, the embodiment of the invention adopts an iterative operation method:
let x1Has a value of greater than
Only a few iterations are needed to obtain an approximation
The numerical value of (c).
An AGC (automatic gain control) block N2 is connected to the output of the envelope extraction block N1, receives the envelope signal, and performs automatic gain control on the envelope signal.
Referring to fig. 2, in one embodiment, the AGC block N2 includes: divider, accumulator and IIR loop filter. The divider realizes automatic gain control on signal intensity according to an automatic gain control coefficient fed back by the IIR loop filter and outputs a controlled envelope signal; the accumulator receives the envelope signal, estimates the signal intensity and outputs the estimated value to the IIR loop filter; and the IIR loop filter receives the estimated value, carries out noise filtering on the estimated value and outputs an automatic gain control coefficient.
The envelope signal passes through an AGC block N2 to control its signal amplitude level to meet the dynamic requirements. The envelope signal is passed through a divider to achieve automatic gain control of the signal strength. The automatic gain control coefficient of the divider is obtained by a feedback loop. The input envelope signal is estimated through an accumulator to obtain the signal intensity, then the estimated value is filtered by a second-order IIR loop filter to remove noise, the output of the loop filter is the automatic gain control coefficient, then the output automatic gain control coefficient is fed back to the input end of the divider to be divided by the input envelope signal, and the controlled envelope signal S (k) is output.
The filtering module is connected to the output end of the AGC module N2, and is configured to perform filtering processing on the envelope signal processed by the AGC module N2.
With continued reference to fig. 1, the filtering module includes an autocorrelation filter N3, a cross-correlation filter N4, and a narrow-band filter N5 connected in series. Other filters are of course possible. The autocorrelation filter N3 is connected to the output of the AGC block N2 and the narrow band filter N5 is connected to the input of the digital phase locked loop N6.
The autocorrelation filter N3 is used for performing autocorrelation operation on the envelope signal S (k) processed by the AGC block N2 to obtain a signal S1(k) And calculating a formula:
The cross-correlation filter N4 is used to process the signal S output from the autocorrelation filter N31(k) Performing cross-correlation operation to obtain signal S2(k) And calculating a formula:
S2(k)＝(S1(k-1)coef(1)+S1(k-2)coef(2)+…+S1(k-n) coef (n)), coef (1), coef (1), … coef (n) are preset matching coefficients, and can be stored in the RAM of the FPGA in advance to match with the received signal (i.e. the concept of a classical matching filter in digital signal processing), and n can be set to 5.
The narrow band filter N5 is used to filter the signal output by the cross-correlation filter N4, with the pass band being the bandwidth of the signal. Preferably, the narrow-band filter N5 is a high-order narrow-band FIR (Finite Impulse Response, Finite single-bit Impulse Response) filter, and the signal output by the cross-correlation process is filtered by a high-order narrow-band FIR filter to remove noise, where the passband of the FIR filter is the bandwidth of the information signal.
The digital phase-locked loop N6 is connected with the output end of the filtering module and used for realizing the tracking of the local clock on the signal processed by the filtering module and outputting the bit synchronization pulse. The tracking of the signal clock by the local clock is performed using a digital phase locked loop N6.
The signal after passing through the FIR filter is a relatively real information signal with a part of noise filtered, but since the local clock and the signal clock are incoherent, the phase (i.e., the starting point of the signal) of the local clock is not known. In the present invention, an integral digital phase locked loop is used to recover this clock.
Referring to fig. 3, the digital phase locked loop may include: the device comprises a homodromous integrator, a quadrature integrator, a first sample holder, a second sample holder, a phase detector and a controller.
The homodromous integrator and the orthogonal integrator respectively integrate the envelope signals subjected to filtering processing and respectively output a signal b and a signal c; the integration time of the homodromous integrator and the quadrature integrator is the code element period T and is controlled by the bit synchronization pulse, so that the integration interval of the homodromous integrator is coincided with the interval of the bit synchronization pulse, and the integration interval of the quadrature integrator just spans between the middle points of two adjacent bit synchronization pulses. The bit synchronization pulse can be directly input into the homodromous integrator and then input into the quadrature integrator after the delay of T/2 through the delay device.
And the first sampling holder and the second sampling holder are respectively connected with the output ends of the homodromous integrator and the quadrature integrator and are respectively used for sampling and holding the signal b and the signal c, and the duration is prolonged to one code element period time T to obtain a signal e and a signal f.
The phase discriminator is used for detecting the phases of the signal e and the signal f to determine the phase lead or lag of the bit synchronization pulse, outputting a leading pulse k when the phase of the bit synchronization pulse is leading, and outputting a lagging pulse j when the phase of the bit synchronization pulse is lagging.
The controller is used for controlling the phase of the bit synchronization pulse to move backwards and controlling the phase of the bit synchronization pulse to move forwards according to the phase discrimination result of the phase discriminator.
Further, the phase detector includes: a transition edge detector, an exclusive-or gate, a first and gate and a second and gate. A transition edge detector is coupled to the output of the first sample-and-hold device for detecting a transition edge of the signal e and generating a narrow pulse signal g at each transition. And the exclusive-OR gate is connected with the output ends of the first sampling holder and the second sampling holder and is used for carrying out exclusive-OR on the signal e and the signal f and outputting a signal h. And the first AND gate receives the narrow pulse signal g and the inverted signal of the signal h, and performs an AND operation on the narrow pulse signal g and the inverted signal to output a lagging pulse j. And the second AND gate receives the narrow pulse signal g and the signal h, and performs an AND operation on the narrow pulse signal g and the signal h to output a leading pulse k.
Specifically, the signals are integrated by the homodromous integrator and the quadrature integrator, the integration time of the homodromous integrator is the same as the symbol period T, the integration interval of the homodromous integrator is overlapped with the interval of the bit synchronization pulse, the integration interval of the quadrature integrator is just enlarged between the key points of two adjacent synchronization pulses, the integration intervals of the quadrature integrator are just different by T/2, if the phase of the bit synchronization pulse is advanced, the polarity of the output voltage of the two integrators is the same, otherwise, if the phase of the bit synchronization pulse is delayed, the polarity of the output voltage of the two integrators is opposite. By using this rule, it is possible to determine whether the bit sync pulse is leading or lagging.
In fig. 3, the outputs of the homodyne integrator and the quadrature integrator are signal b and signal c, respectively. Then, the duration of the signals b and c is extended to one symbol period time T by the first and second sample-holders, thereby obtaining the signals e and f. After the signal e passes through a transition edge detector, specifically, a differential rectifier (outputting a pulse signal at each transition of the signal) and a monostable circuit (continuously outputting a high-level pulse signal for a certain time length when detecting the high-level pulse signal), a zero-crossing point is detected, and a narrow pulse signal g is formed, wherein the narrow pulse signal g enables the first and gate a1 and the second and gate B1 to be opened only when data change exists, and the signal e and the signal f modulo 2 are subjected to exclusive-or through an exclusive-or gate to obtain a signal h. There is a relationship between signals h and g: when the bit sync pulse is advanced, the narrow pulse of signal g falls within the high range of signal h, which corresponds to the same polarity of the two integrator outputs, and the signal h and signal g are anded, and an advanced pulse k is output from the second and gate B1, which shifts the phase of the bit sync pulse backward. Similarly, when the bit sync pulse lags, the narrow pulse of signal g falls within the low range of signal g, which corresponds to the opposite polarity of the two integrator outputs, and the signal h is negated and anded with signal g, a lagging pulse j is output from the first and gate a1, causing the bit sync phase to move forward. This repeatedly adjusts the phase, and bit synchronization is achieved.
Preferably, the satellite-borne ADS-B signal header detection system further comprises a crystal oscillator and a converter. The crystal oscillator outputs a clock signal; the converter receives the clock signal, down-converts the clock signal and generates a pulse sequence clk _ d1 and a pulse sequence clk _ d2 which are staggered with each other by one clock cycle and have the frequency of a preset multiple of the data frequency.
When the controller detects the leading pulse k or the lagging pulse j, a high level signal is generated, and a pulse signal in the pulse sequence clk _ d1 or a pulse signal in the pulse sequence clk _ d2 is output.
Specifically, in fig. 3, the output frequency of the local crystal oscillator is 32 times (32MHz) the data rate, and after conversion, the local crystal oscillator is shifted by one clock cycle to obtain two pulse sequences clk _ d1 and clk _ d2 with a frequency 8 times the data rate. S1 and S2 in the controller are one-shot flip-flops, and when a high level signal is detected, a high level signal of 4 crystal oscillator clock cycles is generated, and one pulse signal in the clk _ d1 sequence or one pulse signal in the clk _ d2 sequence can be turned on or off to pass through.
In one embodiment, the on-board ADS-B signal header detection system further includes a frequency divider and a pulse shaper. The frequency divider is connected with the output end of the controller, and the pulse former is connected with the output end of the frequency divider; the pulse signal output by the controller passes through the frequency divider and the pulse former and then outputs a bit synchronization pulse. The frequency divider divides the clock of the previous stage, and the pulse shaper shapes the divided clock into a pulse form.
In one embodiment, referring to fig. 1 and 4, the satellite-borne ADS-B signal header detection system further includes a digital filter N7, the digital filter N7 being connected between the phase detector and the controller. The digital filter N7 includes:
the random loitering filter receives the leading pulse and the lagging pulse output by the phase discriminator, and respectively filters and counts the leading pulse and the lagging pulse and outputs the filtered leading pulse and the lagging pulse;
a first divider C1, receiving the counting result and the leading pulse output by the random loitering filter, clearing the sporadic leading pulse according to the counting result, and outputting a first clear signal;
the second divider C2 is used for receiving the counting result and the lagging pulse output by the random loitering filter, clearing the sporadic lagging pulse according to the counting result and outputting a first clearing signal;
the input end of the third AND gate D1 receives the leading pulse and the first zero clearing signal, and the two signals are AND-ed to output the leading pulse when the two signals are not zero clearing;
and a fourth AND gate D2 having inputs for receiving the lagging pulse and the second clear signal and for AND-ing the lagging pulse to output the lagging pulse when not clear.
Briefly, the leading and lagging pulses in S3 are first filtered by a random loitering filter, and then the leading or lagging pulses in the random occurrences of nulls are filtered out using two and gates and two dividers. The random loitering filter may consist of an up-down counter and an or-gate.
Specifically, the digital filter N7 digitally filters the leading or lagging pulses generated by the digital phase locked loop N6 to increase their immunity to interference. The specific implementation block diagram is shown in fig. 4, in the diagram, two N counters are included in the random loitering filter, when the count of leading pulses or lagging pulses is full of N, leading pulses or lagging pulses can be output, otherwise, the leading pulses or the lagging pulses are sporadic pulses, and for interference resistance, when the phase detector outputs the sporadic leading pulses or lagging pulses, the sporadic pulses can enable the first divider C1 or the second divider C2 to be cleared, so that the interference resistance performance is good. That is, when the continuous leading or lagging pulses are detected from the beginning, the adjusting pulses input by the filter are directly output through the two and gates D1 and D2, the whole filter performs a through function, and whenever the sporadic randomly occurring leading or lagging pulses are detected, the third and gate D1 and the fourth and gate D2 are in a closed state due to the zero clearing function of the first divider C1 or the second divider C2, because the function of filtering the random pulses is realized.
The header frame detection module N8 is configured to acquire header data according to the position of the bit synchronization pulse, that is, data acquired by the FPGA using a clock, perform frame synchronization with a preset header data format, and if the frame synchronization can be locked, the frame detection is passed, so as to obtain a header frame. The collected data can be stored in RAM and frame synchronized with the header data format in the protocol.
In one embodiment, referring to fig. 1, the satellite-borne ADS-B signal header detection system further includes: a DF check module N9 and a power consistency detection module N10.
The DF checking module N9 is configured to determine a data value of the DF bit in the header frame that is detected by the header frame detecting module N8, and check that the DF bit passes if the data format of the DF bit is equal to the default DF bit.
The default DF location data format is (10001), so a decision is made as to whether the acquired data value for DF in the frame structure passed detection, i.e., equals (10001). The position of the DF is fixed in the protocol, if a 10001 signal is detected, the DF check is passed, otherwise, the check is not passed.
The power consistency detection module N10 is used to perform consistency detection on the power of bit data of 1 in the header frame passing the DF check module N9 check, so that the fluctuation is within a certain threshold range. The power consistency detection is to perform consistency detection on the power of data with bit 1 in a header frame, and the power fluctuation of the data is required to be within a certain threshold range. In this example, it can be set that the fluctuation range of the power of these data is within plus or minus 3 dbm. In fig. 1, the signal output by the power consistency detection module N10 is a signal sampled by the received ADS-B signal, the bit synchronization clock is a clock accompanying data, and the header flag signal is a pulse signal indicating a message position.
Referring to fig. 5, the present invention further provides a method for detecting a header of a satellite-borne ADS-B signal, including the following steps:
s1: carrying out envelope extraction on baseband signals of the received two paths of orthogonal signals to obtain envelope signals;
s2: performing automatic gain control on the envelope signal;
s3: carrying out filtering processing on the envelope signal subjected to the automatic gain control processing;
s4: tracking the signal processed by the filtering module by the local clock and outputting a tracked bit synchronization pulse;
s5: and acquiring data according to the position of the bit synchronization pulse, carrying out frame synchronization with a preset header data format, and if the frame synchronization can be locked, passing the frame detection to obtain a header frame.
S6: judging the acquired data value of the DF bit in the header frame which passes the detection, and if the acquired data value is equal to the data format of the default DF bit, checking to pass;
s7: and carrying out consistency detection on the power of the bit data of 1 in the header frame passing the verification so as to enable the fluctuation to be within a certain threshold range.
For specific contents of the method for detecting the header of the satellite-borne ADS-B signal according to the present invention, reference may be made to contents of embodiments in the system for detecting the header of the satellite-borne ADS-B signal in the foregoing embodiments, and details are not repeated herein.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the scope of the claims, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention.
Claims (9)
1. An on-board ADS-B signal header detection system, comprising:
the envelope extraction module is used for carrying out envelope extraction on the baseband signals of the received two paths of orthogonal signals to obtain envelope signals;
the AGC module is connected with the output end of the envelope extraction module and is used for carrying out automatic gain control on the envelope signal;
the filtering module is connected with the output end of the AGC module and is used for filtering the envelope signal processed by the AGC module;
the digital phase-locked loop is connected with the output end of the filtering module and used for realizing the tracking of the local clock on the signal processed by the filtering module and outputting bit synchronization pulse;
the header frame detection module is used for acquiring header data according to the position of the bit synchronization pulse, carrying out frame synchronization with a preset header data format, and if the frame synchronization can be locked, the frame detection is passed to obtain a header frame;
the DF check module is used for judging the acquired data value of the DF bit in the header frame which is detected to pass by the header frame detection module, and if the acquired data value is equal to the default data format of the DF bit, the DF check module passes;
the power consistency detection module is used for carrying out consistency detection on the power of the bit data which is 1 in the header frame and passes the verification of the DF verification module so as to enable the fluctuation to be within a certain threshold range;
wherein the AGC module includes: a divider, an accumulator and an IIR loop filter;
the divider realizes automatic gain control on signal intensity according to an automatic gain control coefficient fed back by the IIR loop filter and outputs a controlled envelope signal;
the accumulator receives the envelope signal, estimates the signal intensity and outputs the estimated value to the IIR loop filter;
and the IIR loop filter receives the estimated value, carries out noise filtering on the estimated value and outputs an automatic gain control coefficient.
2. The ADS-B signal header detection system of claim 1, wherein the envelope module obtains two orthogonal baseband signals I (k) and Q (k) after ADC sampling, and performs modulo operation on I (k) and Q (k):
an envelope signal s (k) is obtained.
3. The on-board ADS-B signal header detection system of claim 1, wherein the filtering module comprises:
an autocorrelation filter for performing autocorrelation operation on the envelope signal S (k) processed by the AGC module to obtain a signal S1(k) And calculating a formula:
cross-correlation filter for the signal S output from the autocorrelation filter1(k) Performing cross-correlation operation to obtain signal S2(k) And calculating a formula:
S2(k)＝(S1(k-1)coef(1)+S1(k-2)coef(2)+…+S1(k-n) coef (n)), coef (1), coef (1), … coef (n) are preset matching coefficients;
and the narrow-band filter is used for filtering the signal output by the cross-correlation filter, and the pass band of the narrow-band filter is the bandwidth of the signal.
4. The on-board ADS-B signal header detection system of claim 1, wherein the digital phase locked loop comprises: the device comprises a homodromous integrator, a quadrature integrator, a first sample holder, a second sample holder, a phase discriminator and a controller;
the homodromous integrator and the orthogonal integrator respectively integrate the envelope signals subjected to filtering processing and respectively output a signal b and a signal c; the integration time of the homodromous integrator and the quadrature integrator is the code element period T and is controlled by the bit synchronization pulse, so that the integration interval of the homodromous integrator is superposed with the interval of the bit synchronization pulse, and the integration interval of the quadrature integrator just spans between the middle points of two adjacent bit synchronization pulses;
the first sampling holder and the second sampling holder are respectively connected with the output ends of the homodromous integrator and the orthogonal integrator and are respectively used for sampling and holding the signal b and the signal c and prolonging the duration time to a code element period time T to obtain a signal e and a signal f;
the phase discriminator is used for detecting the phases of the signal e and the signal f to determine the phase lead or lag of the bit synchronization pulse, outputting a leading pulse k when the phase of the bit synchronization pulse is leading, and outputting a lagging pulse j when the phase of the bit synchronization pulse is lagging;
the controller is used for controlling the phase of the bit synchronization pulse to move backwards and controlling the phase of the bit synchronization pulse to move forwards according to the phase discrimination result of the phase discriminator.
5. The ADS-B signal header detection system of claim 4, wherein the phase detector comprises:
a transition edge detector connected to the output of the first sample-and-hold device for detecting the transition edge of the signal e and generating a narrow pulse signal g at each transition;
an exclusive-or gate connected to the output ends of the first and second sample-and-hold units, for performing exclusive-or operation on the signal e and the signal f, and outputting a signal h;
the first AND gate receives the narrow pulse signal g and the inverted signal of the signal h, and performs an AND operation on the narrow pulse signal g and the inverted signal of the signal h to output a lagging pulse j;
and the second AND gate receives the narrow pulse signal g and the signal h, and performs an AND operation on the narrow pulse signal g and the signal h to output a leading pulse k.
6. The on-board ADS-B signal header detection system of claim 4, further comprising a crystal oscillator and a transformer; the crystal oscillator outputs a clock signal; the converter receives the clock signal, down-converts the clock signal and generates a pulse sequence clk _ d1 and a pulse sequence clk _ d2 which are staggered with each other by one clock cycle and have the frequency of a preset multiple of the data frequency;
when the controller detects the leading pulse k or the lagging pulse j, a high level signal is generated, and a pulse signal in the pulse sequence clk _ d1 or a pulse signal in the pulse sequence clk _ d2 is output.
7. The on-board ADS-B signal header detection system of claim 6, further comprising a frequency divider and a pulse shaper; the frequency divider is connected with the output end of the controller, and the pulse former is connected with the output end of the frequency divider; the pulse signal output by the controller passes through the frequency divider and the pulse former and then outputs a bit synchronization pulse.
8. The ADS-B signal header detection system on-board of claim 4, further comprising a digital filter connected between the phase detector and the controller, the digital filter comprising:
the random loitering filter receives the leading pulse and the lagging pulse output by the phase discriminator, and respectively filters and counts the leading pulse and the lagging pulse and outputs the filtered leading pulse and the lagging pulse;
the first divider is used for receiving the counting result and the leading pulse output by the random loitering filter, clearing the sporadic leading pulse according to the counting result and outputting a first clear signal;
the second divider is used for receiving the counting result and the lagging pulse output by the random loitering filter, clearing the scattered lagging pulse according to the counting result and outputting a first clearing signal;
the input end of the third AND gate receives the leading pulse and the first zero clearing signal, and the input end of the third AND gate is connected with the leading pulse and the first zero clearing signal in an AND mode so as to output the leading pulse when the leading pulse is not zero clearing;
and the input end of the fourth AND gate receives the lag pulse and the second zero clearing signal, and the lag pulse is output when the lag pulse is not zero clearing by taking the two phases together.
9. An on-board ADS-B signal header detection method based on the on-board ADS-B signal header detection system of any one of claims 1 to 8, comprising the steps of:
s1: carrying out envelope extraction on baseband signals of the received two paths of orthogonal signals to obtain envelope signals;
s2: performing automatic gain control on the envelope signal;
s3: carrying out filtering processing on the envelope signal subjected to the automatic gain control processing;
s4: tracking the signal processed by the filtering module by the local clock and outputting a tracked bit synchronization pulse;
s5: acquiring data according to the position of the bit synchronization pulse, carrying out frame synchronization with a preset header data format, and if the frame synchronization can be locked, passing the frame detection to obtain a header frame;
s6: judging the acquired data value of the DF bit in the header frame which passes the detection, and if the acquired data value is equal to the data format of the default DF bit, checking to pass;
s7: and carrying out consistency detection on the power of the bit data of 1 in the header frame passing the verification so as to enable the fluctuation to be within a certain threshold range.
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