CN107863333A - Line-spacing stack type chip package structure and its method for packing such as height radiating - Google Patents
Line-spacing stack type chip package structure and its method for packing such as height radiating Download PDFInfo
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- CN107863333A CN107863333A CN201711127223.4A CN201711127223A CN107863333A CN 107863333 A CN107863333 A CN 107863333A CN 201711127223 A CN201711127223 A CN 201711127223A CN 107863333 A CN107863333 A CN 107863333A
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- 238000000034 method Methods 0.000 title claims description 40
- 238000012856 packing Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 302
- 239000011521 glass Substances 0.000 claims abstract description 131
- 239000000853 adhesive Substances 0.000 claims abstract description 37
- 230000001070 adhesive effect Effects 0.000 claims abstract description 37
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 12
- 238000003780 insertion Methods 0.000 claims description 8
- 230000037431 insertion Effects 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000005304 joining Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 238000007711 solidification Methods 0.000 description 2
- 230000008023 solidification Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- -1 distribution density Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Wire Bonding (AREA)
Abstract
The present invention provides a kind of encapsulating structure of the line-spacing stack chips such as high radiating, and it is included：First glass substrate, the first IC apparatus, the first anisotropic conductive adhesive paste, the second glass substrate, the second IC apparatus, the second anisotropic conductive adhesive paste and package main body.
Description
Technical field
The present invention is on stack type chip package structure and its method for packing, is engaged especially with respect to one kind using ambetti
Technology and stack type chip package structure and its manufacture method.
Background technology
Factor data amount is huge, the increase for performance requirements, and server need to use multiple central processing units mostly at present
(Central Processing Unit, CPU) carries out calculation process, whether dual processor, four processors or more
Processor, all it is each position that each processor is separately positioned on to mainboard, then carry out circuit design cloth in existing framework
Office.Such a mode at least two great missings, one is there are each processor multiple stitch need to be connected to mainboard, and
Also sequential the problem of, therefore the complexity of wiring is dramatically increased；The second is each processor can take mainboard
Space, it is corresponding also to need constantly to expand the size of mainboard so that the volume of main frame can be very huge when the increase of processor quantity
Greatly, the combination of two above missing, can cause server overall construction design extremely difficult.
Though there are known techniques by multiple CPU IC（Also referred to as integrated circuit, IC), or chip (chip), crystal grain
(die), bare crystalline carries out storehouse post package, but these prior arts still have missing and be different from place of the present invention and state as follows respectively
It is bright.
Chinese invention patent CN101107710 B institutes storehouse for various sizes of integrated circuit（That is IC）, its
Effect also differs, above the area of integrated circuit be more than the area of following integrated circuit, and both are engaged in same substrate, its
Narration will prevent resin from flowing to the central hole of substrate in specification, for allowing light penetration.U.S. patent Nos
US20060016973 A1 are also various sizes of integrated circuit, and both are engaged in same substrate, its substrate center hole
For printing opacity.It is metal inside through hole though the through hole of U.S. patent Nos US8531019 B2 substrate centers is to be used to radiate
Line, and metallic plate and tin ball are connected to reach the purpose of radiating.US6365963 B are also various sizes of integrated circuit,
And same substrate is engaged in, the through hole of its substrate is to be used for connection line.The substrate of TaiWan, China patent of invention 200810063 is not
It is glass substrate, and is to be engaged two substrates, not connects respectively and in package main body, and with attached described in its specification
The mode storehouse integrated circuit of figure, the problem of producing bad connection, be a negative example.
In addition to above-mentioned narration, known techniques（That is prior art）The problem of all not considering wiring, therefore applicant
It is proposed a kind of with can be by waiting line-spacing to solve Circuit Wiring Problem, and stack type chip package structure and envelope with high thermal advantage
Preparation method is filled, to improve the missing of known techniques, and reaches the effect of effectively reducing encapsulation bulk area simultaneously.
The content of the invention
In view of the missing of known techniques, the present invention provides line-spacing stack type chip package structure and its envelopes such as a kind of high radiating
Dress method.
The line-spacing stack type chip package structures such as the high radiating of the present invention, including：First glass substrate, it includes first substrate
The first of surface, second substrate surface and insertion first substrate surface and second substrate surface leads excessive hole, and first, which leads excessive hole, is set
In the center of the first glass substrate, first substrate surface includes first substrate circuit, and first substrate circuit includes a plurality of first
Substrate contact and a plurality of first substrate conductive projections, the first substrate conductive projection are arranged at first glass substrate
Edge, the first substrate contact are arranged at first and led around excessive hole；First integrated circuit（That is IC）Device, it is wrapped
Containing a plurality of（It is i.e. multiple）First device conductive projection, the first device conductive projection are electrically connected at the first substrate and connect
Point；First anisotropic conductive adhesive paste, it is arranged at around the first device conductive projection and the first substrate contact, and is led to
Cross first lead excessive hole lead it is excessive；Second glass substrate, it includes the 3rd substrate table of the 3rd substrate surface, tetrabasal surface and insertion
The second of face and tetrabasal surface leads excessive hole, and second leads the center that excessive hole is arranged at the second glass substrate, the 3rd substrate surface
Comprising second substrate circuit, second substrate circuit includes a plurality of second substrate contacts and a plurality of second substrate conductive projections,
The second substrate conductive projection is arranged at the edge of the second glass substrate, and the second substrate contact is arranged at second and leads excessive hole
Around；Second integrated circuit（That is IC）Device, it includes a plurality of second device conductive projections, the second device
Conductive projection is electrically connected at the second substrate contact；Second anisotropic conductive adhesive paste, it is conductive that it is arranged at the second device
Around projection and the second substrate contact, and by described second lead excessive hole lead it is excessive；And package main body, it includes first
Body surfaces and the second body surfaces, the first body surfaces include groove and main body circuit, the first IC apparatus and first
Glass substrate is arranged in groove, and the first substrate conductive projection is electrically connected at main body circuit, the second IC apparatus
The top of the first glass substrate is arranged at the second glass substrate, the second substrate conductive projection is electrically connected at main body line
Road.
The line-spacing stack type chip package methods such as the high radiating of the present invention, comprising：The first glass substrate is provided, it includes first
Substrate surface and second substrate surface；First substrate circuit, the first substrate circuit bag are formed in the first substrate surface
Containing a plurality of first substrate contacts and a plurality of first substrate conductive projections, the first substrate conductive projection is located at described first
The edge of glass substrate；First is formed in the center of first glass substrate and leads excessive hole, and described first leads described in excessive hole insertion
First substrate surface and the second substrate surface, wherein the first substrate contact is led around excessive hole positioned at described first；
The first IC apparatus is provided, it includes a plurality of first device conductive projections；First anisotropic conductive adhesive paste is provided, set
It is placed in around the first device conductive projection and the first substrate contact；First glass substrate, first are integrated
Circuit arrangement and the heating of the first anisotropic conductive adhesive paste, pressurization, make the first device conductive projection be electrically connected at described first
Substrate contact, first anisotropic conductive adhesive paste by described first lead excessive hole lead it is excessive；The second glass substrate is provided, it includes the
Three substrate surfaces and tetrabasal surface；Second substrate circuit, the second substrate circuit are formed in the 3rd substrate surface
Comprising a plurality of second substrate contacts and a plurality of second substrate conductive projections, the second substrate conductive projection is positioned at described the
The edge of two glass substrates；Second is formed in the center of second glass substrate and leads excessive hole, and described second leads excessive hole insertion institute
The 3rd substrate surface and tetrabasal surface are stated, wherein the second substrate contact is led around excessive hole positioned at described second；Carry
For the second IC apparatus, it includes a plurality of second device conductive projections；Second anisotropic conductive adhesive paste is provided, is located at
Around the second device conductive projection and the second substrate contact；By second glass substrate, the second integrated circuit
Device and the heating of the second anisotropic conductive adhesive paste, pressurization, make the second device conductive projection be electrically connected at the second substrate
Contact, second anisotropic conductive adhesive paste by described second lead excessive hole lead it is excessive；Package main body is provided, it includes the first body table
Face and the second body surfaces, first body surfaces include groove and main body circuit；By first IC apparatus and
First glass substrate is located at the groove, the first substrate conductive projection is electrically connected at the main body circuit；With
And second IC apparatus and second glass substrate are located to the top of first glass substrate, make described the
Two substrate conductive projections are electrically connected at the main body circuit.
Line-spacing stack type chip package structure and the method for packing such as high radiating provided by the present invention, by the way that integrated circuit is filled
Put and be bonded to glass substrate using glass joining technique (chip on glass, COG) individually, and enter line on the glass substrate
Road be laid out, then by it is multiple engaged with glass substrate after IDE storehouse encapsulation, electricity thus can not only be greatly reduced
The complexity of road wires design, the area and volume of encapsulating structure can be also effectively reduced, but will be integrated using glass joining technique
When circuit arrangement is bonded to glass substrate, because anisotropic conductive adhesive paste is possible to be distributed between IC apparatus and glass substrate
It is unequal or produce bubble, cause plate to stick up the missing for waiting out-of-flatness, this missing can not through re-working to repair, because
The center that this applicant is set forth in glass substrate sets and leads excessive hole, therefore reduces the incidence that plate sticks up, and through lead excessive hole lead it is excessive
Anisotropic conductive adhesive paste can also assist IC apparatus to radiate, in conjunction with the heat-conducting effect of glass substrate, can reach high radiating
The effect of rate.
In order that any be familiar with relevant art's understanding technology contents of the invention and implement according to this, and according to this specification
Disclosed content, claim and schema, it is any to be familiar with relevant art and be readily understood upon the mesh of correlation of the invention
And advantage, therefore will in embodiments in detail narration the present invention detailed features and advantage.
Brief description of the drawings
Fig. 1 is the diagrammatic cross-section of the line-spacing stack type chip package structure first embodiments such as the high radiating of the present invention.
Fig. 2 is the schematic diagram of the first glass substrate in the line-spacing stack type chip package structures such as the high radiating of the present invention.
Fig. 3 is the schematic diagram of the second glass substrate in the line-spacing stack type chip package structures such as the high radiating of the present invention.
Fig. 4 is that IC apparatus is engaged in glass substrate in the line-spacing stack type chip package structures such as the high radiating of the present invention
Schematic diagram.
Fig. 5 is the diagrammatic cross-section of the line-spacing stack type chip package structure second embodiments such as the high radiating of the present invention.
Fig. 6-8 is the flow chart of the line-spacing stack type chip package methods such as the high radiating of the present invention.
The line-spacing stack type chip package structures 100 such as height radiating,
First glass substrate 10,
First substrate surface 11,
Second substrate surface 12,
First leads excessive hole 13,
First substrate circuit 14,
First substrate contact 15,
First substrate conductive projection 16,
First IC（That is integrated circuit, integrated circuit）Device 20,
First device conductive projection 21,
Second glass substrate 40,
3rd substrate surface 41,
Tetrabasal surface 42,
Second leads excessive hole 43,
Second substrate circuit 44,
Second substrate contact 45,
Second substrate conductive projection 46,
Second IC apparatus 50,
Second device conductive projection 51,
Package main body 70,
First body surfaces 71,
Second body surfaces 72,
Groove 711,
Main body circuit 712,
Tin ball 713,722,
Radiator 714,721,
The line-spacing stack type chip package method and step S101~S3030 such as height radiating.
Embodiment
Juror and practised to allow in this skilled worker, understand completely the effect of to the present invention, hereby coordinate schema and figure number,
Preferred embodiments of the present invention are described as follows.
If Fig. 1,2, Fig. 1 are that the sections of the line-spacing stack type chip package structure in an embodiment such as high radiating of the invention show
It is intended to, Fig. 2 is the schematic diagram of the first glass substrate in the line-spacing stack type chip package structures such as the high radiating of the present invention, as schemed institute
Show, the present invention provides a kind of line-spacing stack type chip package structures 100 such as high radiating, and it is included：First glass substrate 10, described
One glass substrate includes first substrate surface 11, second substrate surface 12 and the insertion first substrate surface 11 and second substrate
The first of surface 12 leads excessive hole 13, and described first leads the center that excessive hole 13 is arranged at the first glass substrate 10, the first substrate
Surface 11 includes first substrate circuit 14, and the first substrate circuit 14 includes a plurality of first substrate contacts 15 and a plurality of the
One substrate conducting projection 16, these first substrate conductive projections 16 are arranged at the edge of first glass substrate 10, and described
One substrate contact 15 is arranged at described first and led around excessive hole 13.
In the above description, the first glass substrate 10 can be plate conduction tin indium oxide (indium tin oxide,
ITO) the glass of layer, and the first substrate circuit 14 that it is included, can be formed using etching technique, but the present invention is not with this
It is limited, in addition, the first substrate conductive projection 16 can pass through tie lines method, electrolytic plating method, non-electrolytic plating method, transfer projection
The methods of method, is formed, but the present invention is not limited thereto.
Such as Fig. 1, the line-spacing stack type chip package structure 100 such as height radiating also includes：First IC apparatus 20, it is included
A plurality of first device conductive projections 21, the first device conductive projection 21 are electrically connected at the first substrate contact 15；
And the first anisotropic conductive adhesive paste (not shown), it is arranged at the first device conductive projection 21 and the first substrate contact
Around 15, and by described first lead excessive hole 13 lead it is excessive.
In the above description, will be integrated by anisotropic conductive adhesive paste (anisotropic conductive film, ACF)
The conductive projection of circuit arrangement connects and the technology of substrate contact in glass substrate, referred to as glass joining technique (chip on
Glass, COG), ACF and difference, particle size, composition, distribution density, glue material material etc. used in tripe systems dress mode are all regarded
Depending on product is other, the particle density of ACF used in COG is just than rewinding type chip carrier encapsulation (tape carrier
Package, TCP) it is high, because COG is engaged with projection and glass substrate, its contact area is engaged than TCP with pin mode
Area it is small, in order to remain stable electrical, the conductive particle number of unit area must improve.Screen printing can be used in ACF
Or dispensing mode is printed to substrate, it is specifically intended that ACF is not only on contact (weld pad), but in substrate and integrate
On the whole corresponding surface of circuit arrangement, by IC apparatus be placed on substrate and heat, pressurize make its solidify after complete engage.
COG disadvantages are that re-working property is low, and dismounting IC apparatus can destroy glass surface electrode, cause full wafer glass substrate
It can not use.As shown in figure 4, it is engaged for IC apparatus in the line-spacing stack type chip package structures such as the high radiating of the present invention
In the schematic diagram of glass substrate.
Such as the signal that Fig. 1,3, Fig. 3 are the second glass substrate in the line-spacing stack type chip package structures such as high radiating of the invention
The line-spacing stack type chip package structure 100 such as figure, height radiating also includes：Second glass substrate 40, its include the 3rd substrate surface 41,
The second of tetrabasal surface 42 and insertion the 3rd substrate surface 41 and tetrabasal surface 42 leads excessive hole 43, and described second
The center that excessive hole 43 is arranged at second glass substrate 40 is led, the 3rd substrate surface 41 includes second substrate circuit 44,
The second substrate circuit 44 includes a plurality of second substrate contacts 45 and a plurality of second substrate conductive projections 46, and described second
Substrate conducting projection 46 is arranged at the edge of second glass substrate 40, and the second substrate contact 45 is led located at described second
Around excessive hole 43；Second IC apparatus 50, it includes a plurality of second device conductive projections 51, and the second device is led
Electric projection 51 is electrically connected at the second substrate contact 45；And the second anisotropic conductive adhesive paste (not shown), it is located at described
Around second device conductive projection 51 and the second substrate contact 45, and by described second lead excessive hole 43 lead it is excessive.
Second glass substrate 40, the glass substrate 10 of second substrate circuit 44 and first, the feature thunder of first substrate circuit 14
Together, not in this to go forth, and in the preferred embodiment, the first glass substrate 10 further includes anti-interference metallic circuit coating
(not shown), it is formed at second substrate surface 12, and the second glass substrate 40 also further plates comprising anti-interference metallic circuit
Layer (not shown), it is formed at tetrabasal surface 42, can thereby avoid interfering with each other between IC apparatus.And the second collection
The second glass substrate 40 similarly is engaged in using COG into circuit arrangement 50, is not also repeated here herein, as it was previously stated, ACF is
On the whole corresponding surface of substrate and IC apparatus, by IC apparatus be placed on substrate and heat, pressurizeing consolidates it
Engagement is completed after change, but ACF is possible to be distributed between IC apparatus and glass substrate unequal or produces bubble, makes
The missing of out-of-flatness is stuck up etc. into plate, this missing can not be passed through and re-worked to repair, therefore the present invention is through in glass base
Plate center set leads excessive hole, when heating, pressurization make ACF solidification engagement when, unnecessary ACF can by lead excessive hole lead it is excessive, thus
Reduce the incidence stuck up of plate, and can also assist IC apparatus to radiate through leading excessive hole and leading excessive ACF, in conjunction with glass substrate
Heat-conducting effect, the effect of can reach high rate of heat dissipation.
Such as Fig. 1, the line-spacing stack type chip package structure 100 such as height radiating also includes：Package main body 70, it includes the first main body
The body surfaces 72 of surface 71 and second, first body surfaces 71 include groove 711 and main body circuit 712, first collection
Into circuit arrangement 20 and first glass substrate 10 in the groove 711, the first substrate conductive projection 16 is electrical
The main body circuit 712 is connected to, second IC apparatus 50 and second glass substrate 40 are arranged at described
The top of one glass substrate 10, the second substrate conductive projection 51 are electrically connected at the main body circuit 712.
In the above description, the first IC apparatus 20 and the first glass substrate 10 of sum will have been connect, and connect and
The second IC apparatus 50 and the second glass substrate 40, be respectively engaged in package main body 70 with the mode of storehouse, herein
Juncture can be used scolding tin melting engagement, anisotropic conductive adhesive paste engagement or light-hardening resin engagement etc. juncture, but this
Invention is not limited thereto.By way of storehouse IC apparatus, the area and volume of encapsulating structure can be effectively reduced, again
Because IC apparatus is bonded to glass substrate using glass joining technique (chip on glass, COG) individually, and in glass
Substrate enterprising row line layout, thus the line-spacing of each IC apparatus to main body circuit can be designed as easily it is equal,
Therefore can not only solve the problems, such as sequential, moreover it is possible to the complexity of wiring design is greatly reduced.It is noted that in the present invention
In, the first IC apparatus 20 and the second IC apparatus 50 are the IC apparatus with identical function, such as
CPU/MCU (microcontroller)/ASIC (Application-specific integrated circuit) etc. is integrated
Circuit arrangement, and both sizes are identical, and the size of the first glass substrate 10 and the second glass substrate 40 differs, positioned at upper
The size of second glass substrate 40 of side is more than the size of the first glass substrate 10.
It is preferred that groove 711 can be stepped, all settable one of every single order has connect and the integrated circuit in glass substrate
Device, therefore can the multiple IC apparatus of storehouse.
It is preferred that the first body surfaces 71 also include a plurality of tin balls 713, the tin ball is electrically connected at main body circuit
712, the second body surfaces 72 include a plurality of radiators 721.
It is preferred that the line-spacing stack type chip package structure 100 such as high radiating also includes fin (not shown), first is arranged at
Between the IC apparatus 50 of glass substrate 10 and second, and package main body 70 is connected to, to assist to radiate.
It is preferred that the line-spacing stack type chip package structure 100 such as high radiating is also comprising underfill (underfill) (figure
Do not show), to fill to the first glass substrate 10, the first IC apparatus 20, the second glass substrate 40, the second integrated circuit
Gap between device 50 and package main body 70, to strengthen package strength.
Such as Fig. 5, Fig. 5 is the section signal of the line-spacing stack type chip package structure second embodiments such as the high radiating of the present invention
Figure, in a second embodiment, the second body surfaces 72 also include a plurality of tin balls 722, and these tin balls are electrically connected at main body line
Road 712, the first body surfaces 71 also include a plurality of radiators 714, and these radiators are connected to the second glass substrate 40.The
Other features of two embodiments all duplicate with first embodiment, and not in this to go forth.
Such as Fig. 6-8, Fig. 6-8 is the flow chart of the method for packing of line-spacing stack chip such as the high radiating of the present invention, such as Fig. 6 institutes
Show, the present invention provides a kind of line-spacing stack type chip package methods such as high radiating, and it is included：The first glass substrate is provided, it is included
First substrate surface and second substrate surface (step S101)；First substrate circuit is formed in the first substrate surface, it is described
First substrate circuit includes a plurality of first substrate contacts and a plurality of first substrate conductive projections, these first substrate conductive studs
Block is located at the edge (step S102) of first glass substrate；Led in the center formation first of first glass substrate excessive
Hole, it penetrates described first substrate surface and second substrate surface, wherein the first substrate contact led positioned at described first it is excessive
Around hole (step S103)；The first IC apparatus is provided, it includes a plurality of first device conductive projection (steps
S104)；The first anisotropic conductive adhesive paste is provided, the week by it located at the first device conductive projection and the first substrate contact
Enclose (step S105)；By the heating of first glass substrate, the first IC apparatus and the first anisotropic conductive adhesive paste, pressurize,
These first device conductive projections are made to be electrically connected at first substrate contact, first anisotropic conductive adhesive paste is by described first
Lead excessive hole and lead and overflow and solidify (step S106).
Such as Fig. 7, the method for packing of the line-spacing stack chip such as high radiating of the invention also includes：Second glass substrate is provided,
It includes the 3rd substrate surface and tetrabasal surface (step S201)；Second substrate line is formed in the 3rd substrate surface
Road, the second substrate circuit include a plurality of second substrate contacts and a plurality of second substrate conductive projections, second base
Plate conductive projection is located at the edge (step S202) of second glass substrate；The is formed in the center of second glass substrate
Two lead excessive hole, and it penetrates the 3rd substrate surface and the tetrabasal surface, wherein the second substrate contact is located at institute
Second is stated to lead around excessive hole (step S203)；The second IC apparatus is provided, it includes a plurality of second device conductive studs
Block (step S204)；Second anisotropic conductive adhesive paste is provided, it is located at the second device conductive projection and the second substrate
Around contact (step S205)；Second glass substrate, the second IC apparatus and the second anisotropic conductive adhesive paste are added
Heat, pressurization, make the second device conductive projection be electrically connected at the second substrate contact, second anisotropic conductive adhesive paste
Excessive hole, which is led, by described second leads excessive and solidification (step S206).
In the above description, the step of step S101 ~ S103, S201 ~ S103 is prepare glass substrate, wherein glass substrate
Can be the glass of tin indium oxide (indium tin oxide, the ITO) layer for plating conduction, and the base plate line that it is included, can
Formed using etching technique, but the present invention is not limited thereto, substrate conducting projection can by tie lines method, electrolytic plating method,
The methods of non-electrolytic plating method, transfer projection method, is formed, but the present invention is not limited thereto.S104, S204 are integrated electric to prepare
Road device step, wherein IC apparatus device conductive projection, can be by tie lines method, electrolytic plating method, electroless
The methods of galvanoplastic, transfer projection method, is formed, but the present invention is not limited thereto.S105, S205 are preparation anisotropic conductive adhesive paste
The step of；And S106, S206 are the step of engaging glass substrate and IC apparatus through anisotropic conductive adhesive paste.The present invention
It is that each IC apparatus is passed through into anisotropic conductive adhesive paste, connects respectively and in glass substrate, and enter row line in glass substrate
Layout, and excessive hole is led by being provided located at glass substrate center, avoid in engaging process, anisotropic conductive adhesive paste is possible to be distributed
It is unequal or produce bubble, the missing for causing plate to stick up, and can also assist to integrate through leading excessive hole and leading excessive anisotropic conductive adhesive paste
Circuit arrangement radiates, in conjunction with the heat-conducting effect of glass substrate, the effect of can reach high rate of heat dissipation.
Such as Fig. 8, the method for packing of the line-spacing stack chip such as high radiating of the invention also includes：Package main body is provided, it is wrapped
Containing the first body surfaces and the second body surfaces, first body surfaces include groove and main body circuit (step S301)；Will
First IC apparatus and first glass substrate are located at the groove, make the first substrate conductive projection electrical
It is connected to the main body circuit (step S302)；And second IC apparatus and second glass substrate are located at institute
The top of the first glass substrate is stated, these second substrate conductive projections is electrically connected at the main body circuit (step S303).
In the above description, it is IC apparatus by having connect and to glass substrate, in a manner of storehouse, respectively connects
Scolding tin melting engagement, anisotropic conductive adhesive paste engagement or light-hardening resin can be used to connect with package main body, juncture herein
The junctures such as conjunction, but the present invention is not limited thereto.By the mode of storehouse IC apparatus, encapsulation knot can be effectively reduced
The area and volume of structure.
It is preferred that after first IC apparatus and first glass substrate are located at into the groove, can
Fin is arranged between the first glass substrate and the second IC apparatus, and is connected to package main body, to assist to radiate.
It is preferred that making the second substrate conductive projection be electrically connected at after the main body circuit, underfill can be used
Agent (underfill), to fill to the first glass substrate, the first IC apparatus, the second glass substrate, the second integrated electricity
The gap of road device and package main body, to strengthen package strength.
Only the various embodiments described above are to illustrate the features of the present invention, and its purpose will appreciate that this hair making to be familiar with the operator
Bright content is simultaneously implemented according to this, and non-limiting the scope of the claims of the invention, thus it is all other without departing from disclosed spirit
And the equivalent modification completed or modification, it should be included in claim as described below.
Claims (10)
1. a kind of line-spacing stack type chip package structures such as high radiating, it is characterized in that, comprising：
First glass substrate, it includes first substrate surface, second substrate surface and the insertion first substrate surface and described
The first of second substrate surface leads excessive hole, and described first leads the center that excessive hole is located at first glass substrate, first base
Plate surface includes first substrate circuit, and the first substrate circuit includes a plurality of first substrate contacts and a plurality of first substrates
Conductive projection, these described first substrate conductive projections are located at the edge of first glass substrate, these first substrate contacts
Led located at described first around excessive hole；
First integrated circuit devices, it includes a plurality of first device conductive projections, is that these first device conductive projections are electrical
It is connected to these first substrate contacts；
First anisotropic conductive adhesive paste, it leads to around the first device conductive projection and the first substrate contact
Cross described first lead excessive hole lead it is excessive；
Second glass substrate, it includes the 3rd substrate surface, tetrabasal surface and insertion the 3rd substrate surface and described
The second of tetrabasal surface leads excessive hole, and described second leads the center that excessive hole is located at second glass substrate, the 3rd base
Plate surface includes second substrate circuit, and the second substrate circuit includes a plurality of second substrate contacts and a plurality of second substrates
Conductive projection, these described second substrate conductive projections are located at the edge of second glass substrate, the second substrate contact
Led located at described second around excessive hole；
Second integrated circuit devices, it includes a plurality of second device conductive projections, and the second device conductive projection electrically connects
It is connected to the second substrate contact；
Second anisotropic conductive adhesive paste, it leads to around the second device conductive projection and the second substrate contact
Cross described second lead excessive hole lead it is excessive；And
Package main body, it includes the first body surfaces and the second body surfaces, and first body surfaces include groove and main body
Circuit, first integrated circuit devices and first glass substrate are in the groove, the first substrate conductive stud
Block is electrically connected at the main body circuit, and second integrated circuit devices and second glass substrate are located at first glass
The top of glass substrate, the second substrate conductive projection are electrically connected at the main body circuit.
2. the line-spacing stack type chip package structure such as high radiating as claimed in claim 1, it is characterized in that, first glass substrate enters
One step includes anti-interference metallic circuit coating.
3. the line-spacing stack type chip package structures such as high radiating as claimed in claim 1, it is characterized in that, second glass substrate
Further include anti-interference metallic circuit coating.
4. the line-spacing stack type chip package structures such as high radiating as claimed in claim 1, it is characterized in that, first IC
Device and second integrated circuit devices are the integrated circuit devices with identical function, and first integrated circuit devices
It is identical with the size of second integrated circuit devices.
5. the line-spacing stack type chip package structures such as high radiating as claimed in claim 1, it is characterized in that, the groove is ladder
Shape.
6. the line-spacing stack type chip package structures such as high radiating as claimed in claim 1, it is characterized in that, first body surfaces
A plurality of tin balls are also included, the tin ball is electrically connected at the main body circuit.
7. the line-spacing stack type chip package structures such as high radiating as claimed in claim 6, it is characterized in that, second body surfaces
Include a plurality of radiators.
8. the line-spacing stack type chip package structures such as high radiating as claimed in claim 1, it is characterized in that, second body surfaces
A plurality of tin balls are also included, the tin ball is electrically connected at the main body circuit.
9. the line-spacing stack type chip package structures such as high radiating as claimed in claim 8, it is characterized in that, first body surfaces
A plurality of radiators are also included, the radiator is connected to second glass substrate.
10. a kind of method for packing of the line-spacing stack chips such as high radiating, it is characterized in that, including：
The first glass substrate is provided, first glass substrate includes first substrate surface and second substrate surface；
First substrate circuit is formed in the first substrate surface, the first substrate circuit includes a plurality of first substrate contacts
With a plurality of first substrate conductive projections, the first substrate conductive projection is located at the edge of first glass substrate；
One first is formed in the center of first glass substrate and leads excessive hole, and described first, which leads excessive hole, penetrates the first substrate table
Face and the second substrate surface, wherein the first substrate contact is led around excessive hole positioned at described first；
The first integrated circuit devices are provided, first integrated circuit devices include a plurality of first device conductive projections；
The first anisotropic conductive adhesive paste is provided, by first anisotropic conductive adhesive paste located at the first device conductive projection and described
Around a little first substrate contacts；
By the heating of first glass substrate, the first IC apparatus and the first anisotropic conductive adhesive paste, pressurization, make described first
Device conductive projection is electrically connected at the first substrate contact, and first anisotropic conductive adhesive paste leads excessive hole by described first
Lead and overflow and solidify；
The second glass substrate is provided, second glass substrate includes the 3rd substrate surface and tetrabasal surface；
Second substrate circuit is formed in the 3rd substrate surface, the second substrate circuit includes a plurality of second substrate contacts
With a plurality of second substrate conductive projections, the second substrate conductive projection is located at the edge of second glass substrate；
One second is formed in the center of second glass substrate and leads excessive hole, and described second, which leads excessive hole, penetrates the 3rd substrate table
Face and the tetrabasal surface, wherein the second substrate contact is led around excessive hole positioned at described second；
The second integrated circuit devices are provided, it includes a plurality of second device conductive projections；
The second anisotropic conductive adhesive paste is provided, the week by it located at the second device conductive projection and the second substrate contact
Enclose；
By the heating of second glass substrate, the second integrated circuit devices and the second anisotropic conductive adhesive paste, pressurization, make described second
Device conductive projection is electrically connected at the second substrate contact, second anisotropic conductive adhesive paste by second lead excessive hole lead it is excessive
And solidify；
Package main body is provided, it include the first body surfaces and the second body surfaces, first body surfaces comprising groove and
Main body circuit；
First integrated circuit devices and first glass substrate are located at the groove, make the first substrate conductive stud
Block is electrically connected at the main body circuit；And
Second integrated circuit devices and second glass substrate are located at be the first glass substrate top, make described the
Two substrate conductive projections are electrically connected at the main body circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711127223.4A CN107863333A (en) | 2017-11-15 | 2017-11-15 | Line-spacing stack type chip package structure and its method for packing such as height radiating |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711127223.4A CN107863333A (en) | 2017-11-15 | 2017-11-15 | Line-spacing stack type chip package structure and its method for packing such as height radiating |
Publications (1)
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| CN107863333A true CN107863333A (en) | 2018-03-30 |
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ID=61701803
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| Application Number | Title | Priority Date | Filing Date |
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| CN201711127223.4A Pending CN107863333A (en) | 2017-11-15 | 2017-11-15 | Line-spacing stack type chip package structure and its method for packing such as height radiating |
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Cited By (1)
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| CN111199922A (en) * | 2018-11-20 | 2020-05-26 | 奥特斯科技(重庆)有限公司 | Component carrier and method for producing the same |
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Application publication date: 20180330 |