CN107851661A - 功率转换器的物理拓扑结构 - Google Patents

功率转换器的物理拓扑结构 Download PDF

Info

Publication number
CN107851661A
CN107851661A CN201680043194.0A CN201680043194A CN107851661A CN 107851661 A CN107851661 A CN 107851661A CN 201680043194 A CN201680043194 A CN 201680043194A CN 107851661 A CN107851661 A CN 107851661A
Authority
CN
China
Prior art keywords
power electronic
electronic switch
trace
colelctor electrode
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201680043194.0A
Other languages
English (en)
Other versions
CN107851661B (zh
Inventor
J-M.西尔
M.阿马尔
M.艾尔亚科比
P.弗勒里
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dana TM4 Inc
Original Assignee
TM4 Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TM4 Inc filed Critical TM4 Inc
Publication of CN107851661A publication Critical patent/CN107851661A/zh
Application granted granted Critical
Publication of CN107851661B publication Critical patent/CN107851661B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/538—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a push-pull configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/1425—Converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0029—Circuits or arrangements for limiting the slope of switching signals, e.g. slew rate
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/34—Snubber circuits
    • H02M1/342—Active non-dissipative snubbers
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Power Conversion In General (AREA)
  • Inverter Devices (AREA)
  • Electronic Switches (AREA)

Abstract

一种用于接收顶部和底部功率电子开关的物理拓扑结构，包括：顶部集电极迹线，其连接到正电压电源接片，且具有用于顶部功率电子开关的集电极的连接区域；底部发射极迹线，其连接到负电压电源接片，且具有用于底部功率电子开关的发射极的连接区域；以及中间迹线，其连接到负载接片，并具有用于顶部功率电子开关的发射极的连接区域和用于底部功率电子开关的集电极的连接区域。在用于顶部和底部功率电子开关的发射极的电压的迹线上、在用于底部功率电子开关的集电极的电压的迹线上、以及在负电压电源接片上提供采样点。拓扑结构限定了寄生电感。采样电压可以提供给栅极驱动器基准。

Description

功率转换器的物理拓扑结构
技术领域
本公开涉及功率电子领域。更具体地，本公开涉及用于构建功率转换器的物理拓扑结构。
背景技术
换向单元通常用于需要电压源的转换的电子***，包括DC-DC转换器和DC-AC转换器(通常称为逆变器)。由于功率转换器电路(诸如在电动和/或电动混合汽车应用中所使用的功率转换器电路)所允许的有限的空间，并且由于半导体的高成本，因此对这些换向单元的集成的需求增加。
减少功率转换器电路中的半导体所占用的空间的已知方式是提高其效率，以使冷却表面的尺寸减小。
存在于传统功率转换器电路中的功率电子开关的损耗主要由两个来源引起：传导损耗和开关损耗。减少开关损耗的一种方法通常是加速功率电子开关的导通和关断。然而，功率电子开关的快速关断会在其高频回路的杂散电感中产生过电压。因此通常需要减慢功率电子开关的关断以保护其不经受过电压。这可能会严重影响传统功率转换器电路的整体效率。
图1是诸如在传统功率转换器电路中使用的传统换向单元的理想化的电路图。换向单元10将来自电压源12(或电容器)的DC电压Vbus转换成电流源Iout(或电感器)，该电流源Iout通常产生适合于负载14的电压Vout，负载14可以是电阻负载、电动马达等。换向单元10包括续流二极管16和受控功率电子开关18，例如隔离栅极双极晶体管(IGBT)。电容器20(Cin)用于限制电压源12的电压Vbus的变化，电感器32用于限制输出电流Iout的变化。栅极驱动器(图1中未示出，但在后面的附图中示出)控制功率电子开关18的导通和关断。图1示出了换向单元10、负载14和电压源12的配置，其中能量从电压源12流动到负载14，即在图上从左到右。换向单元10也可以以其中能量沿相反方向流动的相反配置使用。
当导通时，功率电子开关18允许电流从其集电极22通过该功率电子开关到其发射极24；此时，功率电子开关18可以近似为闭合电路。当关断时，功率电子开关18不允许电流通过其，并且可以近似为断开电路。
栅极驱动器在功率电子开关18的栅极26和发射极24之间施加可变的控制电压。对于某些类型的功率电子开关，诸如双极型晶体管，栅极驱动器可以充当电流源而不是电压源。通常，当施加在栅极26与发射极24之间的电压为“高”时，功率电子开关18允许电流从集电极22流动到发射极24。当施加在栅极26与发射极24之间的电压为“低”时，功率电子开关18阻断电流通过其。更详细地，栅极驱动器控制表示为Vge的、栅极26和发射极24之间的电压差。当Vge大于功率电子开关18的阈值Vge(th)时，开关18导通，集电极22和发射极24之间的电压Vce接近零。当Vge低于Vge(th)时，功率电子开关18断开，Vce最终达到Vbus。
当功率电子开关18导通时，电流Iout从电压源12(并且瞬时地从电容器20)流动通过负载14并通过集电极22和发射极24。当功率电子开关18关断时，电流Iout从负载14流通并进入续流二极管16。因此可以观察到功率电子开关18和续流二极管16串联操作。以高频导通和关断功率电子开关18允许输出电感Lout32中的电流Iout保持相当恒定。
应该注意的是，在其他功率电子开关类型(例如双极型晶体管)的情况下，术语“栅极”可以用“基极”代替，与栅极由电压控制相对，基极由电流控制。这些区别不改变换向单元10的整体操作原理。
图2是图1的传统换向单元的另一个电路图，示出了寄生(杂散)电感。与图1的理想化模型相反，实际换向单元的组件之间的连接限定了寄生电感。虽然寄生电感分布在换向单元10内的不同位置处，但是图2中呈现的合适模型示出代表整个寄生电感的两(2)个不同的电感，包括功率电子开关18的发射极电感30以及代表围绕由续流二极管16、功率电子开关18和电容器20形成的高频回路36的所有其他寄生电感(除了发射极电感30)的电感34。高频回路36是功率电子开关18切换时电流显著变化的路径。应该注意的是，输出电感Lout32不是高频回路的一部分，因为其电流在换向周期中保持相当恒定。
图3是由两个换向单元形成的IGBT支路的电路图。更具体地，在其中IGBT被用作功率电子开关的图1-2的以上描述中介绍的两个换向单元10被连接在单个回路中，并且形成由电压源12和电容器54供电的IGBT支路50。第一功率电子开关(底部IGBT Q1)与第一续流二极管(顶部续流二极管D2)串联操作，第二功率电子开关(顶部IGBT Q2)与另一续流二极管(底部续流二极管D1)串联操作。顶部IGBT Q2和底部IGBT Q1中的每一个实际上可以包括被组合以提供额外功率的多个并联的IGBT。类似地，顶部和底部续流二极管D1、D2中的每一个可以包括多个并联的二极管。为了简化说明，在图3中没有示出IGBT和二极管的并联。在本公开的上下文中，术语“顶部”和“底部”不是指电路中的电子设备的物理位置；这些术语仅以图3中例示的示意图表示电子设备的位置。例如，在不限制本公开的情况下，当将设备连接为(在电气方面)更接近正电压源、而不是更接近负电压源时，设备被认为位于“顶部”。当设备以比连接到正电压源更低的阻抗连接到负电压源时，设备可以被认为位于“底部”。
每一个IGBT具有其自己的栅极驱动器52。电压源12提供与经由寄生电感Lc连接到IGBT支路50的输入电容54(Cin)并联的电压Vbus。图3中示出了在功率转换器的引线、连接、去耦电容器和电路板迹线中固有地提供的电感。如图3所示，用于从电池(未示出)向三相电动马达(也未示出)供电的三相功率转换器将包括三(3)个IGBT支路50。由于这种功率转换器对于本领域技术人员来说是公知的，所以在此不再详细描述。
当底部IGBT Q1关断时，在过压期间，电流从底部IGBT Q1流动到顶部续流二极管D2。事实上，由IGBT支路50和输入电容54形成的高频环路51中存在的各种寄生电感(Lc、L+Vbus、Lc-top、Le-top、Lc-bot、Le-bot和L-Vbus)抵抗其中的电流变化，如图3中所示的寄生电感的极性所示，在高频回路51中产生增加电压。加到电源电压Vbus的这些电压经常导致电压超过底部IGBTQ1的最大集电极到发射极电压Vce的额定值。顶部IGBT Q2受到同样的问题。
传统解决方案旨在通过减缓栅极-发射极电压的斜率来限制功率电子开关中的过电压。然而，对过电压的过度限制意味着更长的电流切换时间，从而降低了换向单元的性能。
从图3中可以看出，IGBT支路50具有跨高频回路51的一些寄生(杂散)电感而连接的电阻分压器。IGBT支路50使用补偿电路，该补偿电路使用电阻分压器来优化IGBT Q1、Q2上的过电压。谈及图3的IGBT支路50的底部部分，底部IGBT Q1包括寄生集电极电感Lc-bot，寄生发射极电感Le-bot。底部IGBT Q1的栅极26经由电阻器R1连接到其栅极驱动器52。栅极驱动器52的基准56连接到具有电阻分压器电路的补偿电路，所述电阻分压器电路包括两个电阻器R2和R3、并可选地包括二极管D3，该二极管D3可以被增加以允许当在底部IGBT Q1的发射极处的电压高于基准56时，导通不受将电阻器R2短路的影响。如果存在，则二极管D3在导通IGBT Q1时传导，因为IGBT Q1中的电流的方向导致发射极24处的电压高于基准56处的电压。相比之下，二极管D3在关断IGBT Q1时不传导，因为发射极24处的电压下降导致跨二极管D3施加负电压。应该注意的是，虽然电阻器R2和R3被示为跨寄生电感Le-bot和L-Vbus连接，但是它们可以替代地仅跨寄生电感Le-bot连接，如果该寄生电感足够大并且连接可用的话。
在图3的电路中，电阻器R2和R3的值根据跨底部IGBT Q1所允许的可接受过电压电平被选择。R2与R3的比率增加，以降低过电压。这两个电阻器R2和R3的并联值被设定，与一个栅极驱动器电阻器R1串联。根据适当的换向行为以传统方式调整栅极驱动器电阻器R1的值。
补偿电路的电阻器值被设定为降低由IGBT Q1、Q2上的发射极电感的存在所引起的过电压。为了达到最大的IGBT额定值，需要定制过电压，同时出于效率的原因保持di/dt的速度。跨发射极寄生电感的电压因此被分成两路，只有跨逻辑电阻器的电压施加在栅极驱动电路中，以限制栅极压降。
对于底部IGBT Q1，这种技术非常有效，因为发射极电感Le-bot足够大以提供良好的过压采样。相比之下，对于顶部IGBT Q2，发射极电感Le-top通常具有太小的值以在不增加栅极电阻器R4的情况下适当地钳位跨过其的电压，从而保护顶部IGBT Q2。实践中，顶部IGBTQ2的发射极电感Le-top通常太低，以至于不能用来将跨顶部IGBT Q2的过电压降低到安全水平。
图4是IGBT模块的典型拓扑结构的示意图。图5是具有图4的拓扑结构的实际IGBT模块的俯视平面图，该IGBT模块包括电路卡和壳体。同时参照图4和5，传统IGBT模块100包括限定图3的顶部IGBT Q2和其相关联的二极管104的第一组并联IGBT 102，限定底部IGBTQ1和其相关联的二极管108的第二组并联IGBT 106，+Vbus接片110，-Vbus接片112和负载接片114。IGBT模块100的元件安装在直接结合铜(DBC)基板101上。如图4和图5所示，由于IGBT模块封装的限制，上部和下部的IGBT和二极管通常彼此极为贴近地封装。
在图4和图5的例子中，并联放置四(4)个IGBT 102以形成顶部IGBTQ2，而并联放置另外四(4)个IGBTS 106以形成图3的底部IGBT Q1。类似地，顶部续流二极管D2和底部续流二极管D1每一个被实现为具有四(4)个并联二极管104、108的组。在图4和5中，IGBT和二极管连接到DBC基板101的迹线。接片110、112和114安装在DBC基板101上，其本身安装在壳体103中。在图4和5中，各种IGBT的集电极22是不可见的，因为它们直接安装在包括c-top迹线116和c-bot迹线122在内的DBC迹线上。发射极24经由引线120连接到e-top迹线117和e-bot迹线118，而栅极26经由引线121连接到g-top和g-bot迹线。类似地，各种二极管的阴极不可见，直接安装在c-top 116和c-bot 122迹线上。各种二极管的阳极经由引线120连接到e-top 117和e-bot 118迹线。
在IGBT模块100中，经由DBC迹线、引引线接合(wire bond)120、121和外部连接进行的互连产生了在图3的前述描述中介绍的寄生电感。
形成了底部IGBT Q1(IGBT106)的发射极26与-Vbus接片112的外部连接之间的连接的e-bot轨迹118包含在这些元件之间产生相当大的寄生电感的Z字形图案。因此，使用图3的补偿电路，跨底部IGBT Q1的发射极电感Le-bot的电压电平可以注入底部IGBT Q1的栅极驱动器26中，以在其发射极24处产生负电压，充分地减缓栅极电压的负斜率。
相比之下，将顶部IGBT Q2(IGBT 102)的发射极互连到底部IGBT Q1(IGBT 106)的c-bot迹线122的引线接合120非常短。因此，顶部IGBT Q2的发射极与底部IGBT Q1的集电极之间的电感非常小，大约为几纳亨(nH)。因此，使用图3的补偿电路可以注入顶部IGBT Q2的栅极驱动器26中、以在顶部IGBT Q2的发射极24处产生负电压从而减缓栅极电压的负斜率的跨顶部IGBT Q2的发射极电感Le-top的电压电平可能太小，以至于不足以限制顶部IGBT Q2的过电压。
上部发射极电感Le-top的相对较小的值可能影响上文所述的解决方案在不对顶部IGBT Q2进行额外修改的情况下应用的有效性。
因此，存在对这样的拓扑结构的需求，其提供对功率电子开关中的寄生电感的更好的限定。
发明内容
根据本公开，提供了一种用于接收顶部和底部功率电子开关的物理拓扑结构，每个功率电子开关包括集电极、栅极和发射极。该拓扑结构包括顶部集电极迹线、底部发射极迹线和中间迹线。顶部集电极迹线连接到正电压电源接片。它包括用于顶部功率电子开关的集电极的连接区域。底部发射极迹线连接到负电压电源接片。它包括用于底部功率电子开关的发射极的连接区域。中间迹线连接到一个负载接片。它包括用于顶部功率电子开关的发射极的连接区域和用于底部功率电子开关的集电极的连接区域。电压采样点设置在迹线上。它们包括位于用于顶部功率电子开关的发射极的连接区域内的中间迹线上的顶部功率电子开关发射极电压采样点，位于中间迹线到负载接片的连接区域内的底部功率电子开关集电极电压采样点，位于用于底部功率电子开关的发射极的连接区域内的底部发射极迹线上的底部功率电子开关发射极电压采样点，以及位于底部发射极迹线到负电压电源接片的连接区域内的负电压电源接片采样点。
本公开还介绍了一种功率转换器，包括上述的拓扑结构以及顶部和底部功率电子开关。该功率转换器还包括：顶部栅极驱动器，该顶部栅极驱动器具有电连接到顶部功率电子开关发射极电压采样点和底部功率电子开关发射极电压采样点的基准；以及底部栅极驱动器，该底部栅极驱动器具有电连接到底部功率电子开关发射极电压采样点和负电压电源接片采样点的基准。
上述和其它特征将通过阅读以下通过参考附图仅仅以示例的方式给出的示例性实施例的非限制性描述而变得更加明显。
附图说明
通过参考附图，仅仅以示例的方式来描述本公开的实施例，在附图中：
图1是诸如在传统功率转换器电路中使用的传统换向单元的理想化的电路图；
图2是图1的传统换向单元的另一个电路图，示出了寄生(杂散)电感；
图3是由两个换向单元形成的IGBT支路的电路图；
图4是IGBT模块的典型拓扑结构的示意图；
图5是具有图4的拓扑结构的实际IGBT模块的俯视平面图，该IGBT模块包括电路卡和壳体；
图6是根据实施例的IGBT模块的俯视平面图，该IGBT模块包括电路卡和壳体；
图7是图6的IGBT模块的透视图；
图8是图6的IGBT模块的透视图，示出了电路卡和连接器，没有壳体；和
图9是适于与图6的IGBT模块一起使用的IGBT支路的电路图。
在各个附图中，相似的附图标记表示相似的特征。
具体实施方式
本公开的各个方面总体上解决了在切换时存在于功率转换器中的过电压的一个或多个问题。
在国际专利公开号WO2013/082705A1，WO2014/043795和WO2014/161080A1，WO2015/070344A1，WO2015/061901A1，WO2015/070347A1和WO2015/139132A1中描述了可操作以限制(特别是在IGBT的关断时)换向单元中的过电压的电路，这些专利全部以Jean-Marc Cyr等人为作者，且其公开内容通过引用并入本文。
本技术提供了对功率模块的功率电子开关关断时的过电压和开关损耗的控制。本文呈现的电路和方法总体上与其他解决方案兼容以限制功率电子开关关断时的过电压。
在功率模块中，功率电子开关关断时的di/dt产生跨功率模块的高频回路的杂散电感的电压。除了向功率模块提供功率的总线电压之外，该电压跨功率电子开关被施加。已经提出了基于将跨功率电子开关存在的过电压的样本注入功率电子开关的栅极驱动器的解决方案。在一对功率电子开关串联连接的情况下，该解决方案有效地控制“底部”功率电子开关上的过电压。然而，“顶部”功率电子开关的发射极与“底部”功率电子开关的集电极之间存在的寄生电感可能不足以提供顶部功率电子开关中存在的过电压的足够样本。改进包括为安装功率电子开关定义新的物理拓扑结构，该拓扑结构提供寄生电感电压的改变的定义和跨过其的电压的采样点。
要注意的是，在这里和所附权利要求中使用的表述“寄生电感”是指由实际换向单元的各个组件之间的连接产生的电感。如从本公开将理解的，跨一些寄生电感而产生的电压被采样并用于改善换向单元的操作。尽管如此，为了清楚的目的，这些电感在本文中被称为寄生电感。
本文公开的技术将主要关于使用隔离栅极双极晶体管(IGBT)来描述。在下面的描述中提及IGBT是为了说明的目的，并不意味着限制本公开。相同的技术同样可以应用于使用金属氧化物半导体场效应晶体管(MOSFET)、双极晶体管和类似的受控功率电子开关构建的功率模块。
这些技术提供用于连接到IGBT模块的栅极驱动器的电压样本。跨顶部和底部发射极电感的电压被注入相应的栅极驱动器中，以在IGBT的发射极处产生负电压，从而减缓Vge的负斜率。其结果是对栅极电压的直接作用，而没有di/dt限制中的任何延迟。
本公开介绍了定义功率电子开关中(例如IGBT模块中)的寄生电感的改进的物理拓扑结构，。图6是根据实施例的IGBT模块的俯视平面图，该IGBT模块包括电路卡和壳体。图7是图6的IGBT模块的透视图。图8是图6的IGBT模块的透视图，示出了电路卡和连接器，没有壳体。
同时参考图6-8，物理拓扑结构200以卡的形式实现，例如可以安装在壳外202中的直接结合铜(DBC)基板。拓扑结构200适于接收可选地包括多个并联的顶部IGBT 204的顶部功率电子开关以及可选地包括多个并联的底部IGBT 206的底部功率电子开关。如上所述，每个IGBT包括集电极、栅极和发射极。拓扑结构200包括连接到正电压电源接片210的顶部集电极迹线208。顶部集电极线路208为顶部IGBT204的集电极提供连接区域。拓扑结构200还包括连接到负电压电源接片214的底部发射极迹线212。底部发射极迹线212为底部IGBT206的发射极提供连接区域。在拓扑结构200中还包括连接到负载接片218的中间迹线216，在多相实施例的情况下，负载接片218可以是相接片。中间迹线216具有用于顶部IGBT 204的发射极的连接区域和用于底部IGBT 206的集电极的连接区域。顶部IGBT 204的集电极与顶部集电极迹线208直接接触，而底部IGBT 206的集电极与中间迹线216直接接触。引线220将顶部IBGT 204的发射极连接到中间迹线216，并且引线221将底部IGBT 206的发射极连接到底部发射极迹线212。顶部续流二极管222与顶部集电极迹线208上的顶部IGBT 204并联安装，底部续流二极管224与中间迹线216上的底部IGBT 206并联安装。迹线由导电材料制成，使用例如直接结合铜(DBC)。
拓扑结构200包括四(4)个电压采样点。这些包括位于用于顶部IGBT 204的发射极的连接区域内的中间迹线216上的电压采样点226，位于中间迹线216到负载接片218的连接区域内的底部IGBT集电极电压采样点228，位于用于IGBT 206的发射极的连接区域内的底部发射极迹线212上的底部IGBT发射极电压采样点230，以及位于底部发射极迹线212到负电压电源接片214的连接区域内的负电压电源接片采样点232。
采样点226、228、230和232分别连接到引脚234、236、238和240，引脚234、236、238和240从支撑拓扑结构200的卡的平面延伸，以提供到位于单独的电路卡(未示出)上的栅极驱动器(在后面的图上)的连接。可以注意到，引脚234和238分别例如通过焊接直接连接到采样点226和230。另一方面，引脚236和240分别焊接在中间迹线216和底部发射极迹线212的边缘上，并且经由中间迹线216和底部发射极迹线212的部分连接到采样点228和232。设置凹槽242和244以隔离在底部IGBT 206和接片218及214之间流动的强电流，从而引脚236和242上的电压分别有效地反映接片218和214处的电压。
在拓扑结构200内，顶部集电极迹线208形成大体上在正电压电源接片210的连接区域与各个顶部IGBT 204安装在顶部集电极迹线上的点之间限定的顶部集电极电感(Lc-top)。底部发射极迹线216大体上在底部IGBT 206的发射极的连接区域(基本上位于底部IGBT发射极电压采样点230处)与用于负极电压电源接片214的连接区域之间形成底部发射极电感(Le-bot)。中间迹线216大体上在用于顶部IGBT 204的发射极的连接区域(基本上在顶部IGBT发射极电压采样点226处)和用于负载接片218的连接区域之间形成顶部发射极电感(Le-top)。中间迹线216还大体上在用于负载接片218的连接区域与各个底部IGBT 206安装在中间迹线216上的点之间形成底部集电极电感(Lc-bot)。没有限制地，顶部发射极电感(Le-top)和底部发射极电感(Le-bot)均可能大于顶部集电极电感(Lc-top)。
所公开的拓扑结构与早期的布局相比，提供了集电极电感值的减小以及顶部发射极电感值的增加。在一些实施例中，使用所公开的拓扑结构构建的IGBT支路的高频回路中的整体电感可以保持与在较早的布局(例如图4和5的布局)中所提供的整体电感相似，从而导致切换损失和开关速度不受显著影响。然而，由于顶部发射极电感增加，所以配置向顶部功率电子开关的栅极驱动器施加电压(跨其采样)变得更容易。
如图6、7和8所示，顶部IGBT 204和底部IGBT 206的发射极分别经由引线220在相当宽的连接区域上连接到中间迹线216和底部发射极迹线212。为了基本上均衡每一个并联的IGBT 204和206中的电流，中间迹线216包括从顶部IGBT发射极电压采样点226沿朝向负载接片218的方向引导的凹槽246，而底部发射器迹线212包括从底部IGBT发射极电压采样点230沿朝向负电压电源接片214的方向引导的凹槽248。在进一步流向接片218和214之前，来自IGBT 204和206发射极的电流朝向采样点226和230被驱动。
图6、7和8还示出顶部栅极迹线250，其被配置为经由引线223连接到顶部IGBT 204的栅极，且底部栅极迹线252被配置为经由引线225连接到IGBT 206的栅极。从支撑拓扑结构200的卡的平面延伸的引脚254和256提供到相应的顶部和底部栅极驱动器输出的连接(如下图所示)。
拓扑结构200可以用作功率转换器的一部分。图9是被配置为与图6的IGBT模块一起使用的IGBT支路的电路图。示意性地示出了IGBT支路300。其一些元件安装在图6、7和8的物理拓扑结构200上，并且IGBT支路300的一些其他元件安装在单独的电路卡(未示出)上，该电路卡例如可以安装在包围拓扑结构200的壳体202的顶部。IGBT支路300包括顶部IGBT204、顶部续流二极管222、底部IGBT 206和底部续流二极管224，其每一个安装在拓扑结构200上，并且可以包括单个设备或多个并联设备。如上文所述，电感Lc-top、Le-top、Lc-bot和Le-bot由拓扑结构200的迹线208、212和216限定。电感L+Vbus、L-Vbus和Lphase分别由正电压电源接片210、负电压电源接片214和负载接片218(在多相实施例的情况下也称为相接片)限定。
从支撑拓扑结构200的卡的平面延伸的引脚234、236、238和240在图9所示的点处连接在IGBT支路300上。跨顶部发射极电感Le-top的电压存在于引脚234和236之间，跨底部发射极电感Le-bot的电压存在于引脚238和240之间。
顶部栅极驱动器302由正电压电源+Vcc和负电压电源-Vdd供电，并具有基准304。在顶部栅极驱动器302的输入303处供应控制信号，以使得输出305达到基准304以上的+Vcc或基准304以下的-Vdd，形成经由栅极电阻器R4施加到顶部IGBT 204的栅极26的信号。顶部栅极驱动器302的基准304经由包括电阻器和可选的导通二极管的补偿电路跨栅极-发射极与顶部IGBT 204的发射极电感串联连接。基准304直接经由引脚234、或者可选地经由与电阻器RD4串联的导通二极管D4并经由引脚234电连接至顶部IGBT发射极电压采样点226。如果存在导通二极管D4的话，当顶部IGBT 204的发射极电压高于基准304的电压时，导通二极管D4被极化而变为短路。基准304也经由电阻器R8和经由引脚236电连接到底部IGBT集电极电压采样点228。电阻器R7可选地与导通二极管D4和电阻器RD4的串联组合并联地放置。如果导通二极管D4不存在(或者等同地如果电阻器RD4具有无穷大的值)，则补偿电路在顶部IGBT 204的导通和关断期间类似地操作。如果导通二极管D4存在，并且如果电阻器RD4被短路代替，则在导通时没有补偿。在导通二极管D4存在的情况下，为电阻器RD4选择合适的值允许独立于IGBT 204的关断而微调顶部IGBT 204的导通，补偿电路在RD4与并联的R7之间形成电阻分压器，这个并联组合与R8串联。要注意的是，电阻器R7可能具有无穷大的值。如有必要，电阻器R7用于微调电路。
底部栅极驱动器308也由正电压电源+Vcc和负电压电源-Vdd供电并具有基准310。在底部栅极驱动器308的输入309处供应控制信号以使得输出311达到基准310以上的+Vcc或基准310以下的-Vdd，从而形成经由栅极电阻器R1施加到底部IGBT 206的栅极26的信号。底部栅极驱动器308的基准310经由包括电阻器和可选的导通二极管的补偿电路跨底部IGBT206的发射极电感连接。底部栅极驱动器308经由包括电阻器和可选的导通二极管的补偿电路连接到底部IGBT 206。基准310或者直接经由引脚238、或者可选地经由与电阻器RD3串联的导通二极管D3并且经由引脚238电连接至底部IGBT发射极电压采样点230。如果存在导通二极管D3的话，当底部IGBT 206的发射极电压高于基准310的电压时，导通二极管D3被极化而变为短路。基准310还经由电阻器R10和经由引脚240电连接到负电压电源接片采样点232。电阻器R9可选地与和电阻器RD3串联的导通二极管D3并联地放置。如果导通二极管D3不存在(或者等同地如果电阻器RD3具有无穷大的值)，则补偿电路在底部IGBT 206的导通和关断期间类似地操作。如果导通二极管D3存在，并且如果电阻器RD3被短路代替，则在导通时没有补偿。在导通二极管D3存在的情况下，为电阻器RD3选择适当的值允许独立于底部IGBT的206的关断而微调底部IGBT 206的导通，补偿电路在RD3与并联的R9之间形成电阻分压器，这个并联组合与R10串联。要注意的是，电阻器R9可具有无穷大的值。
考虑例如由顶部IGBT 204、其顶部栅极驱动器302、和包括可选的导通二极管D4和电阻器R7与R8的补偿电路形成的换向单元。当顶部IGBT 204已经导通时，顶部栅极驱动器302的输出305处于基准304以上的+Vcc，其基本上被短路并且其在引脚234处存在的发射极电压基本上等于+Vbus电压。这个电压等于基准304和开通二极管D4处的电压。当输入端303向栅极驱动器302提供关断命令而没有补偿电路时，输出305将快速下降到-Vdd，并且顶部IGBT 204将迅速变成断开电路。流过的电流迅速减小会导致跨Le-top的电压过高，具有的极性如图9所示，从而导致过电压。利用补偿电路和本发明的拓扑结构，引脚234处的发射极电压降低到基准304的电压以下，并且导通二极管D4变成断开电路。在引脚234和236之间跨Le-top的电压在电阻器R7和R8之间分配，提供施加在基准304处的过电压的样本。该跨Le-top的过电压样本与-Vdd值串联地相加，有效地减缓了顶部IGBT 204的栅极26和发射极24之间的电压Vge的下降，从而减缓其di/dt，降低了其集电极22和发射极24之间的过电压。
在顶部IGBT 204导通时，因为电流开始流过其，所以跨Le-top的电压具有相反的极性，并且引脚234处的发射极电压增加到基准304的电压以上，再次使导通二极管D4(如果存在的话)短路。当顶部栅极驱动器302的输出305倾向于达到+Vcc时，施加到栅极26的电压的这种升高通过施加在存在于引脚234处的发射极电压的基准304上而减缓。这减缓了栅极26和发射极24之间的电压Vge的升高，并且因此减缓了通过顶部IGBT 204的di/dt。这又降低了底部续流二极管224中的恢复电流。
由底部IGBT 206、其栅极驱动器208、和包括导通二极管D3(如果存在的话)以及电阻器R9和R10的补偿电路形成的换向单元以相同的方式操作。
以上描述的解决方案适用于DC-DC功率转换器、AC-DC功率转换器和DC-AC功率转换器，例如使用全路半导体(a full leg ofsemiconductors)、相反的功率电子开关对和续流二极管的功率模块，以提供到诸如电动车辆的马达的连接负载的交流电流；以及适用于使用如本文公开的三个物理布局和三对功率电子开关构建的三相功率转换器。
本领域的普通技术人员将认识到，功率转换器的物理拓扑结构的描述仅是说明性的，并不意图以任何方式进行限制。受益于本公开内容的本领域的普通技术人员将容易地想到其他实施例。此外，可以定制拓扑结构以针对功率电子开关中现有的需求和发生过电压问题提供有价值的解决方案。
作为非限制性示例，本领域技术人员将理解，采样点226和230在迹线216和212上的位置可以根据特定应用所需的寄生电感的值而改变。
为了清楚起见，并未示出和描述拓扑结构的实施的所有常规特征。当然，将理解，在所述拓扑结构的任何这种实际实施的开发中，为了实现开发者的具体目标(诸如符合应用、***和业务相关的约束条件)，可能需要做出许多实施特定的决定，并且这些具体的目标将随着实施和开发者而变化。此外，将理解，开发工作可能是复杂且耗时的，但对于受益于本公开内容的功率电子领域的普通技术人员来说仍然是工程的常规任务。
应该理解的是，拓扑结构的应用不限于附图中所示和上文所述的构造和部件的细节。所提出的拓扑结构能够具有其他实施例并且能够以各种方式来实践。而且，应该理解，本文使用的措辞和术语是为了描述而非限制的目的。
上文已经通过其说明性实施例描述了拓扑结构。权利要求的范围不应受实施例中所述的实施方式的限制，而是应该考虑与整个说明书一致的最宽泛的解释。

Claims (16)

1.一种用于接收顶部和底部功率电子开关的物理拓扑结构，每个功率电子开关包括集电极、栅极和发射极，所述拓扑结构包括：
顶部集电极迹线，其连接到正电压电源接片，所述顶部集电极迹线具有用于顶部功率电子开关的集电极的连接区域；
底部集电极迹线，其连接到负电压电源接片，所述底部集电极迹线具有用于底部功率电子开关的发射极的连接区域；
中间迹线，其连接到负载接片，所述中间迹线具有用于顶部功率电子开关的发射极的连接区域和用于底部功率电子开关的集电极的连接区域；
顶部功率电子开关发射极电压采样点，位于用于顶部功率电子开关的发射极的连接区域内的中间迹线上；
底部功率电子开关集电极电压采样点，位于中间迹线到负载接片的连接区域内；
底部功率电子开关发射极电压采样点，位于用于底部功率电子开关的发射极的连接区域内的底部发射极迹线上；和
负电压电源接片采样点，位于底部发射极迹线到负电压电源接片的连接区域内。
2.根据权利要求1所述的拓扑结构，其中，
所述顶部集电极迹线形成顶部集电极电感；
所述底部发射极迹线形成底部发射极电感；
所述中间迹线在用于顶部功率电子开关的发射极和底部功率电子开关的集电极的连接区域之间形成顶部发射极电感；和
所述中间迹线在负载接片与用于底部功率电子开关的集电极的连接区域之间形成底部集电极电感。
3.根据权利要求2所述的拓扑结构，其中，
所述顶部发射极电感大于所述顶部集电极电感并大于所述底部集电极电感；和
所述底部发射极电感大于所述顶部集电极电感并大于所述底部集电极电感。
4.根据权利要求1至3中任一项所述的拓扑结构，其中，
用于所述顶部功率电子开关的集电极的连接区域和用于所述底部功率电子开关的集电极的连接区域被配置为与功率电子开关的集电极直接接触；和
用于所述顶部功率电子开关的发射极的连接区域和用于所述底部功率电子开关的发射极的连接区域被配置为经由引线连接到功率电子开关的发射极。
5.根据权利要求1至4中任一项所述的拓扑结构，其中，
所述顶部集电极迹线被配置为与所述顶部功率电子开关并联地安装二极管；和
所述中间迹线被配置为与所述底部功率电子开关并联地安装二极管。
6.根据权利要求1至5中任一项所述的拓扑结构，其中，
所述顶部集电极迹线被配置安装多个并联的顶部功率电子开关；和
所述中间迹线被配置安装多个并联的底部功率电子开关。
7.根据权利要求6所述的拓扑结构，其中，
所述中间迹线包括从所述顶部功率电子开关发射极电压采样点沿着朝向所述负载接片的方向引导的凹槽，以基本上均衡所述并联的顶部功率电子开关中的每一个中的电流；和
所述底部发射极迹线包括从所述底部功率电子开关发射极电压采样点沿着朝向所述负电压电源接片的方向引导的凹槽，以基本上均衡所述并联的底部功率电子开关中的每一个中的电流。
8.根据权利要求1至7中任一项所述的拓扑结构，其中，所述顶部集电极迹线、所述底部发射极迹线和所述中间迹线位于直接结合铜(DBC)基板上。
9.根据权利要求8所述的拓扑结构，其中，所述顶部功率电子开关发射极电压采样点、所述底部功率电子开关集电极电压采样点、所述底部功率电子开关发射极电压采样点和所述负电压电源接片采样点中的每一个电连接到相应的栅极驱动器连接，所述栅极驱动器连接从DBC基板的平面延伸并被配置为连接到单独的电路卡。
10.根据权利要求1至8中任一项所述的拓扑结构，包括：
顶部栅极迹线，其被配置为经由一个或多个引线连接到顶部功率电子开关的栅极；和
底部栅极迹线，其被配置为经由一个或多个引线连接到底部功率电子开关的栅极。
11.根据权利要求10所述的拓扑结构，包括一对栅极驱动器连接，其分别从顶部和底部栅极迹线延伸，并被配置为连接到相应的顶部和底部栅极驱动器输出端。
12.根据权利要求1至11中任一项所述的拓扑结构，其中，负载接片是相接片。
13.根据权利要求1至12中任一项所述的拓扑结构，其中，顶部和底部功率电子开关包括隔离栅极双极晶体管(IGBT)。
14.一种功率转换器，包括：
根据权利要求1至13中任一项所述的拓扑结构以及顶部和底部功率电子开关；
顶部栅极驱动器，其具有电连接到顶部功率电子开关发射极电压采样点和底部功率电子开关集电极电压采样点的基准；和
底部栅极驱动器，其具有电连接到底部功率电子开关发射极电压采样点和负电压电源接片采样点的基准。
15.根据权利要求14所述的功率转换器，其中，
顶部栅极驱动器的基准经由与第一电阻器并联的第一导通二极管连接到顶部功率电子开关发射极电压采样点，当顶部功率电子开关发射极的电压高于顶部栅极驱动器的基准的电压时，所述第一导通二极管被极化以使第一电阻器短路；
顶部栅极驱动器的基准经由第二电阻器连接到底部功率电子开关集电极电压采样点；
底部栅极驱动器的基准经由与第三电阻器并联的第二导通二极管连接到底部功率电子开关发射极电压采样点，当底部功率电子开关发射极的电压高于底部栅极驱动器的基准的电压时，所述第二导通二极管被极化以使第三电阻器短路；
底部栅极驱动器的基准经由第四电阻器连接到负电压电源接片。
16.一种三相功率转换器，包括三个根据权利要求14或15限定的功率转换器。
CN201680043194.0A 2015-06-23 2016-06-16 功率转换器的物理拓扑结构 Active CN107851661B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201562183437P 2015-06-23 2015-06-23
US62/183,437 2015-06-23
PCT/CA2016/050702 WO2016205929A1 (en) 2015-06-23 2016-06-16 Physical topology for a power converter

Publications (2)

Publication Number Publication Date
CN107851661A true CN107851661A (zh) 2018-03-27
CN107851661B CN107851661B (zh) 2021-09-07

Family

ID=57584333

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201680043194.0A Active CN107851661B (zh) 2015-06-23 2016-06-16 功率转换器的物理拓扑结构

Country Status (8)

Country Link
US (1) US10277112B2 (zh)
EP (1) EP3314656B1 (zh)
JP (1) JP2018520625A (zh)
KR (1) KR20180019610A (zh)
CN (1) CN107851661B (zh)
CA (1) CA2989672C (zh)
HK (1) HK1252919A1 (zh)
WO (1) WO2016205929A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108447846A (zh) * 2018-06-06 2018-08-24 臻驱科技（上海）有限公司 一种功率半导体模块衬底及功率半导体模块
CN108447847A (zh) * 2018-06-06 2018-08-24 臻驱科技（上海）有限公司 一种功率半导体模块衬底及功率半导体模块
CN112930642A (zh) * 2018-11-05 2021-06-08 三菱电机株式会社 栅极驱动电路和功率转换装置

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3350910B1 (en) 2015-09-14 2021-04-14 DANA TM4 Inc. Power converter configured for limiting switching overvoltage
CN109997223B (zh) * 2016-11-25 2023-06-30 日立能源瑞士股份公司 功率半导体模块
CN117393509A (zh) 2017-04-20 2024-01-12 罗姆股份有限公司 半导体器件
JP7163054B2 (ja) * 2017-04-20 2022-10-31 ローム株式会社 半導体装置
CN107946293A (zh) * 2017-12-22 2018-04-20 江苏宏微科技股份有限公司 一种功率模块封装结构
US10418307B2 (en) * 2017-12-22 2019-09-17 Deere & Company Electronic assembly with a direct bonded copper substrate
KR102596436B1 (ko) 2018-02-20 2023-11-01 삼성전자주식회사 사용자 발화를 처리하는 시스템 및 그 시스템의 제어 방법
EP3806313A4 (en) * 2018-05-28 2021-07-21 Mitsubishi Electric Corporation POWER CONVERSION DEVICE
JP7491043B2 (ja) 2020-05-13 2024-05-28 富士電機株式会社 半導体モジュール

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998033267A2 (en) * 1997-01-24 1998-07-30 Fische, Llc High efficiency power converter
CN1274192A (zh) * 1999-05-14 2000-11-22 株式会社日立制作所 电力转换***
CN103296905A (zh) * 2013-05-24 2013-09-11 西安理工大学 三相电压型功率因数校正变换器的自适应控制方法
WO2014043795A1 (en) * 2012-09-24 2014-03-27 Tm4 Inc. Topology for controlled power switch module
CN103988410A (zh) * 2011-12-07 2014-08-13 Tm4股份有限公司 用于绝缘栅双极型晶体管的关断过电压限制
WO2015070344A1 (en) * 2013-11-14 2015-05-21 Tm4 Inc. Compensation circuit, commutation cell and power converter controlling turn-on and turn-off of a power electronic switch

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4432953B2 (ja) 2006-09-27 2010-03-17 株式会社日立製作所 半導体電力変換装置
KR20150140304A (ko) 2013-04-04 2015-12-15 티엠4 인코포레이티드 정류 셀 및 그 보상 회로
CN105765850B (zh) 2013-11-01 2019-11-05 Tm4股份有限公司 被配置用于限制切换过压的电力变换器
KR20160086345A (ko) 2013-11-14 2016-07-19 티엠4 인코포레이티드 동적으로 제어되는 전압 이득을 가진 커뮤테이션 셀, 전력 변환기 및 보상 회로
JP2017511115A (ja) 2014-03-20 2017-04-13 ティーエム４・インコーポレーテッド 電子スイッチのコレクタ−エミッタ間電圧の変動を制御するゲートドライバおよび同ゲートドライバを含む回路
US9595954B2 (en) * 2014-11-10 2017-03-14 Nxp Usa, Inc. Method and circuit for recharging a bootstrap capacitor using a transfer capacitor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998033267A2 (en) * 1997-01-24 1998-07-30 Fische, Llc High efficiency power converter
CN1274192A (zh) * 1999-05-14 2000-11-22 株式会社日立制作所 电力转换***
CN103988410A (zh) * 2011-12-07 2014-08-13 Tm4股份有限公司 用于绝缘栅双极型晶体管的关断过电压限制
WO2014043795A1 (en) * 2012-09-24 2014-03-27 Tm4 Inc. Topology for controlled power switch module
CN103296905A (zh) * 2013-05-24 2013-09-11 西安理工大学 三相电压型功率因数校正变换器的自适应控制方法
WO2015070344A1 (en) * 2013-11-14 2015-05-21 Tm4 Inc. Compensation circuit, commutation cell and power converter controlling turn-on and turn-off of a power electronic switch

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ERIC AZEROUAL、DIPL.-ING.JEAN-MARC CYR NG: "limiting the overshoot on IGBT during turn-off using stray inductance，development power electronics", 《ATZ ELEKTRONIK》 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108447846A (zh) * 2018-06-06 2018-08-24 臻驱科技（上海）有限公司 一种功率半导体模块衬底及功率半导体模块
CN108447847A (zh) * 2018-06-06 2018-08-24 臻驱科技（上海）有限公司 一种功率半导体模块衬底及功率半导体模块
CN112930642A (zh) * 2018-11-05 2021-06-08 三菱电机株式会社 栅极驱动电路和功率转换装置

Also Published As

Publication number Publication date
US10277112B2 (en) 2019-04-30
EP3314656B1 (en) 2021-08-04
CA2989672A1 (en) 2016-12-29
US20180183321A1 (en) 2018-06-28
JP2018520625A (ja) 2018-07-26
EP3314656A4 (en) 2019-02-20
HK1252919A1 (zh) 2019-06-06
CN107851661B (zh) 2021-09-07
KR20180019610A (ko) 2018-02-26
EP3314656A1 (en) 2018-05-02
CA2989672C (en) 2022-11-29
WO2016205929A1 (en) 2016-12-29

Similar Documents

Publication Publication Date Title
CN107851661A (zh) 功率转换器的物理拓扑结构
US11095280B2 (en) Efficient IGBT switching
CN108400721B (zh) 车辆用的电驱动器、栅极驱动器和逆变器
KR102236287B1 (ko) GaN 트랜지스터 기반 파워 컨버터를 위한 부트스트랩 커패시터 과전압 관리 회로
US10122294B2 (en) Active gate clamping for inverter switching devices with enhanced common source inductance
WO2012153836A1 (ja) スイッチング回路及び半導体モジュール
CN112019200A (zh) 包括故障安全下拉电路的功率器件和电子开关器件
EP2789092B1 (en) Turn-off overvoltage limiting for igbt
CN104756390B (zh) 用于受控电源开关模块的拓扑
US10250115B2 (en) Inverter switching devices with common source inductance layout to avoid shoot-through
US20100085105A1 (en) Circuit arrangement including a voltage supply circuit and semiconductor switching element
IL95438A (en) Switching circuit
JP2014130909A (ja) 電力用半導体装置
CN101335483A (zh) 电力变换装置
JP5619673B2 (ja) スイッチング回路及び半導体モジュール
JP2013070530A (ja) ゲート駆動回路、電力変換回路、３相インバータ、及びゲート駆動方法
CN106464122A (zh) 控制电子开关的集电极到发射极电压变化的栅极驱动器以及包括所述栅极驱动器的电路
CN111231692A (zh) 具有在栅极驱动器处生成的增强共源极电感的逆变器***
CN105871289B (zh) 驱动装置和输送机械
CN102739218A (zh) 开关装置和开关模块
US10715134B2 (en) Power module, reverse-conducting IGBT, and drive circuit
JP2004187360A (ja) 電圧駆動型スイッチング素子のゲ−ト駆動回路および半導体モジュ−ル
CN108141129A (zh) 配置为限制开关过电压的电力转换器
KR101301221B1 (ko) 3상 모터 드라이브용 전력회로 및 3상 모터 드라이브용 전력모듈

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
REG Reference to a national code

Ref country code: HK

Ref legal event code: DE

Ref document number: 1252919

Country of ref document: HK

GR01 Patent grant
GR01 Patent grant