CN107832496A - Method and system for emulation - Google Patents
Method and system for emulation Download PDFInfo
- Publication number
- CN107832496A CN107832496A CN201710959456.4A CN201710959456A CN107832496A CN 107832496 A CN107832496 A CN 107832496A CN 201710959456 A CN201710959456 A CN 201710959456A CN 107832496 A CN107832496 A CN 107832496A
- Authority
- CN
- China
- Prior art keywords
- language
- excitation signal
- client
- program
- serve end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Stored Programmes (AREA)
Abstract
The application provides a kind of method and system for being used to emulate, and an embodiment of methods described includes：Serve end program and client-side program are established by socket port and connected；The initial excitation signal described using TCL language or C language is obtained by serve end program；Initial excitation signal is transferred to client-side program by serve end program；Initial excitation signal is transferred to data conversion module by client-side program；The target excitation signal for being converted into describing using Verilog HDL language or VHDL language by initial excitation signal by data conversion module；Target excitation signal write-in FPGA is emulated to the input port of user terminal by data conversion module.The initial excitation signal that the embodiment is described using TCL language or C language, without writing substantial amounts of test code, if pumping signal write it is wrong, without writing again.So as to shorten the testing time, simulation efficiency is improved.
Description
Technical field
The application is related to computer realm, more particularly to a kind of method and system for being used to emulate.
Background technology
In general, when be related to FPGA emulation, top layer text is first typically write using Verilog HDL language
The I/O pumping signals of part, then emulation is performed using pumping signal.But, on the one hand, for some complicated signalling engineerings, need
The pumping signal of complexity is write, because logic realization is complex, therefore, it is necessary to writes substantial amounts of test code.The opposing party
Face, after pumping signal is finished, pumping signal can not be modified in emulation.So if pumping signal write it is wrong, it is necessary to
Again write, and restart to emulate.Therefore, the testing time is extended, reduces simulation efficiency.
The content of the invention
One of in order to solve the above-mentioned technical problem, the application provides a kind of method and system for being used to emulate.
According to the first aspect of the embodiment of the present application, there is provided a kind of method for being used to emulate, including：
Serve end program and client-side program are established by socket port and connected；
The initial excitation signal described using TCL language or C language is obtained by the serve end program；
The initial excitation signal is transferred to the client-side program by the serve end program；
The initial excitation signal is transferred to data conversion module by the client-side program；
The initial excitation signal is converted into by the data conversion module to use Verilog HDL language or VHDL languages
Say the target excitation signal of description；
Target excitation signal write-in FPGA is emulated to the input port of user terminal by the data conversion module.
Optionally, methods described also includes：
The FPGA emulation user terminal reads the target excitation signal；
The FPGA emulation user terminal is treated Simulation Engineering using the target excitation signal and emulated, and is used
Verilog HDL language or the primary data of VHDL language description；
The initial data transfer is given to the data conversion module by FPGA emulation user terminals；
The number of targets for being converted into describing using TCL language or C language by the primary data by the data conversion module
According to；
The target data is transferred to the client-side program by the data conversion module；
The target data is transferred to the serve end program by the client-side program, to enter to the target data
Row analysis.
Optionally, described establish serve end program and client-side program by socket port connects, including：
Open the socket port of the serve end program and the socket port of the client-side program；
From the socket port of the client-side program connection request is sent to the socket port of the serve end program；
The socket port of the serve end program is in response to the connection request, to the socket of the client-side program
Port sends the socket port description of the serve end program；
If the socket port of the client-side program confirms the description, successful connection is established.
It is optionally, described that the initial excitation signal described using TCL language or C language is obtained by the serve end program,
Including：
The initial excitation signal described using TCL language is obtained from TCL script files by the serve end program；
Or
Obtained by the serve end program from the C language file of socket port using the described initial of C language description
Pumping signal.
According to the second aspect of the embodiment of the present application, there is provided a kind of system for being used to emulate, including：Serve end program, visitor
Family end program, data conversion module and FPGA emulation user terminals；
The serve end program, connected for being established by socket port and client-side program, acquisition uses TCL language
Or the initial excitation signal of C language description, and the initial excitation signal is transferred to the client-side program；
The client-side program, for the initial excitation signal to be transferred into data conversion module；
The data conversion module, for the initial excitation signal to be converted into using Verilog HDL language or
VHDL language description target excitation signal, and by the target excitation signal write-in FPGA emulation user terminal input port.
Optionally, the FPGA emulation user terminal, for reading the target excitation signal, is believed using the target excitation
Number treating Simulation Engineering is emulated, and obtains the primary data described using Verilog HDL language or VHDL language, and by institute
Initial data transfer is stated to the data conversion module；
The data conversion module, it is additionally operable to for the primary data to be converted into the mesh using TCL language or C language description
Data are marked, and the target data is transferred to the client-side program；
The client-side program, it is additionally operable to the target data being transferred to the serve end program, with to the target
Data are analyzed.
Optionally, the client-side program, it is additionally operable to send connection request to the socket port of the serve end program；
The serve end program, it is additionally operable in response to the connection request, to the socket port of the client-side program
Send the socket port description of the serve end program；If the socket port of the client-side program confirms the description,
Then establish successful connection.
Optionally, the serve end program is arranged to：
The initial excitation signal using the description of TCL language is obtained from TCL script files；Or
The initial excitation signal using C language description is obtained from the C language file of socket port.
The technical scheme that embodiments herein provides can include the following benefits：
The method and system for being used to emulate that embodiments herein provides, serve end program and client-side program are passed through
Socket port establishes connection, and the initial excitation signal described using TCL language or C language is obtained by serve end program, and will
Initial excitation signal is transferred to client-side program, and initial excitation signal is transferred into data conversion module by client-side program, by
Initial excitation signal is converted into believing using the target excitation that Verilog HDL language or VHDL language describe by data conversion module
Number, and by target excitation signal write-in FPGA emulation user terminal input port.Due to what is described using TCL language or C language
Initial excitation signal, it is therefore not necessary to write substantial amounts of test code, also, if pumping signal write it is wrong, without compiling again
Write.So as to shorten the testing time, simulation efficiency is improved.
It should be appreciated that the general description and following detailed description of the above are only exemplary and explanatory, not
The application can be limited.
Brief description of the drawings
Accompanying drawing herein is merged in specification and forms the part of this specification, shows the implementation for meeting the application
Example, and be used to together with specification to explain the principle of the application.
Fig. 1 is a kind of schematic diagram of a scenario that is used to emulate of the application according to an exemplary embodiment；
Fig. 2 is a kind of flow chart of the method that is used to emulate of the application according to an exemplary embodiment；
Fig. 3 is the flow chart for the method that another kind of the application according to an exemplary embodiment is used for emulation；
Fig. 4 is a kind of block diagram of the device that is used to emulate of the application according to an exemplary embodiment.
Embodiment
Here exemplary embodiment will be illustrated in detail, its example is illustrated in the accompanying drawings.Following description is related to
During accompanying drawing, unless otherwise indicated, the same numbers in different accompanying drawings represent same or analogous key element.Following exemplary embodiment
Described in embodiment do not represent all embodiments consistent with the application.On the contrary, they be only with it is such as appended
The example of the consistent apparatus and method of some aspects be described in detail in claims, the application.
It is only merely for the purpose of description specific embodiment in term used in this application, and is not intended to be limiting the application.
" one kind " of singulative used in the application and appended claims, " described " and "the" are also intended to including majority
Form, unless context clearly shows that other implications.It is also understood that term "and/or" used herein refers to and wrapped
Containing the associated list items purpose of one or more, any or all may be combined.
It will be appreciated that though various information, but this may be described using term first, second, third, etc. in the application
A little information should not necessarily be limited by these terms.These terms are only used for same type of information being distinguished from each other out.For example, do not departing from
In the case of the application scope, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as
One information.Depending on linguistic context, word as used in this " if " can be construed to " ... when " or " when ...
When " or " in response to determining ".
As shown in figure 1, Fig. 1 is a kind of schematic diagram of a scenario for being used to emulate according to an exemplary embodiment：In Fig. 1
In the scene shown, analogue system can include serve end program, client-side program, data conversion module and FPGA emulation and use
Family end.Wherein, serve end program, client-side program, data conversion module and FPGA emulation user terminals can be installed on same
Station terminal equipment, cooperate, complete artificial tasks jointly.
When being emulated, first, the socket port of serve end program and the socket ends of client-side program are opened
Mouthful, send connection request to the socket port of serve end program from the socket port of client-side program.Serve end program
Socket port sends the socket port of serve end program in response to the connection request to the socket port of client-side program
Description, if the socket port of client-side program confirms the description, serve end program passes through socket with client-side program
Successful connection is established in port.
Then, serve end program can obtain the initial excitation signal using the description of TCL language from TCL script files.
Or serve end program can also obtain the initial excitation letter using C language description from the C language file of socket port
Number.Initial excitation signal is transferred to client-side program by serve end program.Initial excitation signal is transferred to by client-side program
Initial excitation signal is converted into retouching using Verilog HDL language or VHDL language by data conversion module, data conversion module
The target excitation signal stated, and by target excitation signal write-in FPGA emulation user terminal input port.
Then, FPGA emulates user terminal and reads target excitation signal, and treats Simulation Engineering using target excitation signal and enter
Row emulation, so as to obtain the primary data described using Verilog HDL language or VHDL language.
Finally, FPGA emulates user terminal by initial data transfer to data conversion module, will be initial by data conversion module
The target data that data conversion describes into use TCL language or C language.Target data is transferred to client by data conversion module
Program, target data is transferred to serve end program by client-side program, serve end program can be analyzed target data.
As shown in Fig. 2 Fig. 2 is a kind of flow chart of method for being used to emulate according to an exemplary embodiment, should
Method can apply in terminal device.Serve end program for emulation, client journey can be installed in the terminal device
Sequence, data conversion module and FPGA emulation user terminals.This method comprises the following steps：
In step 201, serve end program and client-side program are established by socket port and connected.
In the present embodiment, when being emulated, the socket port and client-side program of serve end program are opened
Socket port, connection request is sent to the socket port of serve end program from the socket port of client-side program.Service
The socket port of program is held to send serve end program to the socket port of client-side program in response to the connection request
Socket port describes, if the socket port of client-side program confirms the description, serve end program and client-side program
Successful connection is established by socket port.
In step 202, the initial excitation signal described using TCL language or C language is obtained by serve end program.
In the present embodiment, serve end program can obtain from TCL script files is swashed using the initial of TCL language description
Signal is encouraged, the initial excitation signal using C language description can also be obtained from the C language file of socket port.
In step 203, initial excitation signal is transferred to client-side program by serve end program.
In step 204, initial excitation signal is transferred to data conversion module by client-side program.
In step 205, by data conversion module initial excitation signal is converted into using Verilog HDL language or
The target excitation signal of VHDL language description.
In the present embodiment, initial excitation signal is described using TCL language or C language, still, FPGA None- identifieds TCL
Initial excitation signal is converted into using Verilog HDL language or VHDL languages by language or C language, therefore, data conversion module
The target excitation signal of description is sayed, can be emulated using target excitation signal.
In step 206, target excitation signal write-in FPGA is emulated to the input port of user terminal by data conversion module.
The method for being used to emulate that above-described embodiment of the application provides, serve end program and client-side program are passed through
Socket port establishes connection, and the initial excitation signal described using TCL language or C language is obtained by serve end program, and will
Initial excitation signal is transferred to client-side program, and initial excitation signal is transferred into data conversion module by client-side program, by
Initial excitation signal is converted into believing using the target excitation that Verilog HDL language or VHDL language describe by data conversion module
Number, and by target excitation signal write-in FPGA emulation user terminal input port.Due to what is described using TCL language or C language
Initial excitation signal, it is therefore not necessary to write substantial amounts of test code, also, if pumping signal write it is wrong, without compiling again
Write.So as to shorten the testing time, simulation efficiency is improved.
As shown in figure 3, another kinds of the Fig. 3 according to an exemplary embodiment is used for the flow chart of the method emulated, should
Method can apply in terminal device.Serve end program for emulation, client journey can be installed in the terminal device
Sequence, data conversion module and FPGA emulation user terminals.This method comprises the following steps：
In step 301, serve end program and client-side program are established by socket port and connected.
In step 302, the initial excitation signal described using TCL language or C language is obtained by serve end program.
In step 303, initial excitation signal is transferred to client-side program by serve end program.
In step 304, initial excitation signal is transferred to data conversion module by client-side program.
In step 305, by data conversion module initial excitation signal is converted into using Verilog HDL language or
The target excitation signal of VHDL language description.
Within step 306, target excitation signal write-in FPGA is emulated to the input port of user terminal by data conversion module.
In step 307, FPGA emulates user terminal and reads target excitation signal.
In step 308, FPGA emulation user terminal is treated Simulation Engineering using target excitation signal and emulated, and is adopted
The primary data described with Verilog HDL language or VHDL language.
In a step 309, user terminal is emulated by initial data transfer to data conversion module by FPGA.
In the step 310, the mesh for being converted into describing using TCL language or C language by primary data by data conversion module
Mark data.
In step 311, target data is transferred to client-side program by data conversion module.
In step 312, target data is transferred to serve end program by client-side program, to divide target data
Analysis.
It should be noted that for the step identical with Fig. 2 embodiments, no longer gone to live in the household of one's in-laws on getting married in above-mentioned Fig. 3 embodiments
State, related content can be found in Fig. 2 embodiments.
The method for being used to emulate that above-described embodiment of the application provides, serve end program and client-side program are passed through
Socket port establishes connection, and the initial excitation signal described using TCL language or C language is obtained by serve end program, and will
Initial excitation signal is transferred to client-side program, and initial excitation signal is transferred into data conversion module by client-side program, by
Initial excitation signal is converted into believing using the target excitation that Verilog HDL language or VHDL language describe by data conversion module
Number, and by target excitation signal write-in FPGA emulation user terminal input port.FPGA emulation user terminals read target excitation letter
Number, and Simulation Engineering is treated using target excitation signal and emulated, obtain retouching using Verilog HDL language or VHDL language
The primary data stated.Will be initial to data conversion module, data conversion module by initial data transfer by FPGA emulation user terminals
Target data is transferred to client-side program by data conversion into the target data described using TCL language or C language.Client
Target data is transferred to serve end program by end program, to analyze target data.Due to using TCL language or C language
The initial excitation signal of description, it is therefore not necessary to write substantial amounts of test code, also, if pumping signal write it is wrong, without
Again write.Simultaneously, additionally it is possible to return to the target data described using TCL language or C language, improve and target data is carried out
The efficiency of analysis.So as to further shorten the testing time, simulation efficiency is favorably improved.
It should be noted that although describing the operation of the application method with particular order in the accompanying drawings, still, this is not required that
Or imply and must perform these operations according to the particular order, or the operation having to carry out shown in whole could realize the phase
The result of prestige.On the contrary, the step of describing in flow chart can change execution sequence.Additionally or alternatively, it is convenient to omit some
Step, multiple steps are merged into a step and performed, and/or a step is decomposed into execution of multiple steps.
Corresponding with the embodiment of the method for being previously used for emulation, present invention also provides the implementation of the system for emulation
Example.
As shown in figure 4, Fig. 4 is a kind of system block diagram that is used to emulate of the application according to an exemplary embodiment,
The system can include：Serve end program 401, client-side program 402, data conversion module 403 and FPGA emulation user terminals
404。
Wherein, serve end program 401, connected for being established by socket port and client-side program 402, obtain and use
TCL language or the initial excitation signal of C language description, and initial excitation signal is transferred to client-side program 402.
Client-side program 402, for initial excitation signal to be transferred into data conversion module 403.
Data conversion module 403, for being converted into initial excitation signal to use Verilog HDL language or VHDL language
The target excitation signal of description, and by target excitation signal write-in FPGA emulation user terminal 404 input port.
In some optional embodiments, FPGA emulation user terminals 404, for reading target excitation signal, using target
Pumping signal is treated Simulation Engineering and emulated, and obtains the primary data described using Verilog HDL language or VHDL language,
And by initial data transfer to data conversion module 403.
Data conversion module 403, it is additionally operable to for primary data to be converted into the number of targets using TCL language or C language description
According to, and target data is transferred to client-side program 402.
Client-side program 402, it is additionally operable to target data being transferred to serve end program 401, to divide target data
Analysis.
In other optional embodiments, client-side program 402, the socket ends to serve end program 401 are additionally operable to
Mouth sends connection request.
Serve end program 401, it is additionally operable in response to connection request, clothes is sent to the socket port of client-side program 402
The socket port description for end program 401 of being engaged in, if the socket port of client-side program 402 confirms foregoing description, the company of foundation
It is connected into work(.
In other optional embodiments, serve end program 401 is arranged to：Obtain and adopt from TCL script files
The initial excitation signal described with TCL language；Or obtained from the C language file of socket port using C language description
Initial excitation signal.
It should be appreciated that said apparatus can be set in advance in terminal device, can also be loaded by modes such as downloads
Into terminal device.Corresponding module in said apparatus can cooperate with the module in terminal device to be used to emulate to realize
Scheme.
For device embodiment, because it corresponds essentially to embodiment of the method, so related part is real referring to method
Apply the part explanation of example.Device embodiment described above is only schematical, wherein described be used as separating component
The unit of explanation can be or may not be physically separate, can be as the part that unit is shown or can also
It is not physical location, you can with positioned at a place, or can also be distributed on multiple NEs.Can be according to reality
Need to select some or all of module therein to realize the purpose of application scheme.Those of ordinary skill in the art are not paying
In the case of going out creative work, you can to understand and implement.
Those skilled in the art will readily occur to the application its after considering specification and putting into practice invention disclosed herein
Its embodiment.The application is intended to any modification, purposes or the adaptations of the application, these modifications, purposes or
Person's adaptations follow the general principle of the application and including the undocumented common knowledges in the art of the application
Or conventional techniques.Description and embodiments are considered only as exemplary, and the true scope of the application and spirit are by following
Claim is pointed out.
It should be appreciated that the precision architecture that the application is not limited to be described above and is shown in the drawings, and
And various modifications and changes can be being carried out without departing from the scope.Scope of the present application is only limited by appended claim.
Claims (8)
- A kind of 1. method for being used to emulate, it is characterised in that methods described includes：Serve end program and client-side program are established by socket port and connected；The initial excitation signal described using TCL language or C language is obtained by the serve end program；The initial excitation signal is transferred to the client-side program by the serve end program；The initial excitation signal is transferred to data conversion module by the client-side program；The initial excitation signal is converted into retouching using Verilog HDL language or VHDL language by the data conversion module The target excitation signal stated；Target excitation signal write-in FPGA is emulated to the input port of user terminal by the data conversion module.
- 2. according to the method for claim 1, it is characterised in that methods described also includes：The FPGA emulation user terminal reads the target excitation signal；The FPGA emulation user terminal is treated Simulation Engineering using the target excitation signal and emulated, and is used Verilog HDL language or the primary data of VHDL language description；The initial data transfer is given to the data conversion module by FPGA emulation user terminals；The target data for being converted into describing using TCL language or C language by the primary data by the data conversion module；The target data is transferred to the client-side program by the data conversion module；The target data is transferred to the serve end program by the client-side program, to divide the target data Analysis.
- 3. according to the method for claim 1, it is characterised in that described to pass through serve end program and client-side program Socket port establishes connection, including：Open the socket port of the serve end program and the socket port of the client-side program；From the socket port of the client-side program connection request is sent to the socket port of the serve end program；The socket port of the serve end program is in response to the connection request, to the socket port of the client-side program Send the socket port description of the serve end program；If the socket port of the client-side program confirms the description, successful connection is established.
- 4. according to the method for claim 1, it is characterised in that described obtained by the serve end program uses TCL language Or the initial excitation signal of C language description, including：The initial excitation signal described using TCL language is obtained from TCL script files by the serve end program；OrThe initial excitation described using C language is obtained from the C language file of socket port by the serve end program Signal.
- 5. a kind of system for being used to emulate, it is characterised in that the system includes：Serve end program, client-side program, data turn Change the mold block and FPGA emulation user terminals；The serve end program, connected for being established by socket port and client-side program, acquisition uses TCL language or C The initial excitation signal of language description, and the initial excitation signal is transferred to the client-side program；The client-side program, for the initial excitation signal to be transferred into data conversion module；The data conversion module, for being converted into the initial excitation signal to use Verilog HDL language or VHDL languages The target excitation signal of description is sayed, and target excitation signal write-in FPGA is emulated to the input port of user terminal.
- 6. system according to claim 5, it is characterised in thatThe FPGA emulates user terminal, and for reading the target excitation signal, emulation is treated using the target excitation signal Engineering is emulated, and obtains the primary data described using Verilog HDL language or VHDL language, and by the primary data It is transferred to the data conversion module；The data conversion module, it is additionally operable to for the primary data to be converted into the number of targets using TCL language or C language description According to, and the target data is transferred to the client-side program；The client-side program, it is additionally operable to the target data being transferred to the serve end program, with to the target data Analyzed.
- 7. system according to claim 5, it is characterised in thatThe client-side program, it is additionally operable to send connection request to the socket port of the serve end program；The serve end program, it is additionally operable in response to the connection request, is sent to the socket port of the client-side program The socket port description of the serve end program；If the socket port of the client-side program confirms the description, build Vertical successful connection.
- 8. device according to claim 5, it is characterised in that the serve end program is arranged to：The initial excitation signal using the description of TCL language is obtained from TCL script files；OrThe initial excitation signal using C language description is obtained from the C language file of socket port.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710959456.4A CN107832496A (en) | 2017-10-16 | 2017-10-16 | Method and system for emulation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710959456.4A CN107832496A (en) | 2017-10-16 | 2017-10-16 | Method and system for emulation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107832496A true CN107832496A (en) | 2018-03-23 |
Family
ID=61648084
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710959456.4A Pending CN107832496A (en) | 2017-10-16 | 2017-10-16 | Method and system for emulation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107832496A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112560401A (en) * | 2020-12-22 | 2021-03-26 | 成都海光微电子技术有限公司 | Verilog file conversion method, device, storage medium and equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719068A (en) * | 2010-01-06 | 2010-06-02 | 哈尔滨工程大学 | counting loop-oriented C-to-VHDL mapping method and device |
| CN102141951A (en) * | 2010-11-25 | 2011-08-03 | 华为技术有限公司 | Chip simulation system and method |
| CN105116758A (en) * | 2015-08-13 | 2015-12-02 | 杭州杉石科技有限公司 | Simulation method of industrial electronic embedded system |
| CN106155755A (en) * | 2015-06-03 | 2016-11-23 | 上海红神信息技术有限公司 | Program compiling method and compiler |
-
2017
- 2017-10-16 CN CN201710959456.4A patent/CN107832496A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719068A (en) * | 2010-01-06 | 2010-06-02 | 哈尔滨工程大学 | counting loop-oriented C-to-VHDL mapping method and device |
| CN102141951A (en) * | 2010-11-25 | 2011-08-03 | 华为技术有限公司 | Chip simulation system and method |
| CN106155755A (en) * | 2015-06-03 | 2016-11-23 | 上海红神信息技术有限公司 | Program compiling method and compiler |
| CN105116758A (en) * | 2015-08-13 | 2015-12-02 | 杭州杉石科技有限公司 | Simulation method of industrial electronic embedded system |
Non-Patent Citations (1)
| Title |
|---|
| YOUNEVER: ""C语言与verilog 的区别及相互转化"", 《HTTP://BLOG.SINA.COM.CN/S/BLOG_6B2D041F0100PPMG.HTML》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112560401A (en) * | 2020-12-22 | 2021-03-26 | 成都海光微电子技术有限公司 | Verilog file conversion method, device, storage medium and equipment |
| CN112560401B (en) * | 2020-12-22 | 2024-04-09 | 成都海光微电子技术有限公司 | Verilog file conversion method, device, storage medium and equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108170612B (en) | Automatic testing method and device and server | |
| JP2013503393A (en) | System and method for using multiple in-line heuristics to reduce false positives | |
| US10248551B2 (en) | Selective object testing in a client-server environment | |
| Alford | Software Requirements Engineering Methodology (SREM) at the age of two | |
| CN104246759A (en) | Application programming interface testing services | |
| US20230252212A1 (en) | Testbench for sub-design verification | |
| CN112988572A (en) | Multi-environment multi-channel multi-version simulation test method and device | |
| CN110059011A (en) | Interface test method, device, medium and electronic equipment | |
| US11347531B2 (en) | Generalized virtualization platform for systems using hardware abstraction software layers | |
| CN110532182A (en) | A kind of automated testing method and device of virtual platform | |
| CN106201865A (en) | A kind of application programming interface API method of testing, device and terminal unit | |
| US20140156252A1 (en) | Hybrid platform-dependent simulation interface | |
| US10915426B2 (en) | Intercepting and recording calls to a module in real-time | |
| CN107844712A (en) | A kind of browser shares the method, apparatus and computer-readable medium of voucher | |
| CN106844219A (en) | Using detection method and apply detection means | |
| CN107832496A (en) | Method and system for emulation | |
| US10289512B2 (en) | Persistent command parameter table for pre-silicon device testing | |
| CN113495498B (en) | Simulation method, simulator, device and medium for hardware device | |
| CN114640614A (en) | RPC interface automatic test method, system, electronic equipment, medium and product | |
| CN107633219A (en) | Integrated optical character identifying method and system | |
| WO2020138386A1 (en) | Cooperative simulation repeater employing previous trace data | |
| Oyebisi et al. | Development of a remote operational amplifier Ilab using android-based mobile platform | |
| CN111859985A (en) | AI customer service model testing method, device, electronic equipment and storage medium | |
| CN110704051A (en) | Unity interface data binding method | |
| CN110417978A (en) | Menu configuration method, device, equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180323 |