CN107799531B - A kind of 3D nand memory grade layer stack manufacturing method - Google Patents
A kind of 3D nand memory grade layer stack manufacturing method Download PDFInfo
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- CN107799531B CN107799531B CN201711140523.6A CN201711140523A CN107799531B CN 107799531 B CN107799531 B CN 107799531B CN 201711140523 A CN201711140523 A CN 201711140523A CN 107799531 B CN107799531 B CN 107799531B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 37
- 150000004767 nitrides Chemical class 0.000 claims abstract description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 30
- 239000010703 silicon Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000004020 conductor Substances 0.000 claims abstract description 26
- 239000000463 material Substances 0.000 claims abstract description 21
- 239000011248 coating agent Substances 0.000 claims abstract description 12
- 238000000576 coating method Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000009413 insulation Methods 0.000 claims abstract description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 238000000231 atomic layer deposition Methods 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 9
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 8
- 239000010937 tungsten Substances 0.000 claims description 8
- 229910052721 tungsten Inorganic materials 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 238000000427 thin-film deposition Methods 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 238000005429 filling process Methods 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 239000012212 insulator Substances 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 6
- 238000003860 storage Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
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- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000007736 thin film deposition technique Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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Abstract
The present invention relates to a kind of 3D nand memory grade layer stack manufacturing methods, described method includes following steps: forming oxide/nitride grade layer stack on a silicon substrate, then forms the grid line slit for extending vertically through the oxide/nitride grade layer stack；The nitride layer in oxide/nitride grade layer stack is removed, sunk area is formed；It is etched back the sunk area using hydrofluoric acid, so that the oxide layer surface in the oxide/nitride grade layer stack planarizes；Conductor material is inserted in the sunk area, conductor layer is formed and etches the conductor layer, forms conductor/insulation body grade layer stack.3D nand memory grade layer stack manufacturing method of the invention, big header structure is etched back by using hydrofluoric acid (HF), oxide skin(coating) major part phenomenon can be eliminated, to improve the filling rate of conductor layer in 3D NAND grade layer stack, and then improves device performance.
Description
Technical field
The present invention relates to a kind of 3D nand memory grade layer stack manufacturing methods, are related to 3D nand memory manufacture skill
Art field.
Background technique
With the development of semiconductor technology, various semiconductor storage units are proposed.Relative to conventional memory devices such as magnetic
Memory device, semiconductor storage unit have many advantages, such as that access speed is fast, storage density is high.In this, NAND structure just by
More and more concerns.Further to promote storage density, there are a variety of three-dimensional (3D) NAND devices.
It as shown in figs. 1 a-c, is prior art 3D nand memory grade layer stack manufacturing process schematic diagram.Specifically include
Following steps:
(1) as shown in Figure 1A, it is formed with grade layer stack 103 on silicon substrate 101, etches to be formed by dry/wet
Grid line slit 102 (Gate Line Slit, GLS) extends vertically through grade layer stack 103；The grade layer stack 103 by according to
The oxide skin(coating) 104 and nitride layer 105 that minor tick is formed form.Wherein nitride layer 105 can be formed by silicon nitride.
(2) as shown in Figure 1B, it is etched by dry/wet in the grade layer stack 103 near removal grid line slit 102
Nitride layer 105 (such as SiN), formed sunk area 106.
(3) as shown in Figure 1 C, deposited metal tungsten forms tungsten with the sunk area 106 that filling step (2) is formed afterwards
Layer 107.
(4) etching metal tungsten layer 107 ultimately forms new conductor/insulation body grade layer stack 103.
However above-mentioned conventional method has the following deficiencies:
It will use phosphoric acid material, and the etch-rate of phosphoric acid material and silicon therein in the removal technique of silicon nitride layer
Concentration is related.If silicon concentration is high, etch-rate is lower, and etch-rate is higher if instead silicon concentration is low.
When etch-rate is lower, as shown in Figure 1B, at step (2), oxide often regrows, increased more
Remaining oxide (about 5-10 angstroms of thickness, 1 angstrom=10-10Rice), result in the major part phenomenon (circled of Figure 1B of oxide skin(coating) 104
It is shown), and then will lead to and form bubble or hollow area 108 at step (3), this be not intended to occur in NAND device production or
Person wants the phenomenon that avoiding the occurrence of, because this bubble or hollow area eventually result in metal tungsten layer opening or resistance value rises,
To seriously affect device performance.
Usual this major part phenomenon is difficult to avoid, because the silicon concentration in phosphoric acid material is difficult to control, the reason is that when etching
Silicon concentration can be made to increase when removing silicon nitride layer.
Summary of the invention
In order to solve the above-mentioned technical problem, the purpose of the present invention is design a kind of 3D nand memory grade layer stack system
New method is made, big header structure is etched back by using hydrofluoric acid (HF), oxide skin(coating) major part phenomenon can be eliminated.
According to an aspect of the invention, there is provided a kind of 3D nand memory grade layer stack manufacturing method, comprising with
Lower step:
Oxide/nitride grade layer stack is formed on a silicon substrate, is then formed and is extended vertically through the oxide/nitridation
The grid line slit of object grade layer stack；
The nitride layer in oxide/nitride grade layer stack is removed, sunk area is formed；
It is etched back the sunk area using hydrofluoric acid, so that the oxide in the oxide/nitride grade layer stack
Layer surface planarization；
The sunk area is filled using conductor material, form conductor layer and etches the conductor layer, forms conductor/insulation
Body grade layer stack.
Preferably, the nitride layer is formed by silicon nitride.
Preferably, it etches to form the grid line slit and the sunk area using dry/wet.
Preferably, using the nitride layer in phosphoric acid removal oxide/nitride grade layer stack.
Preferably, the concentration of the hydrofluoric acid is HF:H2O=1:500, the etch-back for time are 1 to 5 minutes.
Preferably, the conductive material includes the combination of one or more of tungsten, cobalt, copper, aluminium and silicide.
Preferably, using thin film deposition processes complete described in state filling process and/or formed oxide/nitride grading layer
Storehouse.
It is furthermore preferred that the thin film deposition processes include chemical vapour deposition technique (CVD), physical vaporous deposition (PVD),
One of atomic layer deposition method (ALD).
Preferably, insulating layer is also formed on the oxide/nitride grade layer stack, the grid line slit is vertical
Through oxide/nitride grade layer stack and insulating layer.
According to another aspect of the present invention, a kind of 3D nand memory is additionally provided comprising according to above method system
The conductor/insulation body grade layer stack made.
3D nand memory grade layer stack of the invention manufactures new method, is etched back major part by using hydrofluoric acid (HF)
Structure can eliminate oxide skin(coating) major part phenomenon, to improve the filling rate of conductor layer in 3D NAND grade layer stack, in turn
Improve device performance.
Detailed description of the invention
By reading the following detailed description of the preferred embodiment, various other advantages and benefits are common for this field
Technical staff will become clear.The drawings are only for the purpose of illustrating a preferred embodiment, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings:
Figure 1A-C is prior art 3D nand memory grade layer stack manufacturing process schematic diagram；
Fig. 2A-D is 3D nand memory grade layer stack manufacturing process schematic diagram of the present invention；
Fig. 3 is that there are the latter made grade layer stack photos of major part phenomenon for the prior art；
Fig. 4 is that the present invention eliminates the latter made grade layer stack photo of major part phenomenon.
Specific embodiment
Below in reference to the attached drawing embodiment that the present invention is more fully described, the preferred embodiment of the present invention is shown in the accompanying drawings
Out.However, the present invention can be implemented in different ways, and it should not be construed as limited to embodiments described herein.Whole
Identical appended drawing reference refers to identical element always in a specification.
Although should be appreciated that term first, second etc. can be used to describe various elements here, these elements should not be limited
In these terms.These terms are for making an element be different from another element.For example, first element is properly termed as second yuan
Part, similarly, second element are properly termed as first element, without departing from the scope of the present invention.As used herein, term " and/
Or " include relevant item listed by one or more any and all combination.
It should be appreciated that when claiming an element, in another element "upper", " being connected to " or " being coupled to " another element, it can
To be directly perhaps connected or coupled to another element on another element or there may also be the elements of insertion.On the contrary, working as
Claim on an another element of element " directly existing " or when " being directly connected to " or " being directly coupled to " another element, there is no insert
The element entered.Words of the others for describing relationship between element should explain in a similar way (for example, " ... it
Between " relative to " between directly existing ... ", " adjacent " relative to " direct neighbor " etc.).Here when one element of title is in another element
When upper, it can be directly coupled to another element, or there may be the element of insertion, Huo Zheyuan in another element up or down
Part can be separated by gap or gap.
Terminology used here is not intended to limit the present invention just for the sake of description specific embodiment.As used herein,
It clearly states unless the context otherwise, otherwise singular " one " and "the" are intended to include plural form simultaneously.It should also manage
Solution, term " includes ", " comprising ", " comprising " and/or " comprising ", when here in use, specifying the feature, entirety, step
Suddenly, operation, the presence of element and/or component, but one or more other features, entirety, step, operation, member are not precluded
The presence or addition of part, component and/or combination thereof.
The 3D nand memory grade layer stack manufacturing process of the embodiment of the present invention walks as shown in fig. 2 a-d, including as follows
It is rapid:
S1, as shown in Figure 2 A, grade layer stack 203 is formed on silicon substrate 201, etches to be formed by dry/wet
Grid line slit 202 (Gate Line Slit, GLS) extends vertically through grade layer stack 203；The grade layer stack 203 by according to
The oxide skin(coating) 204 and nitride layer 205 that minor tick is formed form.Wherein nitride layer 205 can be formed by silicon nitride.
In some embodiments, silicon substrate 201 is made of monocrystalline silicon, can also be made of other suitable materials, including but
It is not limited to silicon, germanium, silicon on insulator (Silicon on insulator, SOI) etc..
In some embodiments, grade layer stack 203 is formed in the following way:
Multiple insulator layers pair are formed on a silicon substrate, and multiple insulator layers are to formation grade layer stack, single insulator
Layer material includes but is not limited to the combination of silica, silicon nitride or silicon oxynitride or a variety of above materials, in some embodiments
In, there are more insulator layers pair, the insulator layer has different to being made from a different material in grade layer stack
Thickness.That is, the insulator layer of the insulator layer pair of some positions and other positions is to can be by grade layer stack
Different materials is made and has different thickness, for example, in grade layer stack the insulator layer centering of some positions first
Insulating layer with a thickness of 5-40nm, second insulating layer with a thickness of 5-40nm；The first of the insulator layer centering of other positions
Insulating layer with a thickness of 10-40nm, second insulating layer with a thickness of 10-40nm；The of the insulator layer centering of other position
One insulating layer with a thickness of 50-200nm, second insulating layer with a thickness of 5-40nm.In some embodiments, multiple insulation are formed
Thin film deposition technique, including but not limited to chemical vapour deposition technique (Chemical Vapor can be used in the technique of body layer pair
Deposition, CVD), physical vaporous deposition (Physical Vapor Deposition, PVD) or atomic layer deposition method
(Atomic Layer Deposition,ALD)。
In some embodiments, insulating layer 208 is also formed on grade layer stack 203, grid line slit extends vertically through
Grade layer stack 203 and insulating layer 208.In some embodiments, insulating layer 208 includes silica and/or silicon nitride layer.
In some embodiments, it is also formed with NAND string (not shown) on silicon substrate 201, forms NAND string into one
Step includes being formed to extend vertically through the channel semiconductor of grade layer stack and between channel semiconductor and grade layer stack 203
Dielectric layer.In some embodiments, channel semiconductor is made of amorphous silicon, polysilicon or monocrystalline silicon.In some embodiments,
Dielectric layer is multiple layers of combination, including but not limited to tunnel layer, memory cell layers and barrier layer.In some embodiments, institute
Stating tunnel layer includes insulating materials, including but not limited to the group of silica, silicon nitride or silicon oxynitride or a variety of above-mentioned materials
It closes.In some embodiments, tunnel layer with a thickness of 5-8nm, electronics or hole in channel semiconductor can pass through this layer of tunnel
Channel layer tunnelling is into the memory cell layers of NAND string.In some embodiments, memory cell layers can be used for storing operation NAND
Charge, the storage or removal of the charge in memory cell layers determine the switch state of channel semiconductor.Memory cell layers
Material include but is not limited to silicon nitride, silicon oxynitride or silicon or a variety of above materials combination.In some embodiments,
Memory cell layers with a thickness of 5-8nm.In some embodiments, barrier material is silica, silicon nitride or high dielectric constant
The combination of insulating materials or a variety of above materials.Such as a silicon oxide layer or one include silica/silicon nitride/oxidation
The composite layer with a thickness of 6-9nm of three layers of silicon (ONO).In some embodiments, the barrier layer may further include one
High k dielectric layer (such as aluminium oxide with a thickness of 2-4nm).In some embodiments, formed dielectric layer can using ALD, CVD,
PVD and other suitable methods.
In some embodiments, forming NAND string further comprises being formed in epitaxial layer below the NAND string (in figure
It is not shown), epitaxial layer is silicon layer, is directly contacted with silicon substrate and the epitaxial growth from silicon substrate.In some embodiments, outside
Prolong layer and is further doped to desired doped level.
In some embodiments, the first doped region (not shown), NAND string and grid line are formed on silicon substrate 201
Slit is formed on the first doped region.In some embodiments, the second doped region is also formed on silicon substrate 201 (not show in figure
Out), it is located at the bottom of grid line slit, by being further doped to the first doped region that grid line Slot bottom exposes
It arrives.In some embodiments, the first doped region and the second doped region doping type having the same (are n-type doping or are P
Type doping), the impurity concentration adulterated in the second doped region is greater than the first doped region.In some embodiments, the first doping is formed
Injection and/or diffusion technique can be used in area and the second doped region.
S2, as shown in Figure 2 B, by dry/wet etch removal grade layer stack 203 in nitride layer 205 (such as
SiN), sunk area 206 is formed.
Will use phosphoric acid material in the removal technique of nitride layer 205, and the etch-rate of phosphoric acid material with wherein
Silicon concentration it is related.If silicon concentration is high, etch-rate is lower, and etch-rate is higher if instead silicon concentration is low.Work as erosion
When etching speed is lower, as shown in Figure 2 B, oxide often regrows, and increased undesired oxide (about 5-10 angstroms of thickness, 1
Angstrom=10-10Rice), result in the major part phenomenon of oxide skin(coating) 204 (shown in the circled of Fig. 2 B).
Therefore, in step S2, the silicon concentration in strict control phosphoric acid material is needed, it is raw to avoid serious oxide is generated
Long problem.
S3, as shown in Figure 2 C, be etched back the sunk area 206 using hydrofluoric acid, it is increased extra when removing step S2
Oxide, so that the surface planarisation of oxide skin(coating) 204.
In some embodiments, the concentration of hydrofluoric acid is mass ratio 1:500 (HF:H2O), etch-back for time is 1 to 5 minutes.
In etch-back for time, by controlling the dosage and injection rate of hydrofluoric acid, using sunk area inner surface described in hydrofluoric acid clean,
So that increased undesired oxide (such as silica) generates chemical reaction when hydrofluoric acid and step S2, thus generate be dissolved in it is molten
The reactant (such as SiF) of liquid, thus increased undesired oxide when removal process S2, the major part for eliminating oxide skin(coating) 204 is existing
As.
It is attached on oxide skin(coating) 204 since increased undesired oxide is more open, and used in the present invention
Hydrofluoric acid concentration is very low, and therefore, above-mentioned hydrofluoric acid clean process can easily remove undesired oxide without injuring
The oxide skin(coating) 204 for needing to retain itself.
S4, as shown in Figure 2 D, after conductor material filling nitride layer is removed in the sunk area 206 that is formed, forms
Then conductor layer 207 etches conductor layer 207, ultimately forms new conductor/insulation body grade layer stack 203.
In some embodiments, conductor layer 207 is made of an electrically conducting material, including but not limited to tungsten, cobalt, copper, aluminium and silication
The combination of one or more of object can be used thin film deposition processes and complete above-mentioned filling process, including but not limited to chemical
Vapour deposition process (CVD), physical vaporous deposition (PVD), atomic layer deposition method (ALD) and/or other suitable methods.
In order to verify technical effect of the invention, compared with the prior art.The present invention claps taken the prior art respectively
It is latter made etc. that major part phenomenon is eliminated there are the latter made grade layer stack photo (as shown in Figure 3) of major part phenomenon and through the present invention
Grade layer stack photo (as shown in Figure 4).From figure 3, it can be seen that there are the metal tungsten layer of the grade layer stack of major part phenomenon is (black
Color part) there is opening (line to whiten), and latter made grade layer stack is cleaned using HF through the present invention as shown in Figure 4, tungsten
Layer perfectly eliminates drawbacks described above uniformly and without flaws such as openings.
3D nand memory grade layer stack of the invention manufactures new method, is etched back major part by using hydrofluoric acid (HF)
Structure, can etch away increased undesired oxide (about 5-10 angstroms of thickness, 1 angstrom=10-10Rice), so as to eliminate oxide
Layer major part phenomenon to improve the filling rate of conductor layer in 3D NAND grade layer stack, and then improves device performance.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Subject to enclosing.
Claims (10)
1. a kind of 3D nand memory grade layer stack manufacturing method, characterized in that comprise the steps of:
Oxide/nitride grade layer stack is formed on a silicon substrate, is then formed and is extended vertically through described oxide/nitride etc.
The grid line slit of grade layer stack；
The nitride layer in oxide/nitride grade layer stack is removed, sunk area is formed；
It is etched back the sunk area using hydrofluoric acid, so that the oxide skin(coating) table in the oxide/nitride grade layer stack
Face planarization；
The sunk area is filled using conductor material, form conductor layer and etches the conductor layer, forms conductor/insulation body etc.
Grade layer stack.
2. a kind of 3D nand memory grade layer stack manufacturing method according to claim 1, it is characterized in that:
The nitride layer is formed by silicon nitride.
3. a kind of 3D nand memory grade layer stack manufacturing method according to claim 1, it is characterized in that:
It etches to form the grid line slit and the sunk area using dry/wet.
4. a kind of 3D nand memory grade layer stack manufacturing method according to claim 1, it is characterized in that:
Use the nitride layer in phosphoric acid removal oxide/nitride grade layer stack.
5. a kind of 3D nand memory grade layer stack manufacturing method according to claim 1, it is characterized in that:
The concentration of the hydrofluoric acid is HF:H2O=1:500, the etch-back for time are 1 to 5 minutes.
6. a kind of 3D nand memory grade layer stack manufacturing method according to claim 1, it is characterized in that:
The conductor material includes the combination of one or more of tungsten, cobalt, copper, aluminium and silicide.
7. a kind of 3D nand memory grade layer stack manufacturing method according to claim 1, it is characterized in that:
The filling process is completed using thin film deposition processes and/or forms oxide/nitride grade layer stack.
8. a kind of 3D nand memory grade layer stack manufacturing method according to claim 7, it is characterized in that:
The thin film deposition processes include chemical vapour deposition technique (CVD), physical vaporous deposition (PVD), atomic layer deposition method
One of (ALD).
9. a kind of 3D nand memory grade layer stack manufacturing method according to claim 1, it is characterized in that:
Be also formed with insulating layer on the oxide/nitride grade layer stack, the grid line slit extend vertically through oxide/
Nitride grade layer stack and insulating layer.
10. a kind of 3D nand memory, which is characterized in that it includes -9 any one the methods manufacture according to claim 1
Conductor/insulation body grade layer stack.
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| CN111211129B (en) * | 2020-01-15 | 2023-10-17 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
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| CN103155139A (en) * | 2010-10-14 | 2013-06-12 | 株式会社Eugene科技 | Method and apparatus for manufacturing three-dimensional-structure memory device |
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| CN103155139A (en) * | 2010-10-14 | 2013-06-12 | 株式会社Eugene科技 | Method and apparatus for manufacturing three-dimensional-structure memory device |
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