CN107797442A - Time-to-digital conversion apparatus and digital phase-locked loop - Google Patents
Time-to-digital conversion apparatus and digital phase-locked loop Download PDFInfo
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- CN107797442A CN107797442A CN201711092259.3A CN201711092259A CN107797442A CN 107797442 A CN107797442 A CN 107797442A CN 201711092259 A CN201711092259 A CN 201711092259A CN 107797442 A CN107797442 A CN 107797442A
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The present invention is applied to time accurate measuring technique field, there is provided a kind of time-to-digital conversion apparatus and digital phase-locked loop, described device include：Power control circuit, the first delay circuit, the second delay circuit and time detection circuit；Power control circuit produces first voltage and second voltage and is delivered to the first delay circuit and the second delay circuit respectively；First delay circuit carries out delay disposal according to the first voltage to the first clock signal of reception；Second delay circuit carries out delay disposal according to the second voltage to the second clock signal of reception；Time detection circuit, for receiving the first clock signal and second clock signal after delay disposal, and detect the time difference between the first clock signal and second clock signal.Said apparatus realizes the difference of two delays by inputting different voltage to two delay circuits, and then obtains higher, more stable measurement accuracy, while reduces the requirement to circuit technology and domain.
Description
Technical field
The invention belongs to time accurate measuring technique field, more particularly to a kind of time-to-digital conversion apparatus and digital servo-control
Ring.
Background technology
With the reduction of chip technology size, the small and low in energy consumption advantage of area, all-digital phase-locked loop will progressively substitute biography
System phaselocked loop.Wherein, time-to-digital conversion apparatus realizes output frequency and reference frequency phase difference in all-digital phase-locked loop
Detection.Closely bound up during the detection of the time difference between the detection of phase difference and signal, the precision of time-to-digital conversion apparatus is determined
The frequency accuracy that all-digital phase-locked loop can be realized is determined.
At present, conventional time-to-digital conversion apparatus is prolonged by setting delay cell to do unit to oscillator clock signal
When, then calculate by trigger the time difference of oscillator clock signal and reference clock signal.But this time figure turns
Changing device is larger by the technogenic influence of circuit, such as：In 90nm technique above nodes, the minimum delay 20ps that can be realized；
Below 90nm process nodes, it is possible to achieve 10ps~20ps delay.The time figure of subsequent occurrences of slide measure structure turns
Changing device, by oscillator clock signal and reference clock signal respectively by a delay cell, shaken being calculated by trigger
The time difference of device clock signal and reference clock signal is swung, higher time resolution can be realized.But this slide measure
The requirement that the time-to-digital conversion apparatus of structure matches to the technique and domain of circuit is higher.
The content of the invention
In view of this, the embodiments of the invention provide time-to-digital conversion apparatus and digital phase-locked loop, to solve existing skill
The time resolution of time-to-digital conversion apparatus is not high in art and the requirement that is matched to the technique and domain of circuit is higher
Problem.
The first aspect of the embodiment of the present invention provides a kind of time-to-digital conversion apparatus, including：Power control circuit,
One delay circuit, the second delay circuit and time detection circuit；
The power control circuit is provided with first voltage output end and second voltage output end, the first voltage output
End is connected with first delay circuit, and the second voltage output end is connected with second delay circuit；The power supply control
Circuit processed is used to produce first voltage and second voltage, passes through the first voltage output end and the second voltage output end point
Do not export to first delay circuit and second delay circuit；
First delay circuit, receive the first clock signal, for according to the first voltage to first clock signal
Carry out delay disposal；
Second delay circuit, receive second clock signal, for according to the second voltage to the second clock signal
Carry out delay disposal；
Time detection circuit, for receiving the first clock signal and second clock signal after delay disposal, and examine
The time difference surveyed between the first clock signal and second clock signal.
Optionally, first delay circuit includes multiple first delay cells, and second delay circuit includes multiple
The circuit structure phase of second delay cell, the circuit structure of each first delay cell and each second delay cell
Together.
Optionally, first delay cell is phase inverter or buffer.
Optionally, the power control circuit includes：
Power supply；
Bleeder circuit, is provided with input, the first output end and the second output end, and the input connects with the power supply
Connect, first output end and second output end export different voltage；
First linear voltage regulator, positive pole are connected with the first output end of the bleeder circuit, and negative pole is connected with output end, defeated
Go out end to be also connected with the first delay circuit；
Second linear voltage regulator, positive pole are connected with the second output end of the bleeder circuit, and negative pole is connected with output end, defeated
Go out end to be also connected with the second delay circuit.
Optionally, the time detection circuit includes：
Multiple triggers, the data terminal of n-th trigger are connected with the n-th node of first delay circuit, n-th
The Clock control end of trigger is connected with the n-th node of second delay circuit；Wherein, N is positive integer.
Optionally, first clock signal is oscillator clock signal, and the second clock signal is believed for reference clock
Number.
The second aspect of the embodiment of the present invention provides a kind of digital phase-locked loop, including digital loop filters, oscillator
And the time-to-digital conversion apparatus described in any of the above-described；The time-to-digital conversion apparatus and the digital loop filters
Be connected, the digital loop filters are connected with the oscillator, the oscillator also with the time-to-digital conversion apparatus phase
Even；
The oscillator, for exporting oscillator clock signal to the time-to-digital conversion apparatus；
The digital loop filters, for suppressing the input noise in digital phase-locked loop, it is additionally operable to control the vibration
The output pulse frequency of device；
The time-to-digital conversion apparatus, for detect between the oscillator clock signal and reference clock signal when
Between it is poor.
Existing beneficial effect is the embodiment of the present invention compared with prior art：The embodiment of the present invention, pass through power supply
Circuit output first voltage and second voltage are to the first delay circuit and the second delay circuit so that the first delay circuit and second
Delay circuit carries out different delay disposals to the first clock signal and second clock signal respectively according only to different voltage, leads to
The size for spending the time delay of two delay circuits of the first delay circuit and ground determines the measurement accuracy of time-to-digital conversion apparatus, root
Obtained for first time difference of signal and second clock signal all the time according to time detection circuit.Above-mentioned time-to-digital conversion apparatus passes through
Control to the power supply of delay circuit, reduces the requirement of technique and the domain matching to circuit, while obtains higher time survey
Accuracy of measurement.
Brief description of the drawings
Technical scheme in order to illustrate the embodiments of the present invention more clearly, below will be to embodiment or description of the prior art
In the required accompanying drawing used be briefly described, it should be apparent that, drawings in the following description be only the present invention some
Embodiment, for those of ordinary skill in the art, without having to pay creative labor, can also be according to these
Accompanying drawing obtains other accompanying drawings.
Fig. 1 is the system structure diagram of time-to-digital conversion apparatus provided in an embodiment of the present invention；
Fig. 2 is the circuit diagram of time-to-digital conversion apparatus provided in an embodiment of the present invention；
Fig. 3 is the circuit diagram of power control circuit provided in an embodiment of the present invention；
Fig. 4 is the schematic diagram of digital phase-locked loop provided in an embodiment of the present invention.
Embodiment
In describing below, in order to illustrate rather than in order to limit, it is proposed that such as tool of particular system structure, technology etc
Body details, thoroughly to understand the embodiment of the present invention.However, it will be clear to one skilled in the art that there is no these specific
The present invention can also be realized in the other embodiments of details.In other situations, omit to well-known system, device, electricity
Road and the detailed description of method, in case unnecessary details hinders description of the invention.
In order to illustrate technical solutions according to the invention, illustrated below by specific embodiment.
Embodiment one
Fig. 1 shows the system structure diagram of time-to-digital conversion apparatus, and details are as follows：
Time-to-digital conversion apparatus provided in an embodiment of the present invention includes：Power control circuit 101, the first delay circuit
102nd, the second delay circuit 103 and time detection circuit 104.
Power control circuit 101 is provided with first voltage output end and second voltage output end, the first voltage output
End is connected with first delay circuit 102, and the second voltage output end is connected with second delay circuit 103；It is described
Power control circuit 101 is used to produce first voltage and second voltage, passes through the first voltage output end and second electricity
Pressure output end exports to first delay circuit 102 and second delay circuit 103 respectively.
First delay circuit 102, the first clock signal is received, for believing according to the first voltage first clock
Number carry out delay disposal.
Second delay circuit 103, second clock signal is received, for believing according to the second voltage the second clock
Number carry out delay disposal.
Time detection circuit 104, for receiving the first clock signal and second clock signal after delay disposal, and
Detect the time difference between the first clock signal and second clock signal.
Wherein, first clock signal is postponed by the first delay circuit 102, it is right by the second delay circuit 103
Second clock signal is postponed.First delay circuit 102 is identical with the circuit structure of the second delay circuit 103, so, first
The voltage that delay cell is only exported to delay circuit with the specific retardation of the second delay cell with power control circuit 101 has
Close.Meanwhile the measurement accuracy of time-to-digital conversion apparatus is relevant with the retardation of the first delay cell and the second delay cell, lead to
Cross the measurement accuracy of the output voltage can adjustment time digital switching device of adjustment power control circuit.
Optionally, the first delay circuit 102 includes multiple first delay cells, and the second delay circuit 103 includes multiple the
Two delay cells, the circuit structure of each first delay cell are identical with the circuit structure of each second delay cell.
Referring to Fig. 2, the circuit diagram of time-to-digital conversion apparatus is shown.First delay circuit 102 includes the N number of first delay
Unit, N number of delay cell are sequentially connected in series, by the first clock signal input to the first delay circuit 102.Such as：First delay is single
Member is simplest phase inverter, and the first clock signal of input is in logic-high value, and during first phase inverter of process, phase inverter
Input signal is inverted and exports the logic level opposite with input signal, that is, exports logic low value, but output signal with it is defeated
Enter the delay of a length of TD1 when having between signal.The logic low value of output will be delivered to next phase inverter as input signal,
And export logic-high value.
Signal transmission for the second delay circuit is identical with the first delay circuit, and difference part is：First, input
Clock signal is different；The delay of each delay cell is TD2 in the second, the second delay circuit.It should be noted that the first delay
Circuit 102 is different from the time delay of the second delay circuit 103 only relevant with the voltage of input to delay circuit.
Optionally, the first delay cell is phase inverter or buffer.
Be readily appreciated that, for basic phase inverter with buffer in supply voltage difference, transmission delay also can be different.
Phase inverter and buffer are all based on cmos circuit, and a characteristic of cmos circuit is exactly that transmission delay is relevant with supply voltage,
Input is higher to the supply voltage of delay cell, then the transmission delay of delay cell is smaller；Input to the power supply electricity of delay cell
Pressure is lower, then the transmission delay of delay cell is bigger.Based on this characteristic, using phase inverter and buffer as delay circuit, lead to
Cross and input different voltage for phase inverter and delayer and obtain different delays.
Optionally, power control circuit 101 includes：Power supply；Bleeder circuit, it is provided with input, the first output end and
Two output ends, the input are connected with the power supply, and first output end and second output end export different electricity
Pressure；First linear voltage regulator, positive pole are connected with the first output end of the bleeder circuit, and negative pole is connected with output end, output end
Also it is connected with the first delay circuit；Second linear voltage regulator, positive pole are connected with the second output end of the bleeder circuit, negative pole with
Output end is connected, and output end is also connected with the second delay circuit.
Referring to Fig. 3, the circuit diagram of power control circuit is shown.Wherein, the effect of power control circuit is exactly to export not
With voltage to the first delay circuit 102 and the second delay circuit 103.Wherein, the power supply of access is expressed as VREF, from incoming end
Multiple resistance are set with earth terminal, different resistance is flowed through by electric current to obtain different voltage.Such as：When power supply electricity
When the voltage of first output end on road is the first reference voltage V REF1, the first linear voltage regulator LDO1 positive pole is also defeated with first
When going out to hold connected, the first reference voltage V REF1 of input is adjusted the first linear voltage regulator LDO1, obtains first voltage
VDD1, then first voltage is exported to the first delay circuit.Obtain second voltage VDD2's for the second linear voltage regulator LDO2
Process is identical with the first linear voltage regulator LDO1, repeats no more here.
First linear voltage regulator LDO1 and the second linear voltage regulator LDO2 is preferably low pressure difference linear voltage regulator, and First Line
Property voltage-stablizer LDO1 and the second linear voltage regulator LDO2 circuit structure is identical.For identical linear voltage regulator, pass through input
The difference of reference voltage of regulator, realize the first voltage of output and the difference of second voltage.Wherein, input to first linear
Voltage-stablizer LDO1 and the second linear voltage regulator LDO2 reference voltage can be adjusted by register.The size of reference voltage
Multiple gears can be set, and the delay TD1 of the first delay circuit as needed and the delay TD2's of the second delay circuit is big
It is small, select different reference voltages.Specifically, input can be set to the first linear voltage regulator LDO1 and second by programming
Linear voltage regulator LDO2 reference voltage.
Optionally, time detection circuit 104 includes：Multiple triggers, the data terminal of n-th trigger prolong with described first
The n-th node of slow circuit 102 is connected, the Clock control end of n-th trigger and the n-th of second delay circuit 103
Node is connected；Wherein, N is positive integer.
Referring to Fig. 2, the time detection circuit 104 used here for trigger, trigger be it is a kind of there is memory function,
Information recording device with two stable states, trigger can select rest-set flip-flop, JK flip-flop or d type flip flop, here
Selection for specific trigger is not limited.By taking d type flip flop as an example, illustrate the operation principle of time detection circuit.D type flip flop
With data terminal D, non-inverting output Q and Clock control end CK, the data terminal of n-th trigger is connected to the first delay circuit
102 n-th node, the Clock control end of n-th trigger is connected to the n-th node of the second delay circuit 103, from triggering
The output end of device reads output signal, output signal as caused by trigger and would is that 0 or 1 Serial No..
The output sequence Q0 to Qn of time detection circuit 104 carries the time of the first clock signal and second clock signal
Poor information.When the first clock signal and second clock signal are propagated in the first delay circuit and the second delay circuit, signal
Often pass through a delay cell, the time difference between the first clock signal and second clock signal is increased by TD, wherein, TD=
TD1-TD2.It is assumed that when after M delay cell, there occurs turn from 1 to 0 by the output sequence Q0 to Qm of time detection circuit
Become, or there occurs during the transformation from 0 to 1 by output sequence Q0 to Qm, then it represents that the first clock signal and second clock signal it
Between measuring period difference be M*TD.Wherein, TD is exactly the time resolution of time-to-digital conversion circuit.
For example, when the first voltage of input to the first delay circuit 102 is 1.1V, postpone corresponding to the first delay cell
Time is 30ps, when the second voltage of input to the second delay circuit 103 is 1.4V, when postponing corresponding to the second delay cell
Between be 20ps, then time resolution is 10ps., can be by adjusting the big of first voltage and second voltage according to being actually needed
It is small to change time resolution.
Optionally, the first clock signal is oscillator clock signal, and the second clock signal is reference clock signal.
Wherein, the frequency of general oscillator clock signal is far above the frequency of reference clock signal.When the first clock signal
Inputted from second clock signal to two delay circuits for being delayed different, by calculating the delay time of two delay circuits,
Measurement accuracy with regard to that can obtain time-to-digital conversion apparatus, and then the Serial No. of passage time detection circuit output, calculate shake
Swing the time difference of clock signal and reference clock signal.
Above-mentioned time-to-digital conversion apparatus, first voltage and second voltage are exported to the first delay by power control circuit
Circuit and the second delay circuit so that the first delay circuit and the second delay circuit according only to different voltage respectively to first when
Clock signal and second clock signal carry out different delay disposals, during by the delays of two delay circuits of the first delay circuit and ground
Between size determine the measurement accuracy of time-to-digital conversion apparatus, the first signal and second all the time is obtained according to time detection circuit
The time difference of clock signal.Above-mentioned time-to-digital conversion apparatus is reduced to circuit by the control of the power supply to delay circuit
Technique and the requirement of domain matching, while obtain higher time resolution.
Embodiment two
Referring to Fig. 4, a kind of digital phase-locked loop, including digital loop filtering 200, digital VCO are present embodiments provided
Time-to-digital conversion apparatus 100 described in device 300 and embodiment one；Time-to-digital conversion apparatus 100 is filtered with digital loop
Ripple device 200 is connected, and digital loop filters 200 are connected with voltage controlled oscillator 300, and voltage controlled oscillator 300 also turns with time figure
Changing device 100 is connected.
Digital vco 300, for exporting oscillator clock signal to the time-to-digital conversion apparatus 100.
Wherein, the output of digital vco 300 is a pulse train, and the cycle number of the output pulse sequence
The control for the correction signal that word loop filter 200 is sent.
Digital loop filters 200, for suppressing the input noise in digital phase-locked loop, it is additionally operable to control the numeral pressure
The output pulse frequency of controlled oscillator 300.
Wherein, digital loop filters 200 filter out the high fdrequency component of the output of time-to-digital conversion apparatus 100, then defeated
Go out the input that voltage is added to digital vco 300 so that the local oscillation signal frequency of digital vco 300 is with defeated
Enter the change of voltage and change, and then cause output pulse frequency and reference clock signal caused by digital vco 300
Frequency it is identical.
Time-to-digital conversion apparatus 100, believe for detecting the clock signal of digital vco 300 with reference clock
Time difference between number.
Wherein, time-to-digital conversion apparatus 100 is compared to the oscillator clock signal and reference clock signal of reception,
And export time difference between the two or phase difference or the voltage proportional to phase difference.If when oscillator clock signal and reference
Clock signal frequency is completely the same, and both phase differences will keep some steady state value so that loop is in " lock-out state ".
Phaselocked loop be solve stationary problem core component, and stationary problem be in Modern Communication System systematic function with
The root problem of application.Digital phase-locked loop in the present embodiment may also be referred to as all-digital phase-locked loop in fact, because the present embodiment
In phaselocked loop all parts use be digitizer.
Digital phase-locked loop has precision height compared with traditional analog phase-locked look, not influenceed by temperature and voltage, loop
Bandwidth and centre frequency program the advantages of adjustable.In addition, digital phase-locked loop be also equipped with digital circuit reliability high, small volume and
Low-cost feature.Phaselocked loop is phase feedback control system, in digital phase-locked loop, because error signal is discrete digital letter
Number rather than analog signal, thus the change of controlled output voltage is discrete, rather than continuously.Summary advantage,
Digital phase-locked loop has turned into the direction of Phase Lock Technique development.
Above-mentioned digital phase-locked loop, by the time-to-digital conversion apparatus in above-described embodiment one, digital loop filtering and numeral
Voltage controlled oscillator is formed, and oscillator clock signal is exported to time-to-digital conversion apparatus by digital vco；Pass through number
Word loop filter suppresses the input noise in digital phase-locked loop, and the output pulse frequency that control digital vco arrives
Rate；Passage time digital switching device detects the time difference between digital vco clock signal and reference clock signal.
By using the time-to-digital conversion apparatus in embodiment one, the of regulation input to the first delay circuit and the second delay circuit
One voltage and second voltage obtain different delays, improve the precision of time-to-digital conversion circuit and have stability, enter
And digital phase-locked loop is enabled to obtain higher frequency accuracy and jitter performance.
It should be understood that the size of the sequence number of each step is not meant to the priority of execution sequence, each process in above-described embodiment
Execution sequence should determine that the implementation process without tackling the embodiment of the present invention forms any limit with its function and internal logic
It is fixed.
It is apparent to those skilled in the art that for convenience of description and succinctly, only with above-mentioned each work(
Can unit, module division progress for example, in practical application, can be as needed and by above-mentioned function distribution by different
Functional unit, module are completed, i.e., the internal structure of described device are divided into different functional units or module, more than completion
The all or part of function of description.Each functional unit, module in embodiment can be integrated in a processing unit, also may be used
To be that unit is individually physically present, can also two or more units it is integrated in a unit, it is above-mentioned integrated
Unit can both be realized in the form of hardware, can also be realized in the form of SFU software functional unit.In addition, each function list
Member, the specific name of module are not limited to the protection domain of the application also only to facilitate mutually distinguish.Said system
The specific work process of middle unit, module, the corresponding process in preceding method embodiment is may be referred to, will not be repeated here.
In the above-described embodiments, the description to each embodiment all emphasizes particularly on different fields, and is not described in detail or remembers in some embodiment
The part of load, it may refer to the associated description of other embodiments.
Those of ordinary skill in the art are it is to be appreciated that the list of each example described with reference to the embodiments described herein
Member and algorithm steps, it can be realized with the combination of electronic hardware or computer software and electronic hardware.These functions are actually
Performed with hardware or software mode, application-specific and design constraint depending on technical scheme.Professional and technical personnel
Described function can be realized using distinct methods to each specific application, but this realization is it is not considered that exceed
The scope of the present invention.
In embodiment provided by the present invention, it should be understood that disclosed device/terminal device and method, can be with
Realize by another way.For example, device described above/terminal device embodiment is only schematical, for example, institute
The division of module or unit is stated, only a kind of division of logic function, there can be other dividing mode when actually realizing, such as
Multiple units or component can combine or be desirably integrated into another system, or some features can be ignored, or not perform.Separately
A bit, shown or discussed mutual coupling or direct-coupling or communication connection can be by some interfaces, device
Or INDIRECT COUPLING or the communication connection of unit, can be electrical, mechanical or other forms.
The unit illustrated as separating component can be or may not be physically separate, show as unit
The part shown can be or may not be physical location, you can with positioned at a place, or can also be distributed to multiple
On NE.Some or all of unit therein can be selected to realize the mesh of this embodiment scheme according to the actual needs
's.
In addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, can also
That unit is individually physically present, can also two or more units it is integrated in a unit.Above-mentioned integrated list
Member can both be realized in the form of hardware, can also be realized in the form of SFU software functional unit.
Embodiment described above is merely illustrative of the technical solution of the present invention, rather than its limitations；Although with reference to foregoing reality
Example is applied the present invention is described in detail, it will be understood by those within the art that：It still can be to foregoing each
Technical scheme described in embodiment is modified, or carries out equivalent substitution to which part technical characteristic；And these are changed
Or replace, the essence of appropriate technical solution is departed from the spirit and scope of various embodiments of the present invention technical scheme, all should
Within protection scope of the present invention.
Claims (7)
- A kind of 1. time-to-digital conversion apparatus, it is characterised in that including：Power control circuit, the first delay circuit, the second delay Circuit and time detection circuit；The power control circuit is provided with first voltage output end and second voltage output end, the first voltage output end with The first delay circuit connection, the second voltage output end are connected with second delay circuit；The power supply electricity Road is used to produce first voltage and second voltage, is distinguished by the first voltage output end and the second voltage output end defeated Go out to first delay circuit and second delay circuit；First delay circuit, the first clock signal is received, for being carried out according to the first voltage to first clock signal Delay disposal；Second delay circuit, second clock signal is received, for being carried out according to the second voltage to the second clock signal Delay disposal；Time detection circuit, for receiving the first clock signal and second clock signal after delay disposal, and detect the Time difference between one clock signal and second clock signal.
- 2. time-to-digital conversion apparatus as claimed in claim 1, it is characterised in that first delay circuit includes multiple the One delay cell, second delay circuit include multiple second delay cells, the circuit structure of first delay cell and The circuit structure of second delay cell is identical.
- 3. time-to-digital conversion apparatus as claimed in claim 2, it is characterised in that first delay cell be phase inverter or Buffer.
- 4. time-to-digital conversion apparatus as claimed in claim 1, it is characterised in that the power control circuit includes：Power supply；Bleeder circuit, input, the first output end and the second output end are provided with, the input is connected with the power supply, institute State the first output end and second output end exports different voltage；First linear voltage regulator, positive pole are connected with the first output end of the bleeder circuit, and negative pole is connected with output end, output end Also it is connected with the first delay circuit；Second linear voltage regulator, positive pole are connected with the second output end of the bleeder circuit, and negative pole is connected with output end, output end Also it is connected with the second delay circuit.
- 5. time-to-digital conversion apparatus as claimed in claim 1, it is characterised in that the time detection circuit includes：Multiple triggers, the data terminal of n-th trigger are connected with the n-th node of first delay circuit, n-th triggering The Clock control end of device is connected with the n-th node of second delay circuit；Wherein, N is positive integer.
- 6. the time-to-digital conversion apparatus as described in any one of claim 1 to 5, it is characterised in that first clock signal For oscillator clock signal, the second clock signal is reference clock signal.
- 7. a kind of digital phase-locked loop, it is characterised in that including digital loop filters, digital vco and claim Time-to-digital conversion apparatus described in 1 to 6 any one；The time-to-digital conversion apparatus and the digital loop filters phase Even, the digital loop filters are connected with the digital vco, the digital vco also with the time Digital switching device is connected；The digital vco, for exporting oscillator clock signal to the time-to-digital conversion apparatus；The digital loop filters, for suppressing the input noise in digital phase-locked loop, it is additionally operable to control the numeral voltage-controlled The output pulse frequency of oscillator；The time-to-digital conversion apparatus, for detecting between the digital vco clock signal and reference clock signal Time difference.
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| CN111061145A (en) * | 2019-12-30 | 2020-04-24 | 嘉兴泰传光电有限公司 | Time delay settable time interval measuring device and measuring method based on FPGA |
| IT201900008793A1 (en) * | 2019-06-13 | 2020-12-13 | Fond Bruno Kessler | POWER CIRCUIT MODULE FOR TDC AND CALIBRATION METHOD OF SAID POWER CIRCUIT MODULE |
| CN112824983A (en) * | 2019-11-20 | 2021-05-21 | 圣邦微电子（北京）股份有限公司 | Time measuring circuit, time measuring chip and time measuring device |
| CN114199519A (en) * | 2021-10-31 | 2022-03-18 | 昆山丘钛光电科技有限公司 | Testing device and system |
| WO2022110235A1 (en) * | 2020-11-30 | 2022-06-02 | 华为技术有限公司 | Chip and clock detection method |
| CN114995092A (en) * | 2022-06-15 | 2022-09-02 | 西安电子科技大学芜湖研究院 | Time-to-digital conversion circuit |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005102120A (en) * | 2003-09-04 | 2005-04-14 | Seiko Epson Corp | Delayed phase-locked loop circuit, clock synthesizing circuit, clock multiplying circuit and communication apparatus |
| CN101420217A (en) * | 2008-11-21 | 2009-04-29 | 华东光电集成器件研究所 | Time delay unit |
| CN101694998A (en) * | 2009-10-23 | 2010-04-14 | 中兴通讯股份有限公司 | Locking system and method |
| CN101976036A (en) * | 2010-07-30 | 2011-02-16 | 西安电子科技大学 | Short interval measurement method based on special programmable input and output delay unit |
| CN103840830A (en) * | 2013-12-23 | 2014-06-04 | 华为技术有限公司 | Time-to-digit converter and digital phase-locked loop |
| CN103986461A (en) * | 2014-05-30 | 2014-08-13 | 华为技术有限公司 | Time digital conversion method and time digital converter |
| CN104539288A (en) * | 2015-01-30 | 2015-04-22 | 中国科学技术大学 | TDC (time-to-digital converter) capable of adjusting resolution ratio and ADPLL (all digital phase-locked loop) based on TDC |
| CN104777869A (en) * | 2015-03-27 | 2015-07-15 | 西安华芯半导体有限公司 | Quickly responded low dropout regulator capable of dynamically adjusting reference voltage |
| CN105610434A (en) * | 2016-02-26 | 2016-05-25 | 西安紫光国芯半导体有限公司 | Self-adaptive delay phase-locked loop |
| CN106444345A (en) * | 2016-12-19 | 2017-02-22 | 深圳大学 | Time measurement circuit and method and measuring equipment |
| CN207650568U (en) * | 2017-11-08 | 2018-07-24 | 安凯(广州)微电子技术有限公司 | Time-to-digital conversion apparatus and digital phase-locked loop |
-
2017
- 2017-11-08 CN CN201711092259.3A patent/CN107797442B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005102120A (en) * | 2003-09-04 | 2005-04-14 | Seiko Epson Corp | Delayed phase-locked loop circuit, clock synthesizing circuit, clock multiplying circuit and communication apparatus |
| CN101420217A (en) * | 2008-11-21 | 2009-04-29 | 华东光电集成器件研究所 | Time delay unit |
| CN101694998A (en) * | 2009-10-23 | 2010-04-14 | 中兴通讯股份有限公司 | Locking system and method |
| CN101976036A (en) * | 2010-07-30 | 2011-02-16 | 西安电子科技大学 | Short interval measurement method based on special programmable input and output delay unit |
| CN103840830A (en) * | 2013-12-23 | 2014-06-04 | 华为技术有限公司 | Time-to-digit converter and digital phase-locked loop |
| CN103986461A (en) * | 2014-05-30 | 2014-08-13 | 华为技术有限公司 | Time digital conversion method and time digital converter |
| CN104539288A (en) * | 2015-01-30 | 2015-04-22 | 中国科学技术大学 | TDC (time-to-digital converter) capable of adjusting resolution ratio and ADPLL (all digital phase-locked loop) based on TDC |
| CN104777869A (en) * | 2015-03-27 | 2015-07-15 | 西安华芯半导体有限公司 | Quickly responded low dropout regulator capable of dynamically adjusting reference voltage |
| CN105610434A (en) * | 2016-02-26 | 2016-05-25 | 西安紫光国芯半导体有限公司 | Self-adaptive delay phase-locked loop |
| CN106444345A (en) * | 2016-12-19 | 2017-02-22 | 深圳大学 | Time measurement circuit and method and measuring equipment |
| CN207650568U (en) * | 2017-11-08 | 2018-07-24 | 安凯(广州)微电子技术有限公司 | Time-to-digital conversion apparatus and digital phase-locked loop |
Cited By (18)
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|---|---|---|---|---|
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| IT201900008793A1 (en) * | 2019-06-13 | 2020-12-13 | Fond Bruno Kessler | POWER CIRCUIT MODULE FOR TDC AND CALIBRATION METHOD OF SAID POWER CIRCUIT MODULE |
| WO2020250050A1 (en) * | 2019-06-13 | 2020-12-17 | Fondazione Bruno Kessler | Power supply circuit module for tdc and calibration method of said power supply circuit module |
| JP7201845B2 (en) | 2019-06-13 | 2023-01-10 | フォンダッツィオーネ ブルーノ ケスラー | TDC POWER CIRCUIT MODULE AND CALIBRATION METHOD OF THE POWER CIRCUIT MODULE |
| US11644798B2 (en) | 2019-06-13 | 2023-05-09 | Fondazione Bruno Kessler | Power supply circuit module for TDC and calibration method of said power supply circuit module |
| JP2022535000A (en) * | 2019-06-13 | 2022-08-04 | フォンダッツィオーネ ブルーノ ケスラー | TDC POWER CIRCUIT MODULE AND CALIBRATION METHOD OF THE POWER CIRCUIT MODULE |
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| CN114995092A (en) * | 2022-06-15 | 2022-09-02 | 西安电子科技大学芜湖研究院 | Time-to-digital conversion circuit |
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