CN107768443A - Superjunction devices and its manufacture method - Google Patents
Superjunction devices and its manufacture method Download PDFInfo
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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Abstract
The invention discloses a kind of superjunction devices, there is N-type electric field barrier layer in the p-type post of the superjunction unit of at least more than one, p-type post is divided into first and two p-type posts at the top and bottom of electric field barrier layer by N-type electric field barrier layer in the vertical；N-type electric field barrier layer is used to realize that the segmentation of top and bottom super-junction structure exhausts；When the source-drain voltage of superjunction devices is less than or equal to first voltage value, only top super-junction structure exhausts；When the source-drain voltage of superjunction devices is more than first voltage value, top and bottom super-junction structure all exhausts.The invention also discloses a kind of manufacture method of superjunction devices.The present invention can improve the minimum value of gate leakage capacitance and gate leakage capacitance, so as to effectively reduce electromagnetic interference performance of the device in application circuit and effectively reduce the overshoot of electric current that device brings in application circuit and voltage, the softness factor of the Reverse recovery of device can also be increased, the present invention can also make the breakdown voltage of device be maintained.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing field, more particularly to a kind of superjunction (super junction) device
Part；The invention further relates to a kind of manufacture method of superjunction devices.
Background technology
Super-junction structure is exactly the N-type post and p-type post composition structure being alternately arranged.If substituted with super-junction structure vertical double
Spread in MOS transistor (Vertical Double-diffused Metal-Oxide-Semiconductor, VDMOS) device
N-type drift region, provide conduction path by N-type post in the on-state, p-type post does not provide conduction path during conducting；Cutting
Reversed bias voltage is only born by PN columns jointly under state, is formed superjunction Metal-Oxide Semiconductor field-effect transistor
(Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET).Super node MOSFET can be reverse
In the case that breakdown voltage is consistent with traditional VDMOS device, by using the epitaxial layer of low-resistivity, and make the conducting of device
Resistance is greatly reduced.
As shown in figure 1, being the schematic diagram of existing superjunction devices, the schematic diagram is schematic cross-section；It is flat using superjunction devices
Exemplified by the grid superjunction N-type MOSFET element of face, superjunction devices includes：
Formed with N-type epitaxy layer 30 in the Semiconductor substrate 1 of N-type heavy doping, formed with N-type in N-type epitaxy layer 30
Post 3 and p-type post 4, N-type post 3 and p-type post 4 are alternately arranged to form super-junction structure, the N-type epitaxy layer 30 in the bottom of super-junction structure
Form N-type cushion 30, the impurity concentration of the N-type cushion 30 either with N-type post 3 as impurity concentration or be higher than or
Less than the impurity concentration of N-type post 3, under N-type cushion 30, be impurity concentration it is very high (higher than 1e19 atomicities/cube li
Rice) Semiconductor substrate 1.
One superjunction unit is formed by a N-type post 3 and a p-type post 4, formed with one in each superjunction unit
The primitive cell structure of superjunction devices.
At the top of p-type post 4 formed with p-type trap 7, in p-type trap 7 formed with N+ district's groups into source region 8 and by P+ district's groups
Into p-well draw-out area 9, on the surface of p-type trap 7 formed with gate dielectric layer such as gate oxide 5 and polysilicon gate 6.
Interlayer film 10, contact hole 11, front metal layer 12, source electrode and grid is drawn respectively after front metal layer 12 is graphical
Pole.Drain region is directly made up of the Semiconductor substrate 1 of the heavy doping after being thinned or further adulterates and form, in Semiconductor substrate 1
Drain electrode is drawn formed with metal layer on back 13, metal layer on back 13 in the back side.
Fig. 1 median surfaces C1C2 is the lower surface of the Semiconductor substrate 1 after being thinned, and interface B1B2 is Semiconductor substrate 1
Top surface, interface A 1A2 are the bottom interface of super-junction structure, and interface M1M2 is the top surface of N-type epitaxy layer 30.Interface
Thickness between C1C2 and interface B1B2 is T00, and the thickness between interface C 1C2 and interface M1M2 is T10, interface A 1A2 and boundary
Thickness between the M1M2 of face is T20, and the thickness between interface A 1A2 and interface B1B2 is T30.
Understand as shown in Figure 1, there is a polysilicon gate 6 top of each N-type post 3, and the polysilicon gate 6 can be covered partly
The p-type post 4 on periphery, can not also be covered, and there is a p-type trap 7 top of each p-type post 4, there is a N+ source region in p-type trap 7
8, there is a contact hole 11, source metal is connected by contact hole 11 with source region 8, and the metal of source region 8 is by passing through a high concentration
P-well draw-out area 9 be connected with p-type trap 7.
The top of the p-type post 4 of device is connected to the electrode of source region 8 by contact hole 11, and N-type post 2 is partly led by N+ substrates
Body substrate 11 is connected to drain electrode 13.In the case where relatively low Vds is source-drain voltage, Vds applies horizontal electric field in p-type substantially
Between post 4 and N-type post 3 so that under very low Vds, the p-type post 4 and N-type post 3 being alternately arranged are in the presence of transverse electric field
Exhaust quickly.
Increase to certain data from 0 in Vds voltages, when being, for example, less than 50V, the p-type post 4 and N-type post 3 of device consume completely
To the greatest extent, if p-type post 4 and N-type post 3 realize preferably balance on each lateral attitude, (N-type impurity amount is equal to p type impurity
Amount), then the distribution of the electric-field intensity of N-type drift region as shown in Fig. 2 N-type drift region by positioned at 1 direct N of source region 8 and drain region
Type epitaxial layer forms, including N-type post 3 and the N-type cushion 30 of bottom, corresponding to the interface M1M2 in Fig. 1 and interface B1B2 it
Between N-type epitaxy layer.With Vds increase, electric-field intensity is continuously increased, until the electric-field intensity of maximum reaches Ec, now device
Avalanche breakdown occurs for part, and Vds now is exactly the breakdown voltage BVds of device.
Because the p-type post 4 and N-type post 3 that under very low Vds, are alternately arranged occur quickly in the presence of transverse electric field
Exhaust, it is very big non-linear that the electric capacity Crss of device is that Cgd has under small Vds, and Crss is reverse transfer capacitance, and size is
Cgd；It is superjunction of the stepping less than 12 microns of p-type post 4 and N-type post 3 for N-P posts, typically changes to 20V from 0 volt in Vds
When, the Crss of device has a process drastically declined so that super node MOSFET is in switching process, it is prone to due to
Crss is too low and causes switching process too fast, so that the application system electromagnetic interference of device is big, or even due to electric current and electricity
The overshoot of pressure and cause circuit malfunction, cause description is as follows：In device from during conducting state becomes reverse blocking state,
Due to adjacent p-type post 4 and the carry out having lateral depletion of N-type post 3, and by the part or all of consumption completely of N-type post 3 under a certain voltage
To the greatest extent, because Cgd is Cox and Csi series connection, Csi can become very little, institute after the carry out having lateral depletion of adjacent p-type post 4 and N-type post 3
Become very small with the Cgd of now device, due to dVds/dt=Igp/Cgd (Vds), wherein Vds is drain-source voltage, and Igp is flat
Grid current during platform voltage, at this voltage dVds/dt can become very large, so as to cause the circuit or system using device
There is good electromagnetic interference, influence the normal work of circuit and system；This case is just from high pressure reverse blocking state to leading
Equally existed in the change procedure of logical state.This too high dVds/dt in switching process, except causing the loop in applying
Concussion, it is also possible to cause the excessive electric current and voltage overshoot of application system, cause circuit to damage.
On the other hand, it is most of in the circuit of reality for a high tension apparatus, such as BVds 600V device
Turn-off time in, Vds voltage is or lower less than 500V, particularly in bridge circuit or some other circuits, at certain
MOSFET S/D is to form parasitism two between the i.e. described p-type trap 7 of body diode parasitic between source and drain and drift region under individual state
Pole pipe can carry out forward conduction, a Reverse recovery (reverse recovery) occur afterwards, voltage reaches Vdd between DS
When (be usually no more than 400V), the electric current of diode reaches maximum reverse value of current (Irrm), carries out Reverse recovery afterwards,
The concussion of electric current and voltage in reduction circuit is wished during Reverse recovery, it would be desirable to which the reverse current recovery process of device is got over
It is soft better, it is good to obtain the softness factor, it is necessary to have more carriers remaining in N-type drift region.But in existing structure due to
Carrier when Vds is less than 50V in N-P posts is just completely depleted, therefore even if operating voltage Vdd it is small to 200V V~
300V, the portion among carrier remaining after device voltage reaches Vdd also only has the part N-type cushion 30 under N-P posts
Divide carrier, so as to which softness factor during device body diode reverse recovery cannot be improved.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of superjunction devices, can improve gate leakage capacitance and gate leakage capacitance
Minimum value, so as to effectively reduce electromagnetic interference performance of the device in application circuit and effectively reduce device in application electricity
The electric current and the overshoot of voltage brought in road, moreover it is possible to increase the softness factor of the Reverse recovery of device.Therefore, the present invention also provides
A kind of manufacture method of superjunction devices.
In order to solve the above technical problems, the electric charge flow region of superjunction devices provided by the invention includes being alternately arranged by multiple
N-type post and p-type post composition super-junction structure；Each N-type post and its neighbouring described p-type post form a superjunction list
Member.
There is N-type electric field barrier layer, the N-type electric field blocks in the p-type post of the superjunction unit of at least more than one
The p-type post is divided into the first p-type post at the top of the N-type electric field barrier layer and positioned at the N-type by layer in the vertical
Second p-type post of electric field barrier layer bottom.
The first p-type post and the adjacent N-type post are alternately arranged composition top super-junction structure；The second p-type post and
The adjacent N-type post is alternately arranged composition bottom super-junction structure；The N-type electric field barrier layer is used to realize the top superjunction knot
The segmentation of structure and the bottom super-junction structure exhausts.
When the source-drain voltage of superjunction devices is less than or equal to first voltage value, only described top super-junction structure exhausts,
Electric field is terminated in the N-type electric field barrier layer, and the bottom super-junction structure does not exhaust.
When the source-drain voltage of superjunction devices is more than the first voltage value, the top super-junction structure is completely depleted, electricity
Continue to exhaust the bottom super-junction structure after the N-type electric field barrier layer in field.
The first voltage value requirement is more than or equal to the operating voltage of the superjunction devices and less than the superjunction devices
Breakdown voltage, make the superjunction devices that exhausting for the top super-junction structure only occur at work, so as to improve grid leak electricity
The characteristics of holding, while not exhausted using the bottom super-junction structure can provide carrier in device Reverse recovery, so as to
Increase the softness factor of the Reverse recovery of device；The breakdown voltage of the superjunction devices is by the top super-junction structure and the bottom
The depletion region that portion's super-junction structure is formed when all completely depleted determines.
Further improve is that the first voltage value is determined by the voltage endurance capability of the top super-junction structure, the top
The more big first voltage value of the voltage endurance capability of portion's super-junction structure is bigger, and the voltage endurance capability of the top super-junction structure is smaller described
First voltage value is smaller.
Further improve is that the thickness of the top super-junction structure is smaller, and the first voltage value is smaller.
Further improve is that the thickness of the bottom super-junction structure is bigger, the Reverse recovery of the superjunction devices it is soft
Degree is bigger.
Further improve is charge balance between the first p-type post and the adjacent N-type post.
Charge balance between the second p-type post and the adjacent N-type post；Or the total impurities of the second p-type post
More than the total impurities of the adjoining N-type post；Or the total impurities of the second p-type post are less than the miscellaneous of the adjacent N-type post
Matter total amount.
Further improve is that the doping concentration of the N-type electric field barrier layer is the first p-type post and the 2nd P
2 times~10 times of the maximum doping concentration of doping concentration in type post.
Further improve is that the thickness of the N-type electric field barrier layer is 1 micron~5 microns.
Further improve is that the both sides of the N-type electric field barrier layer and the N-type post connect corresponding to each p-type post
Touch, and the width of each N-type electric field barrier layer is more than or equal to the width of the corresponding first p-type post and the second p-type post
Degree；Or respectively to connect into one whole for the N-type electric field barrier layer of each superjunction unit with the N-type electric field barrier layer
Body.
Further improve is that the thickness of the first p-type post is more than the thickness of the second p-type post.
Further improve is that the thickness of the second p-type post is 2 microns~20 microns；The second p-type post by from
Son injection is diffuseed to form, or the second p-type post is formed by trench fill.
Further improve is that the super-junction structure is formed in N-type epitaxy layer, is formed in the bottom of the super-junction structure
By the N-type cushion being made up of N-type epitaxy layer, the N-type semiconductor substrate in the bottom of the N-type cushion for heavy doping.
In order to solve the above technical problems, the electric charge of superjunction devices flows in the manufacture method of superjunction devices provided by the invention
Area includes the super-junction structure being made up of multiple N-type posts being alternately arranged and p-type post；Each N-type post and its neighbouring described P
Type post forms a superjunction unit；There is N-type electric field barrier layer in the p-type post of the superjunction unit of at least more than one, have
The forming step for having the superjunction unit of the N-type electric field barrier layer includes：
Step 1: providing N-type epitaxy layer, groove, the ditch are formed in the N-type epitaxy layer using lithographic etch process
The depth of groove is identical with the depth of the first p-type post.
Step 2: carry out first time p-type ion implanting forms the second p-type post in the channel bottom；Carry out second of N-type
Ion implanting forms N-type electric field barrier layer in the channel bottom, and the N-type electric field barrier layer is located at the second p-type post
Top.
Step 3: filling P-type silicon in the trench forms the first p-type post；By the first p-type post and the 2nd P
Longitudinally superposition forms the p-type post split by the N-type electric field barrier layer to type post；The N-type post is by between each p-type post
The N-type epitaxy layer composition.
The first p-type post and the adjacent N-type post are alternately arranged composition top super-junction structure；The second p-type post and
The adjacent N-type post is alternately arranged composition bottom super-junction structure；The N-type electric field barrier layer is used to realize the top superjunction knot
The segmentation of structure and the bottom super-junction structure exhausts.
When the source-drain voltage of superjunction devices is less than or equal to first voltage value, only described top super-junction structure exhausts,
Electric field is terminated in the N-type electric field barrier layer, and the bottom super-junction structure does not exhaust.
When the source-drain voltage of superjunction devices is more than the first voltage value, the top super-junction structure is completely depleted, electricity
Continue to exhaust the bottom super-junction structure after the N-type electric field barrier layer in field.
The first voltage value requirement is more than or equal to the operating voltage of the superjunction devices and less than the superjunction devices
Breakdown voltage, make the superjunction devices that exhausting for the top super-junction structure only occur at work, so as to improve grid leak electricity
The characteristics of holding, while not exhausted using the bottom super-junction structure can provide carrier in device Reverse recovery, so as to
Increase the softness factor of the Reverse recovery of device；The breakdown voltage of the superjunction devices is by the top super-junction structure and the bottom
The depletion region that portion's super-junction structure is formed when all completely depleted determines.
In order to solve the above technical problems, the electric charge of superjunction devices flows in the manufacture method of superjunction devices provided by the invention
Area includes the super-junction structure being made up of multiple N-type posts being alternately arranged and p-type post；Each N-type post and its neighbouring described P
Type post forms a superjunction unit；There is N-type electric field barrier layer in the p-type post of the superjunction unit of at least more than one, have
The forming step for having the superjunction unit of the N-type electric field barrier layer includes：
Step 1: provide the first N-type epitaxy layer, photoetching and p-type ion implanting are carried out the in first N-type epitaxy layer
One layer of p type island region, first layer N-type region is formed by first N-type epitaxy layer between the first layer p type island region.
Step 2: the second intrinsic epitaxial layer is formed in first N-type epitaxy layer；Carry out photoetching and p-type ion implanting
The second layer p type island region on the second intrinsic epitaxial layer, photoetching and N-type ion implanting are carried out on the second intrinsic epitaxial layer
Second layer N-type region；The second layer p type island region is superimposed upon on first p type island region, and second N-type region is superimposed upon the first N
Type area.
Step 3: p type island region and the N-type region of the formation more layers of repeat step two, each layer p type island region are superimposed to form the second p-type
Post, each layer N-type region are also superimposed；Repeat step two is 0 time or more than 1 time, until the thickness of the second p-type post reaches
It is required that.
Step 4: N-type electric field barrier layer is formed at the top of the second p-type post using photoetching and N-type ion implanting.
Step 5: carrying out outer layer growth forms the 3rd N-type epitaxy layer；Using lithographic etch process in the 3rd N-type
Groove is formed in epitaxial layer, the N-type electric field barrier layer is exposed in the bottom of the groove；P-type silicon is filled in the trench
Form the first p-type post；By the first p-type post and the second p-type post, longitudinally superposition is formed by the N-type electric field barrier layer point
The p-type post cut；The N-type post is superimposed and formed by each layer N-type region and the 3rd N-type epitaxy layer between each p-type post.
The first p-type post and the adjacent N-type post are alternately arranged composition top super-junction structure；The second p-type post and
The adjacent N-type post is alternately arranged composition bottom super-junction structure；The N-type electric field barrier layer is used to realize the top superjunction knot
The segmentation of structure and the bottom super-junction structure exhausts.
When the source-drain voltage of superjunction devices is less than or equal to first voltage value, only described top super-junction structure exhausts,
Electric field is terminated in the N-type electric field barrier layer, and the bottom super-junction structure does not exhaust.
When the source-drain voltage of superjunction devices is more than the first voltage value, the top super-junction structure is completely depleted, electricity
Continue to exhaust the bottom super-junction structure after the N-type electric field barrier layer in field.
The first voltage value requirement is more than or equal to the operating voltage of the superjunction devices and less than the superjunction devices
Breakdown voltage, make the superjunction devices that exhausting for the top super-junction structure only occur at work, so as to improve grid leak electricity
The characteristics of holding, while not exhausted using the bottom super-junction structure can provide carrier in device Reverse recovery, so as to
Increase the softness factor of the Reverse recovery of device；The breakdown voltage of the superjunction devices is by the top super-junction structure and the bottom
The depletion region that portion's super-junction structure is formed when all completely depleted determines.
In order to solve the above technical problems, in the manufacture method of superjunction devices provided by the invention, the electric charge stream of superjunction devices
Dynamic area includes the super-junction structure being made up of multiple N-type posts being alternately arranged and p-type post；Each N-type post and its neighbouring institute
State p-type post and form a superjunction unit；There is N-type electric field barrier layer in the p-type post of the superjunction unit of at least more than one,
The forming step of the superjunction unit with the N-type electric field barrier layer includes：
Step 1: provide the first N-type epitaxy layer；Is formed in first N-type epitaxy layer using lithographic etch process
One groove；P-type silicon is filled in the first groove and forms the second p-type post.
Step 2: carrying out outer layer growth forms the second N-type epitaxy layer；Using lithographic etch process in second N-type
Form second groove in epitaxial layer, the second p-type post of the second groove alignment bottom and by the second p-type post surface
Expose.
Carry out N-type ion implanting and form N-type electric field barrier layer, the N-type electric field barrier layer in the second groove bottom
Positioned at the top of the second p-type post.
Step 3: P-type silicon is filled in the second groove forms the first p-type post；By the first p-type post and described
Longitudinally superposition forms the p-type post split by the N-type electric field barrier layer to two p-type posts；The N-type post is by each p-type post
Between first N-type epitaxy layer and second N-type epitaxy layer be superimposed to be formed.
The first p-type post and the adjacent N-type post are alternately arranged composition top super-junction structure；The second p-type post and
The adjacent N-type post is alternately arranged composition bottom super-junction structure；The N-type electric field barrier layer is used to realize the top superjunction knot
The segmentation of structure and the bottom super-junction structure exhausts.
When the source-drain voltage of superjunction devices is less than or equal to first voltage value, only described top super-junction structure exhausts,
Electric field is terminated in the N-type electric field barrier layer, and the bottom super-junction structure does not exhaust.
When the source-drain voltage of superjunction devices is more than the first voltage value, the top super-junction structure is completely depleted, electricity
Continue to exhaust the bottom super-junction structure after the N-type electric field barrier layer in field.
The first voltage value requirement is more than or equal to the operating voltage of the superjunction devices and less than the superjunction devices
Breakdown voltage, make the superjunction devices that exhausting for the top super-junction structure only occur at work, so as to improve grid leak electricity
The characteristics of holding, while not exhausted using the bottom super-junction structure can provide carrier in device Reverse recovery, so as to
Increase the softness factor of the Reverse recovery of device；The breakdown voltage of the superjunction devices is by the top super-junction structure and the bottom
The depletion region that portion's super-junction structure is formed when all completely depleted determines.
In order to solve the above technical problems, the electric charge of superjunction devices flows in the manufacture method of superjunction devices provided by the invention
Area includes the super-junction structure being made up of multiple N-type posts being alternately arranged and p-type post；Each N-type post and its neighbouring described P
Type post forms a superjunction unit；There is N-type electric field barrier layer in the p-type post of the superjunction unit of at least more than one, have
The forming step for having the superjunction unit of the N-type electric field barrier layer includes：
Step 1: provide the first N-type epitaxy layer；Is formed in first N-type epitaxy layer using lithographic etch process
One groove；P-type silicon is filled in the first groove and forms the second p-type post；N-type ion implanting is carried out in the second p-type post
Top formed N-type electric field barrier layer.
Step 2: carrying out outer layer growth forms the second N-type epitaxy layer；Using lithographic etch process in second N-type
Form second groove in epitaxial layer, the second p-type post of the second groove alignment bottom and by the N-type electric field barrier layer
Expose.
Step 3: P-type silicon is filled in the second groove forms the first p-type post；By the first p-type post and described
Longitudinally superposition forms the p-type post split by the N-type electric field barrier layer to two p-type posts；The N-type post is by each p-type post
Between first N-type epitaxy layer and second N-type epitaxy layer be superimposed to be formed；
The first p-type post and the adjacent N-type post are alternately arranged composition top super-junction structure；The second p-type post and
The adjacent N-type post is alternately arranged composition bottom super-junction structure；The N-type electric field barrier layer is used to realize the top superjunction knot
The segmentation of structure and the bottom super-junction structure exhausts.
When the source-drain voltage of superjunction devices is less than or equal to first voltage value, only described top super-junction structure exhausts,
Electric field is terminated in the N-type electric field barrier layer, and the bottom super-junction structure does not exhaust.
When the source-drain voltage of superjunction devices is more than the first voltage value, the top super-junction structure is completely depleted, electricity
Continue to exhaust the bottom super-junction structure after the N-type electric field barrier layer in field.
The first voltage value requirement is more than or equal to the operating voltage of the superjunction devices and less than the superjunction devices
Breakdown voltage, make the superjunction devices that exhausting for the top super-junction structure only occur at work, so as to improve grid leak electricity
The characteristics of holding, while not exhausted using the bottom super-junction structure can provide carrier in device Reverse recovery, so as to
Increase the softness factor of the Reverse recovery of device；The breakdown voltage of the superjunction devices is by the top super-junction structure and the bottom
The depletion region that portion's super-junction structure is formed when all completely depleted determines.
The present invention can obtain following beneficial effect：
The present invention by increase N-type electric field barrier layer to p-type post carry out it is longitudinally split, can realize it is longitudinally split after top
The segmentation of portion's super-junction structure and bottom super-junction structure exhausts, and when the source-drain voltage of superjunction devices is more than first voltage value, bottom surpasses
Junction structure can start to exhaust, and only top super-junction structure is exhausted during less than or equal to first voltage value, and first voltage value is wanted
The operating voltage more than or equal to superjunction devices and the breakdown voltage less than superjunction devices are asked, so superjunction devices can be made to work
When top super-junction structure only occur exhaust, so as to improve gate leakage capacitance, so as to can also improve the minimum value of gate leakage capacitance, so as to
Electromagnetic interference performance and the effective electricity that reduces device in application circuit bring of the device in application circuit can effectively be reduced
The overshoot of stream and voltage.
The characteristics of bottom super-junction structure does not exhaust at work using superjunction devices simultaneously, makes bottom super-junction structure exist
Carrier is provided during device Reverse recovery, so can be in Reverse recovery so as to increase the softness factor of the Reverse recovery of device
During wish reduce circuit in electric current and voltage concussion.
In addition, when the breakdown voltage of superjunction devices of the present invention is by top super-junction structure and all completely depleted bottom super-junction structure
The depletion region of formation determines, is compared with existing structure, the breakdown voltage of superjunction devices of the present invention can be kept well.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is the schematic diagram of existing superjunction devices；
Fig. 2 is the electric-field intensity distribution schematic diagram of the drift region of existing superjunction devices；
Fig. 3 is the schematic diagram of the superjunction devices of the embodiment of the present invention one；
Fig. 4 A are drift region of the superjunction devices of the embodiment of the present invention one when source-drain voltage is less than or equal to first voltage value
Electric-field intensity distribution schematic diagram；
Fig. 4 B are the electric fields of drift region of the superjunction devices of the embodiment of the present invention one when source-drain voltage is more than first voltage value
Intensity distribution schematic diagram；
Fig. 4 C are the electric fields of drift region of the superjunction devices of the embodiment of the present invention two when source-drain voltage is more than first voltage value
Intensity distribution schematic diagram；
Fig. 4 D are the electric fields of drift region of the superjunction devices of the embodiment of the present invention three when source-drain voltage is more than first voltage value
Intensity distribution schematic diagram；
Fig. 4 E are the gate leakage capacitance curves of the superjunction devices of the embodiment of the present invention one and as existing super shown in the Fig. 1 compared
The gate leakage capacitance curve of junction device；
Fig. 5 is the schematic diagram of the superjunction devices of the embodiment of the present invention four；
Fig. 6 is the schematic diagram of the superjunction devices of the embodiment of the present invention five；
Fig. 7 is the schematic diagram of the superjunction devices of the embodiment of the present invention six.
Embodiment
The superjunction devices of the embodiment of the present invention one：
As shown in figure 3, it is the schematic diagram of the superjunction devices of the embodiment of the present invention one；In the embodiment of the present invention one：
Electric charge flow region includes the super-junction structure being made up of multiple N-type posts 3 being alternately arranged and p-type post；Each N-type
Post 3 and its neighbouring described p-type post form a superjunction unit.
The super-junction structure is formed in N-type epitaxy layer, in the bottom of the super-junction structure formed with by N-type epitaxy layer group
Into N-type cushion 30, the bottom of the N-type cushion 30 be heavy doping N-type semiconductor substrate 1.
There is N-type electric field barrier layer 31 in the p-type post of the superjunction unit of at least more than one, shown in Fig. 3 all
The p-type post in all include N-type electric field barrier layer 31.The N-type electric field barrier layer 31 divides the p-type post in the vertical
It is cut into the first p-type post 41 positioned at the top of the N-type electric field barrier layer 31 and the positioned at the bottom of N-type electric field barrier layer 31
Two p-type posts 42.
The first p-type post 41 and the adjacent N-type post 3 are alternately arranged composition top super-junction structure；The second p-type post
42 are alternately arranged composition bottom super-junction structure with the adjacent N-type post 3.
In Fig. 3, interface M1M2 be whole super-junction structure top surface namely top super-junction structure top surface, interface
D1D2 is the lower surface of top super-junction structure, and interface E1E2 is the top surface of bottom super-junction structure, and interface A 1A2 is bottom
The lower surface of the lower surface of super-junction structure namely whole super-junction structure, interface C 1C2 are the Semiconductor substrate 1 after being thinned
Lower surface, interface B1B2 are the top surface of Semiconductor substrate 1.After thickness between interface C 1C2 and interface B1B2 is thinned
The thickness of Semiconductor substrate 1 be T00, the thickness between interface A 1A2 and interface B1B2 is the thickness of the N-type cushion 30
For T30, the thickness between interface A 1A2 and interface M1M2 is T20, and the thickness between interface D1D2 and interface M1M2 is T201.Boundary
It is top super-junction structure region between face M1M2 to interface D1D2, is the N-type electric field resistance between interface D1D2 to interface E1E2
The region of tomography 31, it is bottom super-junction structure region between interface E1E2 to interface A 1A2.
The N-type electric field barrier layer 31 is used for the segmentation consumption for realizing the top super-junction structure and the bottom super-junction structure
To the greatest extent.Preferably selection is that the doping concentration of the N-type electric field barrier layer 31 is the first p-type post 41 and the second p-type post 42
2 times~10 times of the maximum doping concentration of middle doping concentration.The thickness of the N-type electric field barrier layer 31 is 1 micron~5 microns.
The both sides of the N-type electric field barrier layer 31 and the N-type post 3 contact corresponding to each p-type post, and each N-type electric field resistance
The width of tomography 31 is more than or equal to the width of the corresponding first p-type post 41 and the second p-type post 42.
The thickness of the first p-type post 41 is more than the thickness of the second p-type post 42.Preferably, the second p-type post 42
Thickness be 2 microns~20 microns；The second p-type post 42 is by ion implanting or diffuses to form.The present invention shown in Fig. 3 is real
Apply in example one, formed by trench fill process during the first p-type post 41, the N-type electric field barrier layer 31 and the 2nd P
Type post 42 is all to be formed after groove corresponding to the first p-type post 41 is formed by ion implanting.
In the embodiment of the present invention one, charge balance between the first p-type post 41 and the adjacent N-type post 3, charge balance
The total impurities looked like between the first p-type post 41 and the adjacent N-type post 3 are identical.The impurity of the second p-type post 42
Total amount is more than the total impurities of the adjacent N-type post 3.
When the source-drain voltage of superjunction devices is less than or equal to first voltage value, only described top super-junction structure exhausts,
Electric field is terminated in the N-type electric field barrier layer 31, and the bottom super-junction structure does not exhaust.If Fig. 4 A are shown, this hairs
The electric-field intensity distribution schematic diagram of drift region of the bright superjunction devices of embodiment one when source-drain voltage is less than or equal to first voltage value,
The gradual increases of wherein source-drain voltage Vds1, Vds2, Vds3 and Vds4 and both less than first voltage value, it can be seen that electric field only position
Between interface M1M2 and D1D2, namely only top super-junction structure exhausts, and electric field can't pass through the N-type electric field to hinder
Tomography 31 and enter in the super-junction structure of bottom, so the bottom super-junction structure does not exhaust.
When the source-drain voltage of superjunction devices is more than the first voltage value, the top super-junction structure is completely depleted, electricity
Continue to exhaust the bottom super-junction structure after the N-type electric field barrier layer 31 in field.As shown in Figure 4 B, it is implementation of the present invention
The electric-field intensity distribution schematic diagram of drift region of the superjunction devices of example one when source-drain voltage is more than first voltage value, due to the present invention
The total impurities of second p-type post 42 described in embodiment one are set greater than abutting the total impurities of the N-type post 3, electric-field strength
Degree can decline in the N-type electric field barrier layer 31, through the N-type electric field barrier layer 31 after in interface E1E2 to interface A 1A2
Between can rise between the super-junction structure region of bottom, finally drop to 0 in the N-type cushion 30；It should be noted that
The amplitude that electric-field intensity increases between the super-junction structure region of bottom needs to control, and not cause the electric-field intensity of maximum to occur
Between E1E2 to A1A2, the EAS abilities extremely uniformity of device otherwise can be influenceed.
The first voltage value requirement is more than or equal to the operating voltage of the superjunction devices and less than the superjunction devices
Breakdown voltage, make the superjunction devices that exhausting for the top super-junction structure only occur at work, so as to improve grid leak electricity
Appearance is Cgd, while can provide carrier in device Reverse recovery the characteristics of do not exhausted using the bottom super-junction structure,
So as to increase the softness factor of the Reverse recovery of device；The breakdown voltage of the superjunction devices is by the top super-junction structure and institute
State bottom super-junction structure it is all completely depleted when the depletion region that is formed determine.
The first voltage value determines by the voltage endurance capability of the top super-junction structure, the top super-junction structure it is pressure-resistant
The more big first voltage value of ability is bigger, and the smaller first voltage value of voltage endurance capability of the top super-junction structure is smaller.
The thickness of the top super-junction structure is smaller, and the first voltage value is smaller, namely by adjusting the top super-junction structure
Thickness can adjust the first voltage value, can so improve the flexibility of design.The thickness of the bottom super-junction structure is bigger,
The softness of the Reverse recovery of the superjunction devices is bigger.
Illustrate the embodiment of the present invention one in order to clearer, below the N-type super node MOSFET device using breakdown voltage as 600V
The superjunction devices of the embodiment of the present invention one is described further exemplified by part and with reference to design parameter：
The Semiconductor substrate 1 is silicon substrate, and silicon substrate 1 is high concentration substrate, the ohmcm of resistivity 0.001~
0.003 ohmcm, the thickness T00 after silicon substrate 1 is thinned is 60 microns~160 microns.The resistivity of N-type epitaxy layer is 1
The ohmcm of ohmcm~2, preferably, the resistivity of N-type epitaxy layer is 1.5 ohmcms, 1.5 ohmcms
N-type impurity concentration corresponding to the resistivity of size is 3.13e15cm-3, whole N-type epitaxy layer includes super-junction structure and described
The thickness of the whole N-type epitaxy layer of N-type cushion 30 is 50 microns；N-type cushion 30 and N-type post 3 are all directly by N-type extension
Layer composition, therefore the resistivity of N-type cushion 30 and N-type post 3 is all identical with N-type epitaxy layer, the thickness T30 of N-type cushion 30
For 5 microns~20 microns；N-type post width is 5.5 microns, and the width of p-type post is 4.5 microns；The thickness of first p-type post 41 is 30
Micron~40 microns；Further, the thickness of the N-type electric field barrier layer 31 is 1 micron~2 microns, it is desirable to is ensured in relatively low electricity
Depressing the N-type carrier in the region will not be completely depleted；Further, the thickness of the second p-type post 42 is 2 microns~5 micro-
Rice.
N-type super-junction MOSFET device also includes the primitive cell structure being formed in each superjunction unit, and primitive cell structure includes：
At the top of p-type post formed with p-type trap 7, in p-type trap 7 formed with N+ district's groups into source region 8 with by P+ district's groups into
P-well draw-out area 9, on the surface of p-type trap 7 formed with gate dielectric layer such as gate oxide 5 and polysilicon gate 6.
Interlayer film 10, contact hole 11, front metal layer 12, source electrode and grid is drawn respectively after front metal layer 12 is graphical
Pole.Drain region is directly made up of the Semiconductor substrate 1 of the heavy doping after being thinned or further adulterates and form, in Semiconductor substrate 1
Drain electrode is drawn formed with metal layer on back 13, metal layer on back 13 in the back side.
The drift region of device is made up of the N-type post 3 between p-type trap 7 and drain region 1 and N-type cushion 30, p-type trap 7 and drift
Parasitic body diode can be formed between area.
Because the breakdown voltage of the superjunction devices of the embodiment of the present invention one is by the top super-junction structure and the bottom superjunction
The depletion region formed when structure is all completely depleted determines, compared with prior art, the embodiment of the present invention is a kind of to increase the N-type
Electric field barrier layer 31 influences very little to the BVds of device, will not become substantially, so the embodiment of the present invention one can be realized well
600V breakdown voltage.For the superjunction devices that BVds is 600V, its operating voltage be generally less than 500V or less than 0.8 ×
BVds, namely when device it is in running order when, the Vds of device is less than 500V or 0.8 × BVds, at this moment, only pushes up
Portion's super-junction structure exhausts and part depletion can occur for the N-type electric field barrier layer 31, and this is a key for influenceing Cgd
Parameter, the thickness of depletion layer reduce, therefore the Cgd of device can improve relative to prior art, are described as follows in conjunction with Fig. 4 E：
As shown in Figure 4 E, curve 102 is the gate leakage capacitance curve of the superjunction devices of the embodiment of the present invention one, and curve 101 is as comparing
The gate leakage capacitance curve of existing superjunction devices shown in Fig. 1, it can be seen that be less than the first electricity in relatively low source-drain voltage Vds
Under conditions of pressure value, the Cgd corresponding to curve 102 is both greater than the Cgd of curve 101, and Cgd minimum value is Cgd2 in curve 102,
Cgd minimum value is Cgd1 in curve 101, it is known that Cgd2 is greater than Cgd1, so the embodiment of the present invention one can make superjunction devices
Exhausting for top super-junction structure only occurs at work, so as to improve gate leakage capacitance, so as to can also improve the minimum of gate leakage capacitance
Value, so as to effectively reduce electromagnetic interference performance and effective reduction device in application circuit band of the device in application circuit
The electric current and the overshoot of voltage come.When source-drain voltage continues to increase so that the first p-type post 41 and the second p-type post 42 all consume
When to the greatest extent, curve 101 and curve 102 are just ended in agreement.
Further, since the superjunction devices of the embodiment of the present invention one, when Vds is less than 500V, only top super-junction structure consumes
To the greatest extent and N-type electric field barrier layer 31 has part to exhaust, therefore in the reversely restoring process of parasitic body diode, in circuit
Working power Vdd be typically smaller than 480V, when the Vds of device reaches Vdd, bottom super-junction structure in device is also without consuming
To the greatest extent, therefore relative to prior art, it is in device to remain the hole not exhausted and electronics more, so that device Reverse recovery
Softness increase, improve the reverse recovery characteristic of device.
The superjunction devices of the embodiment of the present invention two：
It is that the present invention is implemented in place of the difference of the superjunction devices of the embodiment of the present invention two and the superjunction devices of the embodiment of the present invention one
Charge balance between the second p-type post 42 and the adjacent N-type post 3 in the superjunction devices of example two, i.e., described second p-type post 42
It is equal with the total impurities of the adjoining N-type post 3.This causes the superjunction devices of the embodiment of the present invention two to be more than first in source-drain voltage
The electric-field intensity distribution of drift region during magnitude of voltage and the difference of the embodiment of the present invention one, it is implementation of the present invention as shown in Figure 4 C
The electric-field intensity distribution schematic diagram of drift region of the superjunction devices of example two when source-drain voltage is more than first voltage value；Electric-field intensity exists
Can decline in the N-type electric field barrier layer 31, through the N-type electric field barrier layer 31 after interface E1E2 to interface A 1A2
It can keep being basically unchanged between bottom super-junction structure region, so ensure that the maximum field intensity in this section of region surpasses less than top
Maximum field intensity in junction structure, so that avalanche breakdown occurs in the super-junction structure of top, the EAS abilities of device are not influenceed
And its consistency；Electric-field intensity finally drops to 0 in the N-type cushion 30.
The superjunction devices of the embodiment of the present invention three：
It is that the present invention is implemented in place of the difference of the superjunction devices of the embodiment of the present invention three and the superjunction devices of the embodiment of the present invention one
The total impurities of the second p-type post 42 in the superjunction devices of example three are less than the total impurities of the adjacent N-type post 3.This causes
The electric-field intensity distribution and Ben Fa of drift region of the superjunction devices of the embodiment of the present invention three when source-drain voltage is more than first voltage value
The difference of bright embodiment one, it is that the superjunction devices of the embodiment of the present invention three is more than first voltage value in source-drain voltage as shown in Figure 4 D
When drift region electric-field intensity distribution schematic diagram；Electric-field intensity can decline in the N-type electric field barrier layer 31, electric-field intensity
After through the N-type electric field barrier layer 31 interface E1E2 to interface A 1A2 be bottom super-junction structure region between can be progressively
Diminish, so ensure that the maximum field intensity in this section of region is less than maximum field intensity in the super-junction structure of top, so that snow
Collapse breakdown to occur in the super-junction structure of top, do not influence the EAS abilities and its consistency of device；Electric-field intensity is finally in the N
Drop to 0 in type cushion 30.
The superjunction devices of the embodiment of the present invention four：
As shown in figure 5, it is the schematic diagram of the superjunction devices of the embodiment of the present invention four；The superjunction devices of the embodiment of the present invention four and sheet
It is that there is following feature in the superjunction devices of the embodiment of the present invention four in place of the difference of the superjunction devices of inventive embodiments one：Described
Two p-type posts 42 add ion implanting to be formed by multiple extension, can so increase the thickness of the second p-type post 42.With this hair
The bright superjunction devices of embodiment one is compared, if under conditions of the gross thickness of super-junction structure keeps constant, the embodiment of the present invention four
The thickness of thickness the second p-type post 42 of the first p-type post 41 of superjunction devices can be bigger, so that described
It is that first voltage value can be smaller that N-type electric field barrier layer 31 can produce electric field blocking effect under lower Vds, and causes device
Reverse recovery characteristic is further improved, and expands the flexibility of device design.
The superjunction devices of the embodiment of the present invention five：
As shown in fig. 6, it is the schematic diagram of the superjunction devices of the embodiment of the present invention five；The superjunction devices of the embodiment of the present invention five and sheet
It is that there is following feature in the superjunction devices of the embodiment of the present invention five in place of the difference of the superjunction devices of inventive embodiments one：Described
Two p-type posts 43 are formed by trench fill P-type silicon, individually represent the second p-type post of trench fill with mark 43 here.This
The thickness of the second p-type post 43 of inventive embodiments five can adjust, and can expand the flexibility of device design.
The superjunction devices of the embodiment of the present invention six：
As shown in fig. 7, it is the schematic diagram of the superjunction devices of the embodiment of the present invention six；The superjunction devices of the embodiment of the present invention six and sheet
It is that there is following feature in the superjunction devices of the embodiment of the present invention six in place of the difference of the superjunction devices of inventive embodiments five：Respectively have
The N-type electric field barrier layer 31 of each superjunction unit of the N-type electric field barrier layer 31 connects integral.It is if whole
All super elements of electric charge flow region all have the N-type electric field barrier layer 31, then the N-type electric field barrier layer 31 can run through
Whole electric charge flow region.The dimension enlargement of the N-type electric field barrier layer 31 can further increase electric field blocking effect, improve device
The reverse recovery characteristic of part, so as to further expand the flexibility of device design.
The manufacture method of the superjunction devices of the embodiment of the present invention one：
The manufacture method of the superjunction devices of the embodiment of the present invention one is used to manufacture the superjunction of the embodiment of the present invention one as shown in Figure 3
Device, the electric charge flow region of superjunction devices include the super-junction structure being made up of multiple N-type posts 3 being alternately arranged and p-type post；It is each
The N-type post 3 and its neighbouring described p-type post form a superjunction unit；The p-type of the superjunction unit of at least more than one
There is N-type electric field barrier layer 31, the forming step with the superjunction unit of the N-type electric field barrier layer 31 includes in post：
Step 1: providing N-type epitaxy layer, N-type epitaxy layer is formed at Semiconductor substrate 1.Using lithographic etch process in institute
State and groove is formed in N-type epitaxy layer, the depth of the groove is identical with the depth of the first p-type post 41.
Step 2: carry out first time p-type ion implanting forms the second p-type post 42 in the channel bottom；Carry out second of N
Type ion implanting forms N-type electric field barrier layer 31 in the channel bottom, and the N-type electric field barrier layer 31 is located at the 2nd P
The top of type post 42.
Preferably, after the completion of ion implanting twice, groove cleaning can be carried out, sacrificial oxide layer is formed and removes sacrifice
The technique of oxide layer.
Step 3: filling P-type silicon in the trench forms the first p-type post 41；By the first p-type post 41 and described
The superposition of the longitudinal direction of two p-type post 42 forms the p-type post split by the N-type electric field barrier layer 31；The N-type post 3 is by each P
N-type epitaxy layer composition between type post.
The first p-type post 41 and the adjacent N-type post 3 are alternately arranged composition top super-junction structure；The second p-type post
42 are alternately arranged composition bottom super-junction structure with the adjacent N-type post 3；The N-type electric field barrier layer 31 is used to realize the top
The segmentation of portion's super-junction structure and the bottom super-junction structure exhausts.
When the source-drain voltage of superjunction devices is less than or equal to first voltage value, only described top super-junction structure exhausts,
Electric field is terminated in the N-type electric field barrier layer 31, and the bottom super-junction structure does not exhaust.
When the source-drain voltage of superjunction devices is more than the first voltage value, the top super-junction structure is completely depleted, electricity
Continue to exhaust the bottom super-junction structure after the N-type electric field barrier layer 31 in field.
The first voltage value requirement is more than or equal to the operating voltage of the superjunction devices and less than the superjunction devices
Breakdown voltage, make the superjunction devices that exhausting for the top super-junction structure only occur at work, so as to improve grid leak electricity
The characteristics of holding, while not exhausted using the bottom super-junction structure can provide carrier in device Reverse recovery, so as to
Increase the softness factor of the Reverse recovery of device；The breakdown voltage of the superjunction devices is by the top super-junction structure and the bottom
The depletion region that portion's super-junction structure is formed when all completely depleted determines.
So that the superjunction devices is N-type super-junction MOSFET device as an example, also comprise the following steps：
Step 4: it is p-type trap 7 that photoetching and ion implanting and annealing process form p-type backgate on super-junction structure, p-type
Trap 7 is located at the top of p-type post and extends to the top of N-type post 3.
Afterwards in p-type trap 7 formed by N+ district's groups into source region 8；On the surface of p-type trap 7 formed with gate dielectric layer such as grid
Oxide layer 5 and polysilicon gate 6；Formed interlayer film 10, contact hole 11, in the p-type trap 7 of the bottom of contact hole 11 by P+ district's groups
Into p-well draw-out area 9, front metal layer 12, source electrode and grid are drawn respectively after graphical to front metal layer 12；To semiconductor
Substrate 1 carry out be thinned form drain region or Semiconductor substrate 1 be thinned after carry out again N+ ion implantings formed drain region, formed carry on the back
Face metal level 13, drain electrode is drawn by metal layer on back 13.
For the clearer explanation method of the embodiment of the present invention one, below to form N-type superjunction of the breakdown voltage as 600V
Each step of the method for the embodiment of the present invention one is described further exemplified by MOSFET element and with reference to design parameter：
In step 1, the thickness of N-type epitaxy layer is 50 microns, and the depth of the groove is 30 microns~40 microns.
In step 2, first time p-type ion implantation technology parameter be：Implanted dopant is boron, Implantation Energy be 1Mev~
4Mev, implantation dosage 1E12cm-2~3E12cm-2；Second of N-type ion implantation technology parameter be：Implanted dopant is phosphorus, note
It is 50Kev, implantation dosage 2E12cm to enter energy-2~3E12cm-2。
If in step 3, the top of the groove width be 4.5 microns, N-type extension top width between groove is micro- for 5.5
Rice, then p-type extension is that the concentration of the first P-type silicon 41 is set according to the inclination angle of groove, typically in 4E15cm-3~
6E15cm-3, target be such that in the first P-N posts i.e. top super-junction structure in, P-N impurity levels can be balanced preferably, or protect
The difference of card two is less than the 10% of any one impurity level.
In step 4 formed p-well 7 annealing push away trap thermal process it is longer, temperature is higher, such as temperature is Celsius more than 1100
Degree, time are 60 minutes.At this moment the further improvement to above-mentioned technique is, in step 2 to complete after ion implanting twice just
High annealing is formed, the boron and phosphorus for ensureing injection can sufficiently be spread so that the thickness of N-type electric field barrier layer 31 reaches 1
Micron~2 microns, and enable the thickness of the second p-type post 42 to reach 3 microns~5 microns.
The manufacture method of the superjunction devices of the embodiment of the present invention two：
The manufacture method of the superjunction devices of the embodiment of the present invention two is used to manufacture the superjunction of the embodiment of the present invention four as shown in Figure 5
Device, in the manufacture method of the superjunction devices of the embodiment of the present invention two, the electric charge flow region of superjunction devices includes alternately being arranged by multiple
The super-junction structure of N-type post 3 and p-type the post composition of row；Each N-type post 3 and its neighbouring described p-type post form a superjunction
Unit；There is N-type electric field barrier layer 31 in the p-type post of the superjunction unit of at least more than one, there is N-type electric field resistance
The forming step of the superjunction unit of tomography 31 includes：
Step 1: provide the first N-type epitaxy layer, photoetching and p-type ion implanting are carried out the in first N-type epitaxy layer
One layer of p type island region, first layer N-type region is formed by first N-type epitaxy layer between the first layer p type island region.
Step 2: the second intrinsic epitaxial layer is formed in first N-type epitaxy layer；Carry out photoetching and p-type ion implanting
The second layer p type island region on the second intrinsic epitaxial layer, photoetching and N-type ion implanting are carried out on the second intrinsic epitaxial layer
Second layer N-type region；The second layer p type island region is superimposed upon on first p type island region, and second N-type region is superimposed upon the first N
Type area.
Step 3: p type island region and the N-type region of the formation more layers of repeat step two, each layer p type island region are superimposed to form the second p-type
Post 42, each layer N-type region are also superimposed；Repeat step two is 0 time or more than 1 time, until the thickness of the second p-type post 42
Reach requirement.In the method for the embodiment of the present invention two, as shown in figure 5, finally causing the thickness between interface B1B2 to interface D1D2
Reach 20 microns.
Step 4: N-type electric field barrier layer is formed at the top of the second p-type post 42 using photoetching and N-type ion implanting
31。
Step 5: carrying out outer layer growth forms the 3rd N-type epitaxy layer.Preferably, in the method for the embodiment of the present invention two, the
The thickness of three N-type epitaxy layers is 30 microns.
Groove is formed in the 3rd N-type epitaxy layer using lithographic etch process, the bottom of the groove is by the N-type
Electric field barrier layer 31 is exposed；P-type silicon is filled in the trench forms the first p-type post 41；By the first p-type post 41 and described
The superposition of the longitudinal direction of second p-type post 42 forms the p-type post split by the N-type electric field barrier layer 31；The N-type post 3 is by each institute
Each layer N-type region and the 3rd N-type epitaxy layer between p-type post is stated to be superimposed to be formed.
The first p-type post 41 and the adjacent N-type post 3 are alternately arranged composition top super-junction structure；The second p-type post
42 are alternately arranged composition bottom super-junction structure with the adjacent N-type post 3；The N-type electric field barrier layer 31 is used to realize the top
The segmentation of portion's super-junction structure and the bottom super-junction structure exhausts.
Preferably, in step 5, if the top of the groove width is 4.5 microns, the N-type extension top width between groove is
5.5 microns, then p-type extension is that the concentration of the first P-type silicon 41 is set according to the inclination angle of groove, typically in 4E15cm-3
~6E15cm-3,Target is such that in the first P-N posts i.e. in the super-junction structure of top, and P-N impurity levels can be balanced preferably, or
Ensure that the difference of two is less than the 10% of any one impurity level.
When the source-drain voltage of superjunction devices is less than or equal to first voltage value, only described top super-junction structure exhausts,
Electric field is terminated in the N-type electric field barrier layer 31, and the bottom super-junction structure does not exhaust.
When the source-drain voltage of superjunction devices is more than the first voltage value, the top super-junction structure is completely depleted, electricity
Continue to exhaust the bottom super-junction structure after the N-type electric field barrier layer 31 in field.
The first voltage value requirement is more than or equal to the operating voltage of the superjunction devices and less than the superjunction devices
Breakdown voltage, make the superjunction devices that exhausting for the top super-junction structure only occur at work, so as to improve grid leak electricity
The characteristics of holding, while not exhausted using the bottom super-junction structure can provide carrier in device Reverse recovery, so as to
Increase the softness factor of the Reverse recovery of device；The breakdown voltage of the superjunction devices is by the top super-junction structure and the bottom
The depletion region that portion's super-junction structure is formed when all completely depleted determines.
So that the superjunction devices is N-type super-junction MOSFET device as an example, also comprise the following steps：
Step 6: it is p-type trap 7 that photoetching and ion implanting and annealing process form p-type backgate on super-junction structure, p-type
Trap 7 is located at the top of p-type post and extends to the top of N-type post 3.
Afterwards in p-type trap 7 formed by N+ district's groups into source region 8；On the surface of p-type trap 7 formed with gate dielectric layer such as grid
Oxide layer 5 and polysilicon gate 6；Formed interlayer film 10, contact hole 11, in the p-type trap 7 of the bottom of contact hole 11 by P+ district's groups
Into p-well draw-out area 9, front metal layer 12, source electrode and grid are drawn respectively after graphical to front metal layer 12；To semiconductor
Substrate 1 carry out be thinned form drain region or Semiconductor substrate 1 be thinned after carry out again N+ ion implantings formed drain region, formed carry on the back
Face metal level 13, drain electrode is drawn by metal layer on back 13.
In step 6 formed p-well 7 annealing push away trap thermal process it is longer, temperature is higher, such as temperature is Celsius more than 1100
Degree, time are 60 minutes；This can enable several p type island regions of the second p-type post 42 to link together well, also cause and second
Several N-type regions of the adjacent N-type post of p-type post 42 can also link together well, so ensure the conducting resistance of device, hit
It is normal to wear the characteristics such as voltage.
The manufacture method of the superjunction devices of the embodiment of the present invention three：
The manufacture method of the superjunction devices of the embodiment of the present invention three and the manufacture method of the superjunction devices of the embodiment of the present invention two
Difference part is, in the superjunction devices of the embodiment of the present invention three, it is not necessary to form N-type electric field barrier layer using single step 4
31, but by the ion implanting step for forming N-type electric field barrier layer 31 be arranged in step 5 groove formed after, P-type silicon fills out
Before filling, such N-type electric field barrier layer 31 is just directly defined using the mask for forming groove, it is not necessary to individually using once
Photoetching process is defined.
The manufacture method of the superjunction devices of the embodiment of the present invention four：
The manufacture method of the superjunction devices of the embodiment of the present invention four is used to manufacture the superjunction of the embodiment of the present invention five as shown in Figure 6
Device, in the manufacture method of the superjunction devices of the embodiment of the present invention four, the electric charge flow region of superjunction devices includes alternately being arranged by multiple
The super-junction structure of N-type post 3 and p-type the post composition of row；Each N-type post 3 and its neighbouring described p-type post form a superjunction
Unit；There is N-type electric field barrier layer 31 in the p-type post of the superjunction unit of at least more than one, there is N-type electric field resistance
The forming step of the superjunction unit of tomography 31 includes：
Step 1: provide the first N-type epitaxy layer；Is formed in first N-type epitaxy layer using lithographic etch process
One groove；P-type silicon is filled in the first groove and forms the second p-type post 42.First N-type epitaxy layer corresponds in Fig. 6 and is located at
N-type epitaxy layer between interface B1B2 to interface D1D2, preferably, the thickness of the first N-type epitaxy layer is 15 microns~20 microns.
Filling P-type silicon needs to carry out cmp (CMP) realization planarization.
Step 2: carrying out outer layer growth forms the second N-type epitaxy layer；Using lithographic etch process in second N-type
Form second groove in epitaxial layer, the second p-type post 42 of the second groove alignment bottom and by the second p-type post 42
Expose on surface.Preferably, the thickness of the second N-type epitaxy layer is 30 microns.
Carry out N-type ion implanting and N-type electric field barrier layer 31 is formed in the second groove bottom, the N-type electric field blocks
Layer 31 is located at the top of the second p-type post 42；
Step 3: P-type silicon is filled in the second groove forms the first p-type post 41；Filling P-type silicon needs to carry out chemistry
Planarization is realized in mechanical lapping.Formed by the first p-type post 41 and the superposition of the longitudinal direction of the second p-type post 42 by N-type electricity
The p-type post that field barrier layer 31 is split；The N-type post 3 is by first N-type epitaxy layer between each p-type post and institute
The second N-type epitaxy layer is stated to be superimposed to be formed.
The first p-type post 41 and the adjacent N-type post 3 are alternately arranged composition top super-junction structure；The second p-type post
42 are alternately arranged composition bottom super-junction structure with the adjacent N-type post 3；The N-type electric field barrier layer 31 is used to realize the top
The segmentation of portion's super-junction structure and the bottom super-junction structure exhausts；
When the source-drain voltage of superjunction devices is less than or equal to first voltage value, only described top super-junction structure exhausts,
Electric field is terminated in the N-type electric field barrier layer 31, and the bottom super-junction structure does not exhaust；
When the source-drain voltage of superjunction devices is more than the first voltage value, the top super-junction structure is completely depleted, electricity
Continue to exhaust the bottom super-junction structure after the N-type electric field barrier layer 31 in field；
The first voltage value requirement is more than or equal to the operating voltage of the superjunction devices and less than the superjunction devices
Breakdown voltage, make the superjunction devices that exhausting for the top super-junction structure only occur at work, so as to improve grid leak electricity
The characteristics of holding, while not exhausted using the bottom super-junction structure can provide carrier in device Reverse recovery, so as to
Increase the softness factor of the Reverse recovery of device；The breakdown voltage of the superjunction devices is by the top super-junction structure and the bottom
The depletion region that portion's super-junction structure is formed when all completely depleted determines.
So that the superjunction devices is N-type super-junction MOSFET device as an example, also comprise the following steps：
Step 4: it is p-type trap 7 that photoetching and ion implanting and annealing process form p-type backgate on super-junction structure, p-type
Trap 7 is located at the top of p-type post and extends to the top of N-type post 3.
Afterwards in p-type trap 7 formed by N+ district's groups into source region 8；On the surface of p-type trap 7 formed with gate dielectric layer such as grid
Oxide layer 5 and polysilicon gate 6；Formed interlayer film 10, contact hole 11, in the p-type trap 7 of the bottom of contact hole 11 by P+ district's groups
Into p-well draw-out area 9, front metal layer 12, source electrode and grid are drawn respectively after graphical to front metal layer 12；To semiconductor
Substrate 1 carry out be thinned form drain region or Semiconductor substrate 1 be thinned after carry out again N+ ion implantings formed drain region, formed carry on the back
Face metal level 13, drain electrode is drawn by metal layer on back 13.
The manufacture method of the superjunction devices of the embodiment of the present invention five：
The manufacture method of the superjunction devices of the embodiment of the present invention five is used to manufacture the superjunction of the embodiment of the present invention six as shown in Figure 7
Device, in the manufacture method of the superjunction devices of the embodiment of the present invention five, the electric charge flow region of superjunction devices includes alternately being arranged by multiple
The super-junction structure of N-type post 3 and p-type the post composition of row；Each N-type post 3 and its neighbouring described p-type post form a superjunction
Unit；There is N-type electric field barrier layer 31 in the p-type post of the superjunction unit of at least more than one, there is N-type electric field resistance
The forming step of the superjunction unit of tomography 31 includes：
Step 1: provide the first N-type epitaxy layer；Is formed in first N-type epitaxy layer using lithographic etch process
One groove；P-type silicon is filled in the first groove and forms the second p-type post 42；N-type ion implanting is carried out in second p-type
N-type electric field barrier layer 31 is formed on the top of post 42.
First N-type epitaxy layer corresponds to the N-type epitaxy layer between interface B1B2 to interface D1D2 in Fig. 6, preferably,
The thickness of first N-type epitaxy layer is 15 microns~20 microns.It is flat that filling P-type silicon needs progress cmp (CMP) to realize
Smoothization.
Step 2: carrying out outer layer growth forms the second N-type epitaxy layer；Using lithographic etch process in second N-type
Second groove is formed in epitaxial layer, the second p-type post 42 of the second groove alignment bottom simultaneously blocks the N-type electric field
Layer 31 exposes.Preferably, the thickness of the second N-type epitaxy layer is 30 microns.
Step 3: P-type silicon is filled in the second groove forms the first p-type post 41；Filling P-type silicon needs to carry out chemistry
Planarization is realized in mechanical lapping.Formed by the first p-type post 41 and the superposition of the longitudinal direction of the second p-type post 42 by N-type electricity
The p-type post that field barrier layer 31 is split；The N-type post 3 is by first N-type epitaxy layer between each p-type post and institute
The second N-type epitaxy layer is stated to be superimposed to be formed.
The first p-type post 41 and the adjacent N-type post 3 are alternately arranged composition top super-junction structure；The second p-type post
42 are alternately arranged composition bottom super-junction structure with the adjacent N-type post 3；The N-type electric field barrier layer 31 is used to realize the top
The segmentation of portion's super-junction structure and the bottom super-junction structure exhausts.
When the source-drain voltage of superjunction devices is less than or equal to first voltage value, only described top super-junction structure exhausts,
Electric field is terminated in the N-type electric field barrier layer 31, and the bottom super-junction structure does not exhaust.
When the source-drain voltage of superjunction devices is more than the first voltage value, the top super-junction structure is completely depleted, electricity
Continue to exhaust the bottom super-junction structure after the N-type electric field barrier layer 31 in field.
The first voltage value requirement is more than or equal to the operating voltage of the superjunction devices and less than the superjunction devices
Breakdown voltage, make the superjunction devices that exhausting for the top super-junction structure only occur at work, so as to improve grid leak electricity
The characteristics of holding, while not exhausted using the bottom super-junction structure can provide carrier in device Reverse recovery, so as to
Increase the softness factor of the Reverse recovery of device；The breakdown voltage of the superjunction devices is by the top super-junction structure and the bottom
The depletion region that portion's super-junction structure is formed when all completely depleted determines.
So that the superjunction devices is N-type super-junction MOSFET device as an example, also comprise the following steps：
Step 4: it is p-type trap 7 that photoetching and ion implanting and annealing process form p-type backgate on super-junction structure, p-type
Trap 7 is located at the top of p-type post and extends to the top of N-type post 3.
Afterwards in p-type trap 7 formed by N+ district's groups into source region 8；On the surface of p-type trap 7 formed with gate dielectric layer such as grid
Oxide layer 5 and polysilicon gate 6；Formed interlayer film 10, contact hole 11, in the p-type trap 7 of the bottom of contact hole 11 by P+ district's groups
Into p-well draw-out area 9, front metal layer 12, source electrode and grid are drawn respectively after graphical to front metal layer 12；To semiconductor
Substrate 1 carry out be thinned form drain region or Semiconductor substrate 1 be thinned after carry out again N+ ion implantings formed drain region, formed carry on the back
Face metal level 13, drain electrode is drawn by metal layer on back 13.
The present invention is described in detail above by specific embodiment, but these not form the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (15)
- A kind of 1. superjunction devices, it is characterised in that：Electric charge flow region includes the super-junction structure being made up of multiple N-type posts being alternately arranged and p-type post；Each N-type post and Its neighbouring described p-type post forms a superjunction unit；There is N-type electric field barrier layer, the N-type electric field barrier layer will in the p-type post of the superjunction unit of at least more than one The p-type post is divided into the first p-type post at the top of the N-type electric field barrier layer and positioned at the N-type electric field in the vertical Second p-type post of barrier layer bottom；The first p-type post and the adjacent N-type post are alternately arranged composition top super-junction structure；The second p-type post and adjoining The N-type post is alternately arranged composition bottom super-junction structure；The N-type electric field barrier layer be used for realize the top super-junction structure and The segmentation of the bottom super-junction structure exhausts；When the source-drain voltage of superjunction devices is less than or equal to first voltage value, only described top super-junction structure exhausts, electric field Terminate in the N-type electric field barrier layer, the bottom super-junction structure does not exhaust；When the source-drain voltage of superjunction devices is more than the first voltage value, the top super-junction structure is completely depleted, electric field warp Continue to exhaust the bottom super-junction structure after crossing the N-type electric field barrier layer；The first voltage value requirement is more than or equal to the operating voltage of the superjunction devices and hitting less than the superjunction devices Voltage is worn, makes the superjunction devices that exhausting for the top super-junction structure only occur at work, so as to improve gate leakage capacitance, together The characteristics of bottom super-junction structure does not exhaust described in Shi Liyong can provide carrier in device Reverse recovery, so as to increase device The softness factor of the Reverse recovery of part；The breakdown voltage of the superjunction devices is by the top super-junction structure and the bottom superjunction The depletion region formed when structure is all completely depleted determines.
- 2. superjunction devices as claimed in claim 1, it is characterised in that：The first voltage value is by the top super-junction structure Voltage endurance capability determines that the more big first voltage value of voltage endurance capability of the top super-junction structure is bigger, the top superjunction knot The smaller first voltage value of voltage endurance capability of structure is smaller.
- 3. superjunction devices as claimed in claim 2, it is characterised in that：The thickness of the top super-junction structure is smaller, and described One magnitude of voltage is smaller.
- 4. superjunction devices as claimed in claim 1, it is characterised in that：The thickness of the bottom super-junction structure is bigger, described super The softness of the Reverse recovery of junction device is bigger.
- 5. superjunction devices as claimed in claim 1, it is characterised in that：Electricity between the first p-type post and the adjacent N-type post Lotus balances；Charge balance between the second p-type post and the adjacent N-type post；Or the total impurities of the second p-type post are more than The total impurities of the adjacent N-type post；Or the total impurities of the second p-type post are total less than the impurity of the adjacent N-type post Amount.
- 6. superjunction devices as claimed in claim 1, it is characterised in that：The doping concentration of the N-type electric field barrier layer is described 2 times~10 times of the maximum doping concentration of doping concentration in first p-type post and the second p-type post.
- 7. superjunction devices as claimed in claim 1, it is characterised in that：The thickness of the N-type electric field barrier layer is 1 micron~5 Micron.
- 8. superjunction devices as claimed in claim 1, it is characterised in that：The N-type electric field barrier layer corresponding to each p-type post Both sides and N-type post contact, and the width of each N-type electric field barrier layer is more than or equal to the corresponding first p-type post With the width of the second p-type post；Or respectively each superjunction unit with the N-type electric field barrier layer the N-type electricity Field barrier layer connection is integral.
- 9. superjunction devices as claimed in claim 1, it is characterised in that：The thickness of the first p-type post is more than second p-type The thickness of post.
- 10. the superjunction devices as described in claim 1 or 4 or 9, it is characterised in that：The thickness of the second p-type post is 2 microns ~20 microns；The second p-type post is by ion implanting or diffuses to form, or the second p-type post passes through trench fill shape Into.
- 11. superjunction devices as claimed in claim 1, it is characterised in that：The super-junction structure is formed in N-type epitaxy layer, Attach most importance to formed with the N-type cushion being made up of N-type epitaxy layer in the bottom of the N-type cushion bottom of the super-junction structure The N-type semiconductor substrate of doping.
- 12. a kind of manufacture method of superjunction devices, it is characterised in that the electric charge flow region of superjunction devices includes alternately being arranged by multiple The super-junction structure of N-type post and p-type the post composition of row；Each N-type post and its neighbouring described p-type post form a superjunction list Member；There is N-type electric field barrier layer in the p-type post of the superjunction unit of at least more than one, there is the N-type electric field barrier layer The forming step of the superjunction unit include：Step 1: providing N-type epitaxy layer, groove is formed in the N-type epitaxy layer using lithographic etch process, the groove Depth is identical with the depth of the first p-type post；Step 2: carry out first time p-type ion implanting forms the second p-type post in the channel bottom；Carry out second of N-type ion It is infused in the channel bottom and forms N-type electric field barrier layer, the N-type electric field barrier layer is located at the top of the second p-type post；Step 3: filling P-type silicon in the trench forms the first p-type post；By the first p-type post and the second p-type post Longitudinal direction superposition forms the p-type post split by the N-type electric field barrier layer；The N-type post is by the institute between each p-type post State N-type epitaxy layer composition；The first p-type post and the adjacent N-type post are alternately arranged composition top super-junction structure；The second p-type post and adjoining The N-type post is alternately arranged composition bottom super-junction structure；The N-type electric field barrier layer be used for realize the top super-junction structure and The segmentation of the bottom super-junction structure exhausts；When the source-drain voltage of superjunction devices is less than or equal to first voltage value, only described top super-junction structure exhausts, electric field Terminate in the N-type electric field barrier layer, the bottom super-junction structure does not exhaust；When the source-drain voltage of superjunction devices is more than the first voltage value, the top super-junction structure is completely depleted, electric field warp Continue to exhaust the bottom super-junction structure after crossing the N-type electric field barrier layer；The first voltage value requirement is more than or equal to the operating voltage of the superjunction devices and hitting less than the superjunction devices Voltage is worn, makes the superjunction devices that exhausting for the top super-junction structure only occur at work, so as to improve gate leakage capacitance, together The characteristics of bottom super-junction structure does not exhaust described in Shi Liyong can provide carrier in device Reverse recovery, so as to increase device The softness factor of the Reverse recovery of part；The breakdown voltage of the superjunction devices is by the top super-junction structure and the bottom superjunction The depletion region formed when structure is all completely depleted determines.
- 13. a kind of manufacture method of superjunction devices, it is characterised in that the electric charge flow region of superjunction devices includes alternately being arranged by multiple The super-junction structure of N-type post and p-type the post composition of row；Each N-type post and its neighbouring described p-type post form a superjunction list Member；There is N-type electric field barrier layer in the p-type post of the superjunction unit of at least more than one, there is the N-type electric field barrier layer The forming step of the superjunction unit include：Step 1: providing the first N-type epitaxy layer, photoetching and p-type the ion implanting first layer in first N-type epitaxy layer are carried out P type island region, first layer N-type region is formed by first N-type epitaxy layer between the first layer p type island region；Step 2: the second intrinsic epitaxial layer is formed in first N-type epitaxy layer；Photoetching and p-type ion implanting are carried out in institute Second layer p type island region on the second intrinsic epitaxial layer is stated, carries out photoetching and N-type ion implanting second on the second intrinsic epitaxial layer Layer N-type region；The second layer p type island region is superimposed upon on first p type island region, and second N-type region is superimposed upon first N-type Area；Step 3: p type island region and the N-type region of the formation more layers of repeat step two, each layer p type island region are superimposed to form the second p-type post, respectively Layer N-type region is also superimposed；Repeat step two is 0 time or more than 1 time, until the thickness of the second p-type post reaches requirement；Step 4: N-type electric field barrier layer is formed at the top of the second p-type post using photoetching and N-type ion implanting；Step 5: carrying out outer layer growth forms the 3rd N-type epitaxy layer；Using lithographic etch process in the 3rd N-type extension Groove is formed in layer, the N-type electric field barrier layer is exposed in the bottom of the groove；Filling P-type silicon is formed in the trench First p-type post；By the first p-type post and the second p-type post, longitudinally superposition is formed by N-type electric field barrier layer segmentation The p-type post；The N-type post is superimposed and formed by each layer N-type region and the 3rd N-type epitaxy layer between each p-type post；The first p-type post and the adjacent N-type post are alternately arranged composition top super-junction structure；The second p-type post and adjoining The N-type post is alternately arranged composition bottom super-junction structure；The N-type electric field barrier layer be used for realize the top super-junction structure and The segmentation of the bottom super-junction structure exhausts；When the source-drain voltage of superjunction devices is less than or equal to first voltage value, only described top super-junction structure exhausts, electric field Terminate in the N-type electric field barrier layer, the bottom super-junction structure does not exhaust；When the source-drain voltage of superjunction devices is more than the first voltage value, the top super-junction structure is completely depleted, electric field warp Continue to exhaust the bottom super-junction structure after crossing the N-type electric field barrier layer；The first voltage value requirement is more than or equal to the operating voltage of the superjunction devices and hitting less than the superjunction devices Voltage is worn, makes the superjunction devices that exhausting for the top super-junction structure only occur at work, so as to improve gate leakage capacitance, together The characteristics of bottom super-junction structure does not exhaust described in Shi Liyong can provide carrier in device Reverse recovery, so as to increase device The softness factor of the Reverse recovery of part；The breakdown voltage of the superjunction devices is by the top super-junction structure and the bottom superjunction The depletion region formed when structure is all completely depleted determines.
- 14. a kind of manufacture method of superjunction devices, it is characterised in that the electric charge flow region of superjunction devices includes alternately being arranged by multiple The super-junction structure of N-type post and p-type the post composition of row；Each N-type post and its neighbouring described p-type post form a superjunction list Member；There is N-type electric field barrier layer in the p-type post of the superjunction unit of at least more than one, there is the N-type electric field barrier layer The forming step of the superjunction unit include：Step 1: provide the first N-type epitaxy layer；First ditch is formed in first N-type epitaxy layer using lithographic etch process Groove；P-type silicon is filled in the first groove and forms the second p-type post；Step 2: carrying out outer layer growth forms the second N-type epitaxy layer；Using lithographic etch process in the second N-type extension Second groove is formed in layer, the second p-type post of the second groove alignment bottom simultaneously reveals the second p-type post surface Go out；Carry out N-type ion implanting and form N-type electric field barrier layer in the second groove bottom, the N-type electric field barrier layer is located at The top of the second p-type post；Step 3: P-type silicon is filled in the second groove forms the first p-type post；By the first p-type post and the 2nd P Longitudinally superposition forms the p-type post split by the N-type electric field barrier layer to type post；The N-type post is by between each p-type post First N-type epitaxy layer and second N-type epitaxy layer be superimposed to be formed；The first p-type post and the adjacent N-type post are alternately arranged composition top super-junction structure；The second p-type post and adjoining The N-type post is alternately arranged composition bottom super-junction structure；The N-type electric field barrier layer be used for realize the top super-junction structure and The segmentation of the bottom super-junction structure exhausts；When the source-drain voltage of superjunction devices is less than or equal to first voltage value, only described top super-junction structure exhausts, electric field Terminate in the N-type electric field barrier layer, the bottom super-junction structure does not exhaust；When the source-drain voltage of superjunction devices is more than the first voltage value, the top super-junction structure is completely depleted, electric field warp Continue to exhaust the bottom super-junction structure after crossing the N-type electric field barrier layer；The first voltage value requirement is more than or equal to the operating voltage of the superjunction devices and hitting less than the superjunction devices Voltage is worn, makes the superjunction devices that exhausting for the top super-junction structure only occur at work, so as to improve gate leakage capacitance, together The characteristics of bottom super-junction structure does not exhaust described in Shi Liyong can provide carrier in device Reverse recovery, so as to increase device The softness factor of the Reverse recovery of part；The breakdown voltage of the superjunction devices is by the top super-junction structure and the bottom superjunction The depletion region formed when structure is all completely depleted determines.
- 15. a kind of manufacture method of superjunction devices, it is characterised in that the electric charge flow region of superjunction devices includes alternately being arranged by multiple The super-junction structure of N-type post and p-type the post composition of row；Each N-type post and its neighbouring described p-type post form a superjunction list Member；There is N-type electric field barrier layer in the p-type post of the superjunction unit of at least more than one, there is the N-type electric field barrier layer The forming step of the superjunction unit include：Step 1: provide the first N-type epitaxy layer；First ditch is formed in first N-type epitaxy layer using lithographic etch process Groove；P-type silicon is filled in the first groove and forms the second p-type post；N-type ion implanting is carried out on the top of the second p-type post Portion forms N-type electric field barrier layer；Step 2: carrying out outer layer growth forms the second N-type epitaxy layer；Using lithographic etch process in the second N-type extension Second groove is formed in layer, the second p-type post of the second groove alignment bottom simultaneously reveals the N-type electric field barrier layer Go out；Step 3: P-type silicon is filled in the second groove forms the first p-type post；By the first p-type post and the 2nd P Longitudinally superposition forms the p-type post split by the N-type electric field barrier layer to type post；The N-type post is by between each p-type post First N-type epitaxy layer and second N-type epitaxy layer be superimposed to be formed；The first p-type post and the adjacent N-type post are alternately arranged composition top super-junction structure；The second p-type post and adjoining The N-type post is alternately arranged composition bottom super-junction structure；The N-type electric field barrier layer be used for realize the top super-junction structure and The segmentation of the bottom super-junction structure exhausts；When the source-drain voltage of superjunction devices is less than or equal to first voltage value, only described top super-junction structure exhausts, electric field Terminate in the N-type electric field barrier layer, the bottom super-junction structure does not exhaust；When the source-drain voltage of superjunction devices is more than the first voltage value, the top super-junction structure is completely depleted, electric field warp Continue to exhaust the bottom super-junction structure after crossing the N-type electric field barrier layer；The first voltage value requirement is more than or equal to the operating voltage of the superjunction devices and hitting less than the superjunction devices Voltage is worn, makes the superjunction devices that exhausting for the top super-junction structure only occur at work, so as to improve gate leakage capacitance, together The characteristics of bottom super-junction structure does not exhaust described in Shi Liyong can provide carrier in device Reverse recovery, so as to increase device The softness factor of the Reverse recovery of part；The breakdown voltage of the superjunction devices is by the top super-junction structure and the bottom superjunction The depletion region formed when structure is all completely depleted determines.
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| CN111341828A (en) * | 2018-12-18 | 2020-06-26 | 深圳尚阳通科技有限公司 | Super junction structure and manufacturing method thereof |
| CN111883422A (en) * | 2020-07-16 | 2020-11-03 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of super junction device |
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