CN107482060A - Superjunction devices and its manufacture method - Google Patents

Superjunction devices and its manufacture method Download PDF

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Publication number
CN107482060A
CN107482060A CN201610402272.3A CN201610402272A CN107482060A CN 107482060 A CN107482060 A CN 107482060A CN 201610402272 A CN201610402272 A CN 201610402272A CN 107482060 A CN107482060 A CN 107482060A
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packed layer
groove
type
layer
doping
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曾大杰
肖胜安
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Sanrise Technology Co ltd
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Sanrise Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors

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Abstract

The invention discloses a kind of superjunction devices, super-junction structure is alternately arranged by the second conductivity type columns being filled in groove and the first conductivity type columns being made up of the first conductive type epitaxial layer between groove and is formed super-junction structure；The side of groove tilts；Second conductivity type columns include the first and second packed layers, and the first packed layer is covered in side and the lower surface of groove, and the second packed layer is superimposed upon the surface of first packed layer；Doping concentration of two packed layers all for the doping of the second conduction type and the first packed layer is high and doping total amount of second conductivity type columns at the different depth of groove is mainly determined by the first packed layer, suppress influence of the groove side surface incline structure to the doping total amount at the different depth of groove, improve the balance of the P and n-type doping total amount at the different depth of groove.The invention also discloses a kind of manufacture method of superjunction devices.The present invention can improve the P of the top and bottom of side inclined groove and the balance of N-type impurity, improve breakdown voltage.

Description

Superjunction devices and its manufacture method
Technical field
The present invention relates to semiconductor integrated circuit manufacturing field, more particularly to a kind of superjunction (super Junction) device；The invention further relates to a kind of manufacture method of superjunction devices.
Background technology
Super-junction structure is exactly the N-type post and p-type post composition structure being alternately arranged.If substituted with super-junction structure Vertical double-diffused MOS transistor (Vertical Double-diffused Metal-Oxide-Semiconductor, VDMOS) N-type drift region in device, conduction path is provided by N-type post in the on-state, p-type post is not during conducting Conduction path is provided；Reversed bias voltage is born by PN columns jointly in the off state, be formed superjunction metal- Oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET).Super node MOSFET can be consistent with traditional VDMOS device in breakdown reverse voltage In the case of, by using the epitaxial layer of low-resistivity, and the conducting resistance of device is greatly reduced.
As shown in figure 1, being the structure chart of existing superjunction devices, the superjunction devices is super junction power device, here It is to be introduced by taking N-type superjunction devices as an example, corresponding replace of doping type progress to device can obtain P Type superjunction devices, p-type superjunction devices is not described in detail here.As shown in Figure 1, N-type superjunction devices bag Include：
Grid 1, it is polysilicon gate typically to form i.e. grid 1 by polysilicon, and thickness generally exists Between.
Gate oxide 2, for being the isolation for realizing grid 1 and raceway groove, the thickness of gate oxide 2 determines grid Pole 1 it is pressure-resistant, generally for the pressure-resistant of certain grid 1 is ensured, the thickness of gate oxide 2 is generally higher than
Source region 3, it is N+ district's groups into the dopant dose of source region 3 is ion implantation doping by N-type heavily doped region Implantation dosage is typically in 1e15/cm2More than.
P-type channel area 5, the dopant dose in P-type channel area 5 is typically in 3e13/cm2~1e14/cm2Between, The doping in P-type channel area 5 determines the threshold voltage of device, and dopant dose is higher, and the threshold voltage of device is got over It is high.It is used to form raceway groove by the surface in the P-type channel area 5 that grid 1 covers.
Hole collection area 4, be formed from the p-type heavily doped region i.e. P+ district's groups on the surface of P-type channel area 5 into.
N-type epitaxy layer 7, its bulk concentration adulterated are typically in 1e15/cm3~5e16/cm3Between, outside N-type Prolong drift region of the layer 7 as device, the thickness of N-type epitaxy layer 7 determines the breakdown voltage of device.
P-type post 6, p-type post 6 and the N-type post being made up of the N-type epitaxy layer 7 between p-type post 6 are alternately arranged Arrange and form super-junction structure, in super-junction structure, each p-type post 6 and the complementation of corresponding N-type post are adulterated and realized to N The having lateral depletion of type post, can be easily by the mutual having lateral depletion between each p-type post 6 and adjacent N-type post Realization exhausts to the N-type drift region in whole super-junction structure, so as to realize high doping concentration and high simultaneously Breakdown voltage.
P-type post 6 generally has two kinds of implementations in technique, and one kind is by being repeatedly epitaxially formed in addition one Kind is inserted to be formed by grooving and P-type silicon.
N-type epitaxy layer 7 is formed in Semiconductor substrate 9, and Semiconductor substrate 9 is that N-type is highly doped, and its body is dense Spend 1e19/cm3More than, its high doping concentration is to reduce the resistance of Semiconductor substrate 9.Superjunction power When device is MOSFET element, drain region is formed by the highly doped Semiconductor substrate 9 of N-type, and serve as a contrast in semiconductor The back side at bottom 9 forms the drain electrode being made up of metal layer on back.
In two kinds of formation process of p-type post 6, there is secondary epitaxy technique higher cost and process time to grow. And the method inserted by grooving and P-type silicon, technique is simple and efficiency high.Inserted by grooving and P-type silicon Method is relatively more to form the use of p-type post 6, is now described below：
First, need to form groove in N-type epitaxy layer using lithographic etch process.
Afterwards, P-type silicon filling is carried out to groove.
In two kinds of formation process of p-type post 6, multiple epitaxy technique has higher cost and process time It is long.And the method inserted by grooving and P-type silicon, technique is simple and efficiency high.Filled out by grooving and P-type silicon The method entered is more to form the comparison of the use of p-type post 6, is now described below：
First, need to form groove in N-type epitaxy layer using lithographic etch process.
As shown in Fig. 2 it is the schematic diagram of the ideal state of the groove of existing superjunction devices；It can be seen that in N Type epitaxial layer 101a forms multiple groove 102a.Wherein, outside the N-type in N-type epitaxy layer 101a and Fig. 1 Prolong that layer 7 is corresponding, groove 102a is the forming region of the p-type post 6 in Fig. 1.As can be seen that groove 102a side is vertical stratification, and its side inclination angle is that the angle corresponding to mark 130a is 90 degree.
As shown in figure 3, it is the schematic diagram of the actual state of the groove of existing superjunction devices；In actual process, Multiple groove 102b are formd in N-type epitaxy layer 101b；Wherein, the N in N-type epitaxy layer 101b and Fig. 1 Type epitaxial layer 7 is corresponding, and groove 102b is the forming region of the p-type post 6 in Fig. 1.As can be seen that Groove 102b side is incline structure, and its side inclination angle is that the angle corresponding to mark 130b is 88.5 degree.
Afterwards, P-type silicon is carried out to groove to fill to form the super-junction structure that N-type post and p-type post are alternately arranged.
As shown in figure 5, the super-junction structure schematic diagram when groove for being existing superjunction devices is ideal state；And figure 2 contrasts understand that p-type post 403a is made up of the P-type silicon being filled in groove 102a, and N-type post 402a is by ditch N-type epitaxy layer 101a compositions between groove 102a, p-type post 403a and N-type post 402a are alternately arranged composition Super-junction structure.It is cushion 401a in super-junction structure bottom, cushion 401a is also by N-type epitaxy layer 101a Composition, namely cushion 401a are made up of the N-type epitaxy layer 101a of groove 102a bottoms.In cushion 401a Bottom there is Semiconductor substrate 9 shown in Fig. 1.
As shown in fig. 6, the super-junction structure schematic diagram when groove for being existing superjunction devices is actual state；And figure 3 contrasts understand that p-type post 403b is made up of the P-type silicon being filled in groove 102b, and N-type post 402b is by ditch N-type epitaxy layer 101b compositions between groove 102b, p-type post 403b and N-type post 402b are alternately arranged composition Super-junction structure.It is cushion 401b in super-junction structure bottom, cushion 401b is also by N-type epitaxy layer 101b Composition, namely cushion 401b are made up of the N-type epitaxy layer 101b of groove 102b bottoms.In cushion 401b Bottom there is Semiconductor substrate 9 shown in Fig. 1.
Why groove side surface inclined structure Fig. 3 and Fig. 6 shown in is used in actual process, without using The vertical structure of groove side surface shown in Fig. 2 and Fig. 5, be because：
1st, during etching groove, the vertical structure in side is difficult stable production, if groove is due to work Skill becomes pattern of the undercut width more than top channel, just occurs that filling lacks after trench fill Fall into, cause element leakage to increase, and groove can improve the steady of etching technics after having a certain degree of inclination angle Qualitative and uniformity, this can improve the electric leakage of device and the uniformity of breakdown voltage.The wherein angle of etching groove Corresponding to the side inclination angle of the groove after etching.
2nd, in the technical process of trench fill silicon, there is certain angle of inclination, can ensure that silicon is inserted scarce It is sunken few as far as possible, and the production capacity of trench fill equipment is improved, manufacturing cost is reduced, so as to reduce The electric leakage of device.
From the foregoing, it will be observed that exactly because groove side surface incline structure can be during etching groove and trench fill mistake Good effect is all brought in journey, therefore in practical situations both, the angle of etching groove is typically 88.4 to 89 Between degree.
Although the inclined groove in side can be all favourable to etching and filling, the inclined groove in side in itself can The breakdown voltage of device is reduced, is described below：
Table one
The angle of etching groove Breakdown voltage
88.45 degree 782.54V
90 degree 938.75V
As shown in Table 1, the comparison of the breakdown voltage of device when etching groove angle difference is given in table one.This In in superjunction devices in addition to the angle difference of etching groove, the process conditions of other structures are all identical, such as adopt With identical substrat structure.It is all deep that the depth of the groove of super-junction structure is formed in the present invention, ability technology people Member is typically also referred to as deep trouth.It is assumed here that the depth of the deep trouth of device is 41 μm.
It can see from table one, because the difference of etching groove angle, breakdown voltage differ by more than 150V.Tool Body reason is as follows：
As shown in figure 4, it is the electricity for the AA ' opening positions for having the device of groove shown in Fig. 2 and Fig. 3 along Fig. 1 Field intensity distribution curve；Wherein curve 201 corresponds to the device edge with the vertical groove in the side shown in Fig. 2 The electric-field intensity distribution curve of Fig. 1 AA ' opening positions, curve 202 correspond to the side shown in Fig. 3 The electric-field intensity distribution curve of AA ' opening position of the device of inclined groove along Fig. 1, the here institute of curve 202 The side inclination angle of corresponding groove is 88.45 degree.X-axis in Fig. 4 is represented along AA ' positions in Fig. 1 Longitudinal depth, 0 micron of interface for representing silicon and silica, unit is micron；Y-axis represents electric-field intensity, Unit is V/cm.
It can be seen that homologous thread 201, in the depth bounds of whole groove, electric-field intensity is substantially flat 's.And in curve 202, electric-field intensity all has relatively low value, wherein dotted line frame in the top and bottom of groove The band of position shown in 203 is the top area of groove, and the band of position shown in dotted line frame 204 corresponds to the bottom of groove Portion region.Comparison curves 201 and 202 is understood, because the electric-field intensity of curve 202 is at the top of groove and bottom Portion can reduce, therefore the area that curve 202 covers can be smaller, namely the breakdown potential of the device corresponding to curve 202 Pressure can reduce.This is consistent with the data of table one.
Why occur in curve 202 electric-field intensity groove top and bottom reduce phenomenon, be because Caused by the N-type post of the top and bottom with the inclined groove in side and the doping balance of p-type post are deteriorated. Concrete analysis is as follows：
As shown in fig. 6, when if the angle that groove (Trench) is dug is the inclination of inclined i.e. groove side surface, that The bottom width of groove is smaller, namely p-type post 403b bottom width is small, top width is big；And N Type post 402b structure contrast, it is that top width is small, bottom width is big, because p-type post 403b is filled Shi Caiyong Uniform Doped structures, such p-type post 403b width can adulterate to the p-type at different longitudinal position Accumulated dose has an impact, and so can finally make it that the p type impurity accumulated dose of p-type post 403b bottom is less, And the p type impurity accumulated dose at p-type post 403b top is more；Correspond to N-type post 402b then contrasts, N The N-type impurity accumulated dose of type post 402b bottom is more, and the total agent of N-type impurity at N-type post 402b top Measure less；It is that the more N of P are few at the top of groove for two adjacent p-type post 403b and N-type post 402b I.e. p type impurity total amount is more, N-type impurity total amount is few, is that the few N of P are more in the bottom of groove.It will thus be seen that Occur p type impurity and the unbalanced phenomenon of N-type impurity respectively in the top and bottom of groove.
And in the groove side surface vertical stratification shown in Fig. 5, because the side of groove is vertical, therefore from groove Top-to-bottom width is consistent, and this causes doping of the width of groove to different longitudinal position not have an impact, Therefore all balanced each other in the depth bounds class of whole groove, p type impurity and N-type impurity.
For superjunction devices, the doping concentration of device why under same breakdown voltage, can be improved, is exactly Because P impurity and N impurity can be just by laterally completely depleted, it is desirable to can in each position of groove P and N is that the accumulated dose of P impurity and N impurity just balances.And if angle is inclined, then meeting naturally N is few at the top of causing, and P is more, and bottom is P few, and N is more.So P and N balance is merely able in a certain position Put, and P-N balance can not be realized in all positions.Namely P can not be realized in the top and bottom of groove Balanced with N, this exactly corresponds in Fig. 4 curve 202 in the electricity of opening position corresponding to dotted line frame 203 and 204 Field intensity can reduce；And vertical trench by no inclined groove occur in the top of the groove and bottom P and N Unbalanced problem, therefore the Electric Field Distribution in the range of whole gash depth of curve 201 is flat.It is exactly because bent In line 202 the top of the groove and bottom electric-field intensity reduction so that have the inclined groove in side superjunction The breakdown voltage of device can drastically reduce, and reduce more than 150V.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of superjunction devices, can improve the top of side inclined groove The P and N-type impurity of portion and bottom balance, so as to improve breakdown voltage.Therefore, the present invention also provides one kind The manufacture method of superjunction devices.
In order to solve the above technical problems, in superjunction devices provided by the invention, on the first conductive type epitaxial layer Formed with multiple grooves, in the trench filled with the second conductivity type columns, the institute being filled in the groove First for stating the second conductivity type columns and being made up of first conductive type epitaxial layer between the groove is led Electric type post is alternately arranged composition super-junction structure；
The side of the groove is that incline structure makes the bottom width of the groove be less than top width, so as to favourable The filling with second conductivity type columns is etched so as to reduce filling defect in the groove；
Second conductivity type columns include the first packed layer and the second packed layer, and first packed layer is covered in The side of the groove and lower surface, second packed layer are superimposed upon the surface of first packed layer；Institute State the first packed layer and second packed layer and all mixed for the doping of the second conduction type and first packed layer Miscellaneous concentration is more than 2 times of the doping concentration of second packed layer, makes second conductivity type columns described The second conduction type doping total amount at the different depth of groove is mainly determined by first packed layer, so as to press down Make the groove bottom width be less than top width side incline structure to the different depth of the groove at The second conduction type doping total amount influence, so as to improve the second conductive-type at the different depth of the groove Type adulterates the balance of the first conduction type doping total amount of total amount and adjacent first conductivity type columns.
Further improve is that first conductive type epitaxial layer is the first conduction type silicon epitaxy layer, described First packed layer is the second conduction type silicon epitaxy layer, second packed layer be the second conduction type silicon epitaxy layer, Second conductivity type polysilicon layer or deielectric-coating.
Further improve is that the inclination angle of the side of the groove is 88.4 degree~89 degree.
Further improve is that the doping concentration of first packed layer meets：The second of first packed layer Conductive type impurity total amount is the first value, and the total impurities of first conductivity type columns are second value, described the The difference of one value and the second value is the 3rd value, and the 3rd value is less than the 10% of the described first value, described the Three 10% of value less than the second value.
Further improve is that second conductivity type columns also include the 3rd packed layer, the 3rd packed layer Doping concentration for the doping of the second conduction type and the 3rd packed layer is that the doping of first packed layer is dense Less than the 1/2 of degree；3rd packed layer is located at bottom of the thickness less than the groove of the side of the groove The 1/5 of width, the 3rd packed layer are isolated from side and the bottom table of second packed layer and the groove Between face, for reducing p type impurity between adjacent p-type post and N-type post and N-type impurity diffusion so as to dropping Low on-resistance.
Further improve is that second conductivity type columns also include the 4th packed layer, the 4th packed layer Doping concentration for the doping of the second conduction type and the 4th packed layer is that the doping of second packed layer is dense More than 2 times of degree, the 4th packed layer is superimposed upon the surface of second packed layer.
Further improve is that the doping concentration of first packed layer is the doping concentration of second packed layer More than 10 times.
Further improve is that the volume of first packed layer is more than or equal to whole second conductivity type columns Volume half；Or first packed layer be covered in the lower surface of the groove thickness be more than etc. In the 1/3 of the depth of the groove.
Further improve is that first conductive type epitaxial layer is Uniform Doped structure.
Or the overlaying structure that first conductive type epitaxial layer is the first extension sublayer and the second extension sublayer, The first extension sublayer is Uniform Doped structure, and the second extension sublayer is Uniform Doped structure, described One extension sublayer is different with the doping concentration of the second extension sublayer.
Or the doping concentration of first conductive type epitaxial layer is in the direction from lower surface to top surface It is upper to be distributed in incremental gradient distribution or the gradient successively decreased.
Further improve is that the first conduction type is N-type, and the second conduction type is p-type；Or first Conduction type is p-type, and the second conduction type is N-type.
In order to solve the above technical problems, the manufacture method of superjunction devices provided by the invention comprises the following steps：
Step 1: the first conductive type epitaxial layer is provided, formed with multiple ditches on the first conductive type epitaxial layer Groove, the side of the groove makes the bottom width of the groove be less than top width for incline structure, so as to favourable The filling with follow-up second conductivity type columns is etched so as to reduce filling defect in the groove.
Step 2: the second conductivity type columns are filled in the trench, described second be filled in the groove Conductivity type columns and the first conduction type being made up of first conductive type epitaxial layer between the groove Post is alternately arranged composition super-junction structure.
The fill process of second conductivity type columns is included as follows step by step：
Step 21, the first packed layer of filling formation for the first time is carried out, first packed layer is covered in the ditch The side of groove and lower surface.
Step 22, carry out second filling and form the second packed layer, second packed layer is superimposed upon described the The surface of one packed layer.
First packed layer and second packed layer are all the doping of the second conduction type and first filling The doping concentration of layer is more than 2 times of the doping concentration of second packed layer, makes second conductivity type columns The second conduction type at the different depth of the groove adulterates total amount and mainly determined by first packed layer, So as to suppress difference of the side incline structure to the groove that the bottom width of the groove is less than top width The influence of the second conduction type doping total amount of depth, so as to improve second at the different depth of the groove Conduction type adulterates the flat of the first conduction type doping total amount of total amount and adjacent first conductivity type columns Weighing apparatus.
Further improve is that first conductive type epitaxial layer is the first conduction type silicon epitaxy layer, described First packed layer is the second conduction type silicon epitaxy layer, second packed layer be the second conduction type silicon epitaxy layer, Second conductivity type polysilicon layer or deielectric-coating.
Further improve is that the doping concentration of first packed layer meets：The second of first packed layer Conductive type impurity total amount is the first value, and the total impurities of first conductivity type columns are second value, described the The difference of one value and the second value is the 3rd value, and the 3rd value is less than the 10% of the described first value, described the Three 10% of value less than the second value.
Further improve be, in the fill process of second conductivity type columns of step 2 step 21 it It is preceding also to include：
Step 20, in the side of the groove and lower surface form the 3rd packed layer, the 3rd packed layer Doping concentration for the doping of the second conduction type and the 3rd packed layer is that the doping of first packed layer is dense Less than the 1/2 of degree；3rd packed layer is located at bottom of the thickness less than the groove of the side of the groove The 1/5 of width, the 3rd packed layer are isolated from side and the bottom table of second packed layer and the groove Between face, for reducing p type impurity between adjacent p-type post and N-type post and N-type impurity diffusion so as to dropping Low on-resistance.
Further improve be, in the fill process of second conductivity type columns of step 2 step 22 it Also include afterwards：
Step 23, the 4th packed layer is formed on the surface of second packed layer, the 4th packed layer is the Two conduction types adulterate and the doping concentration of the 4th packed layer is the doping concentration of second packed layer More than 2 times.
Inclined groove structure is used in the super-junction structure of the present invention, using inclined groove in etching groove and groove The advantages of in filling, the stability and uniformity of trench etch process can be respectively increased, improve trench fill and set Standby production capacity and the defects of reduce cost and trench fill can be reduced, so as to reduce caused by defect Device electric leakage.
In addition, the present invention can also be solved the problems, such as because the breakdown voltage that groove tilting band is come reduces and can carry significantly The breakdown voltage of high device：The present invention is directed to the characteristic of the top width narrow base of inclined groove, in order to avoid groove The longitudinally wide different influence to PN impurity balances, the present invention is to the second conductive-type for filling in the trench Type post is specifically designed, and the second conductivity type columns include the first packed layer and the second packed layer, the first filling Layer is covered in side and the lower surface of groove, and the second packed layer is superimposed upon the surface of the first packed layer；Passing through will First packed layer is arranged to high-concentration dopant, makes the second conductivity type columns second leading at the different depth of groove Electric type doping total amount is mainly determined by the first packed layer, is less than top width so as to suppress the bottom width of groove Side incline structure at the different depth of groove the second conduction type adulterate total amount influence, so as to improve The second conduction type at the different depth of groove adulterates total amount and the first of the first adjacent conductivity type columns and led The balance of electric type doping total amount, it can so greatly improve the breakdown voltage of device.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is the structure chart of existing superjunction devices；
Fig. 2 is the schematic diagram of the ideal state of the groove of existing superjunction devices；
Fig. 3 is the schematic diagram of the actual state of the groove of existing superjunction devices；
Fig. 4 is the electric-field intensity point for the AA ' opening positions for having the device of groove shown in Fig. 2 and Fig. 3 along Fig. 1 Cloth curve；
Fig. 5 is the super-junction structure schematic diagram when groove of existing superjunction devices is ideal state；
Fig. 6 is the super-junction structure schematic diagram when groove of existing superjunction devices is actual state；
Fig. 7 is the super-junction structure schematic diagram of first embodiment superjunction devices of the embodiment of the present invention；
Fig. 8 is that have the existing superjunction shown in the super-junction structure and Fig. 6 of the first embodiment of the invention shown in Fig. 7 The electric-field intensity distribution curve of AA ' opening position of the structure along Fig. 1；
Fig. 9 is the structure chart of second embodiment superjunction devices of the embodiment of the present invention；
Super-junction structure in each step of manufacture method of Figure 10 A- Figure 10 D third embodiment of the invention superjunction devices Schematic diagram；
Super-junction structure in each step of manufacture method of Figure 11 A- Figure 11 D fourth embodiment of the invention superjunction devices Schematic diagram.
Embodiment
First embodiment of the invention superjunction devices illustrates by taking N-type device as an example, and first embodiment of the invention surpasses Junction device is a super junction power device, and its structural representation is identical with Fig. 1.It is conductive for N-type device, first Type is N-type, and the second conduction type is p-type, and the first conduction type is changed into p-type and by the second conductive-type Type, which is changed to N-type, can then obtain P-type device, P-type device not elaborated in description of the invention.
First embodiment of the invention superjunction devices is mainly that the super-junction structure of device is specifically designed, such as Fig. 7 It is shown, it is the super-junction structure schematic diagram of first embodiment superjunction devices of the embodiment of the present invention；In N-type epitaxy layer Formed with multiple grooves 503, p-type post is filled with the groove 503, is filled in the groove 503 The p-type post and the N-type post 502 that is made up of the N-type epitaxy layer between the groove 503 alternately arrange Row composition super-junction structure.N-type epitaxy layer in Fig. 7 is the N-type epitaxy layer 7 in Fig. 1, outside the N-type It is Uniform Doped structure to prolong layer 7, is Semiconductor substrate such as silicon substrate 9 in the bottom of N-type epitaxy layer 7；This hair In bright first embodiment, the groove 503 is not passed through the N-type epitaxy layer 7, finally in super-junction structure Formed with the cushion 501 being made up of the N-type epitaxy layer 7, cushion 501 is used to buffer heavy doping for bottom Influence of the Semiconductor substrate 9 to super-junction structure.
The side of the groove 503 is that incline structure makes the bottom width of the groove 503 be less than top width, So as to be advantageous to the filling of the etching of the groove 503 and the p-type post so as to reduce filling defect.Preferably, The inclination angle of the side of the groove 503 is 88.4 degree~89 degree.
The p-type post includes the first packed layer 504 and the second packed layer 505, and first packed layer 504 covers Cover in the side of the groove 503 and lower surface, second packed layer 505 is superimposed upon first filling The surface of layer 504；First packed layer 504 and second packed layer 505 are all p-type doping and described The doping concentration of first packed layer 504 is more than 2 times of the doping concentration of second packed layer 505, makes institute State p-type of the p-type post at the different depth of the groove 503 and adulterate total amount mainly by first packed layer 504 determine, so as to suppress side incline structure of the bottom width of the groove 503 less than top width to institute The influence of the p-type doping total amount at the different depth of groove 503 is stated, so as to improve the difference of the groove 503 The balance of the p-type doping total amount of depth and the n-type doping total amount of the adjacent N-type post 502.
In first embodiment of the invention, the doping concentration of the first packed layer 5 is very high, and the second packed layer 505 doping concentration is very low, the doping concentration of the second packed layer 505 light can arrive close to intrinsic doping and It is exactly intrinsic doping.Preferably, the doping concentration of first packed layer 504 is second packed layer 505 More than 10 times of doping concentration.
The N-type epitaxy layer is N-type silicon epitaxy layer, and first packed layer 504 is P-type silicon epitaxial layer, institute It is P-type silicon epitaxial layer, p-type polysilicon layer or deielectric-coating to state the second packed layer 505.
The doping concentration of first packed layer 504 meets：The p type impurity total amount of first packed layer 504 For the first value, the total impurities of the N-type post 502 are second value, the difference of first value and the second value It is worth and is less than the 10% of the described first value for the 3rd value, the 3rd value, the 3rd value is less than the second value 10%.The setting of the doping concentration of first packed layer 504 described above enables to the difference of the groove 503 The p-type doping total amount of depth and the n-type doping total amount of the adjacent N-type post 502 reach good balance. In other embodiments, can be to described above according to the height of the requirement of N-type and the balance of p type impurity 10% is increased or decreased.
Set for thickness, preferably：The volume of first packed layer 504 is more than or equal to the whole P The half of the volume of type post；Or first packed layer 504 is covered in the lower surface of the groove 503 Thickness be more than or equal to the groove 503 depth 1/3.
The above is the description to the super-junction structure of the superjunction devices in first embodiment of the invention, for super-junction structure Other structures, refer to shown in Fig. 1, including：
Grid 1, it is polysilicon gate typically to form i.e. grid 1 by polysilicon, and thickness generally exists Between.
Gate oxide 2, for being the isolation for realizing grid 1 and raceway groove, the thickness of gate oxide 2 determines grid Pole 1 it is pressure-resistant, generally for the pressure-resistant of certain grid 1 is ensured, the thickness of gate oxide 2 is generally higher thanIn other embodiments, the gate oxide 2 can also use other dielectric layers to replace.
Source region 3, it is N+ district's groups into the dopant dose of source region 3 is ion implantation doping by N-type heavily doped region Implantation dosage is typically in 1e15/cm2More than.
P-type channel area 5, the dopant dose in P-type channel area 5 is typically in 3e13/cm2~1e14/cm2Between, The doping in P-type channel area 5 determines the threshold voltage of device, and dopant dose is higher, and the threshold voltage of device is got over It is high.It is used to form raceway groove by the surface in the P-type channel area 5 that grid 1 covers.
Hole collection area 4, be formed from the p-type heavily doped region i.e. P+ district's groups on the surface of P-type channel area 5 into.
N-type epitaxy layer 7, its bulk concentration adulterated are typically in 1e15/cm3~5e16/cm3Between, outside N-type Prolong drift region of the layer 7 as device, the thickness of N-type epitaxy layer 7 determines the breakdown voltage of device.
P-type post 6 in Fig. 1 corresponds in Fig. 7 to be superimposed by the first packed layer 504 and the second packed layer 505 The p-type post of formation.N-type post 502 in Fig. 7 corresponds in Fig. 1 by the N-type epitaxy layer between p-type post 6 The N-type post of 7 compositions.
N-type epitaxy layer 7 is formed in Semiconductor substrate 9, and Semiconductor substrate 9 is that N-type is highly doped, and its body is dense Spend 1e19/cm3More than, its high doping concentration is to reduce the resistance of Semiconductor substrate 9.Superjunction power When device is MOSFET element, drain region is formed by the highly doped Semiconductor substrate 9 of N-type, and serve as a contrast in semiconductor The back side at bottom 9 forms the drain electrode being made up of metal layer on back.
In first embodiment of the invention device, filled by using p-type twice to form P in groove 503 Type post.Pay attention in the prior art, also thering is the method for mentioning multiple P fillings, but prior art is only public Opened using for the first time do it is light, to reduce the horizontal expansion between P and N-type impurity between N-type post and p-type post, Compare conducting resistance so as to reduce.And the multiple p-type filling of the p-type post in first embodiment of the invention is according to this The technical problems to be solved by the invention set out what is be designed, i.e., different primarily directed to the angle of deep etching, Cause the P of the bottom of groove 503 i.e. p type impurity total amount be few less and the P i.e. p type impurity total amounts more at top are more, By repeatedly filling this problem that makes up, accomplish the P-N i.e. P between N-type post and p-type post as far as possible Type impurity and N-type impurity realize preferably balance, so as to preferably improve breakdown voltage, so as to obtain more Good performance.
First time in the filling twice of first embodiment of the invention fills first packed layer 504 to be formed Second packed layer 505 that doping concentration is very dense and second filling is formed doping concentration it is very light, Both concentration differences are even more at 2 times.
Both thickness can be filled with the filling time of second of filling to adjust for the first time by adjusting, and can be made ：The volume of first packed layer 504 is more than or equal to the half of the volume of the whole p-type post；Or The thickness that first packed layer 504 is covered in the lower surface of the groove 503 is more than or equal to the groove The 1/3 of 503 depth.It is specifically as follows：If it is assumed that completely complete the time corresponding to whole deep trouth 503 For 1, then can allow 30% time raising concentration first packed layer 504,70% time fills out low concentration Second packed layer 505；Can also allow 25% time raising concentration first packed layer 504, Either 75% time fills out second packed layer 505 of low concentration；40% time raising can also be allowed dense First packed layer 504 of degree, or 60% time fill out second packed layer 505 of low concentration. This can voluntarily be selected according to the requirement of designer.It can be seen that described the first of first embodiment of the invention Packed layer 504 is very dense, and second packed layer 505 is very light, and its groove 503 bottom P is few, top Phenomenon more than portion P is alleviated, and the PN balances of device are more preferable.Breakdown voltage can finally be improved.
As shown in Table 2, table two is in the existing p-type post and first embodiment of the invention that composition is filled using single The breakdown voltage of superjunction devices of p-type post of the composition of packed layer twice compare.Wherein p-type post is existing There is single interstitital texture to refer to shown in Fig. 6, the p-type post 403b in Fig. 6 is single interstitital texture, from ditch Trench bottom to top p-type post 403b doping concentration is identical last make it that the p type impurity of the top of the groove is more, bottom I.e. top P is more less, bottom P is few for the p type impurity in portion.For the ease of comparing, the doping concentration of p-type post is entered Row normalized, it is assumed that the doping concentration using the p-type post 403b of the existing structure shown in Fig. 6 is as 1.0 1 unit doping concentration；The of the p-type post being then used in table two in the first embodiment of the invention that is compared The doping concentration of one packed layer 504 is arranged to 1.5, and the doping concentration of the second packed layer 505 is arranged to 0.1, It can be seen that the second packed layer 505 is close to intrinsic filling.Incline the side for the groove that both p-type posts are filled Angle all uses 88.45 degree, it can be seen that the breakdown voltage of the device of first embodiment of the invention can reach 932.54V, 150V is improved relative to the 782.54V of existing device.Compare and understand with table one, the present invention the The breakdown voltage of the device of one embodiment only hitting than the 938.75V using the vertical existing device of groove side surface Wear the low 6V of voltage, both substantially close to.
It follows that the existing device vertical with groove side surface is compared, the groove side surface of first embodiment of the invention To tilt, this can make it that first embodiment of the invention is favourable to the etching of groove and filling, i.e., can be respectively increased The production capacity of etching machine bench equipment and the defects of reduce cost and trench fill can be reduced, so as to reduce due to The electric leakage of device caused by defect and the breakdown voltage for improving device.
And compared with the inclined existing device of groove, after first embodiment of the invention is using two layers of interstitital texture, energy Enough greatly improve breakdown voltage.
Table two
P-type rod structure Breakdown voltage (V)
Existing single interstitital texture 782.54
The interstitital texture twice of first embodiment of the invention 932.54
The breakdown voltage that first embodiment of the invention device can improve device can also be found out from Fig. 8 is vivid, scheme Curve 301 is the superjunction devices of the super-junction structure with the first embodiment of the invention shown in Fig. 7 along Fig. 1 in 8 AA ' opening positions electric-field intensity distribution curve, curve 302 is that have the existing super-junction structure shown in Fig. 6 AA ' opening position of the superjunction devices along Fig. 1 electric-field intensity distribution curve；Corresponding to curve 301 and 302 Groove side inclination angle all be 88.45 degree.X-axis in Fig. 8 represent along in Fig. 1 AA ' positions it is vertical To depth, 0 micron of interface for representing silicon and silica, unit is micron；Y-axis represents electric-field intensity, single Position is V/cm.
Dotted line frame 303 corresponds to the top area of groove, and dotted line frame 304 corresponds to the bottom section of groove, can Know, in the top area and bottom section of groove, the electric-field intensity of first embodiment of the invention is all improved, This is due to that first embodiment of the invention all realizes N-type impurity and p type impurity in the top and bottom of groove Balance, finally make it that the depth bounds inner curve 301 in whole groove is all relatively more flat；And curve 302 and Fig. 4 In curve 202 it is identical, be all due to N-type impurity and the imbalance of p type impurity in the top and bottom of groove It is that the more N of P are few, groove bottom is few for the more P of N at the top of groove, by N-type impurity and p type impurity not Balance and finally reduce corresponding electric-field intensity.
As shown in figure 9, it is the structure chart of second embodiment superjunction devices of the embodiment of the present invention；The present invention second is real Apply in place of the difference of a superjunction devices and first embodiment of the invention superjunction devices and be：In second embodiment of the invention N-type epitaxy layer be the first extension sublayer 7b and the second extension sublayer 7a overlaying structure, first extension Sublayer 7b is Uniform Doped structure, and the second extension sublayer 7a is Uniform Doped structure, first extension Sublayer 7b and the second extension sublayer 7a doping concentration is different.Other structures are all identical, namely the present invention P-type post in second embodiment also uses the p-type rod structure of first embodiment of the invention as shown in Figure 7.
In other embodiments, also can be：The doping concentration of the N-type epitaxy layer is from lower surface to top In incremental gradient distribution or the gradient distribution successively decreased on the direction on surface, i.e., N-type epitaxy layer is Graded Epi.
As shown in Figure 10 D, it is the super-junction structure schematic diagram of third embodiment of the invention superjunction devices；The present invention the It is in place of the difference of three embodiment superjunction devices and first embodiment of the invention superjunction devices：The present invention the 3rd is implemented Also include the 3rd packed layer 506, the 3rd packed layer 506 in the p-type post of the super-junction structure of example superjunction devices Doping concentration for p-type doping and the 3rd packed layer 506 is the doping concentration of first packed layer 504 Less than 1/2；The thickness that 3rd packed layer 506 is located at the side of the groove 503 is less than the groove The 1/5 of 503 bottom width, the 3rd packed layer 506 are isolated from second packed layer 505 and described Between the side of groove 503 and lower surface, for reducing the P between adjacent p-type post and N-type post 502 Type impurity and N-type impurity are spread so as to reduce conducting resistance.That is, the knot relative to first embodiment of the invention In structure the first packed layer 504 be formed directly into groove side and lower surface so as to and N-type epitaxy layer directly connect Tactile situation, in third embodiment of the invention using relatively low the 3rd packed layer 506 of doping concentration come and N Type epitaxial layer is in contact, and this p type impurity that can reduce high concentration is diffused laterally into N-type post 502 so as to drop Low on-resistance.
As shown in Figure 11 D, it is the super-junction structure schematic diagram of fourth embodiment of the invention superjunction devices；The present invention the It is in place of the difference of three embodiment superjunction devices and first embodiment of the invention superjunction devices：The present invention the 3rd is implemented Also include the 4th packed layer 507, the 4th packed layer 507 in the p-type post of the super-junction structure of example superjunction devices Doping concentration for p-type doping and the 4th packed layer 507 is the doping concentration of second packed layer 505 More than 2 times, the 4th packed layer 507 is superimposed upon the surface of second packed layer 505.The present invention the The 4th packed layer 507 in four embodiments positioned at the top of the groove can be carried out to the doping at the top of groove 503 Regulation, improves the p-type of the top of the groove and the balance of N-type impurity.
Increase third embodiment of the invention on the basis of the super-junction structure of first embodiment of the invention superjunction devices In the 3rd packed layer 506 and fourth embodiment of the invention in the 4th packed layer 507 can obtain the present invention the The super device of five embodiments, namely the super-junction structure of fifth embodiment of the invention superjunction devices p-type post by the 3rd Packed layer 506, the first packed layer 504, the second packed layer 505 and the superposition of the 4th packed layer 507 are formed.
The manufacture method of first embodiment of the invention superjunction devices is for the super-junction structure shown in Fig. 7 Superjunction devices, the schematic diagram of whole superjunction devices is as shown in figure 1, comprise the following steps：
Step 1: N-type epitaxy layer is provided, formed with multiple grooves 503, the groove in N-type epitaxy layer 503 side is that incline structure makes the bottom width of the groove 503 be less than top width, so as to be advantageous to The etching of groove 503 and the filling of follow-up p-type post are stated so as to reduce filling defect.
N-type epitaxy layer is the N-type epitaxy layer 7 in Fig. 1, and the N-type epitaxy layer 7 is Uniform Doped structure, It is Semiconductor substrate such as silicon substrate 9 in the bottom of N-type epitaxy layer 7；In first embodiment of the invention, the ditch Groove 503 is not passed through the N-type epitaxy layer 7, finally in the bottom of super-junction structure formed with outside by the N-type Prolong the cushion 501 of the composition of layer 7, the Semiconductor substrate 9 that cushion 501 is used to buffer heavy doping is to superjunction knot The influence of structure.
Preferably, the inclination angle of the side of the groove 503 is 88.4 degree~89 degree.
Step 2: p-type post, the P being filled in the groove 503 are filled in the groove 503 Type post and the N-type post 502 being made up of the N-type epitaxy layer between the groove 503, which are alternately arranged to form, to be surpassed Junction structure；
The fill process of the p-type post is included as follows step by step：
Step 21, the first packed layer 504 of filling formation for the first time is carried out, first packed layer 504 is covered in The side of the groove 503 and lower surface.
Step 22, second of filling the second packed layer 505 of formation is carried out, second packed layer 505 is superimposed upon The surface of first packed layer 504.
First packed layer 504 and second packed layer 505 are all p-type doping and first packed layer 504 doping concentration is more than 2 times of the doping concentration of second packed layer 505, the p-type post is existed P-type at the different depth of the groove 503 is adulterated total amount and mainly determined by first packed layer 504, from And the bottom width for suppressing the groove 503 is less than the side incline structure of top width to the groove 503 Different depth at p-type doping total amount influence, so as to improve the P at the different depth of the groove 503 Type adulterates the balance of total amount and the n-type doping total amount of the adjacent N-type post 502.
In first embodiment of the invention method, the doping concentration of the first packed layer 5 is very high, and the second filling The doping concentration of layer 505 is very low, and the doping concentration of the second packed layer 505 light can be arrived close to intrinsic doping It is exactly intrinsic doping.Preferably, the doping concentration of first packed layer 504 is second packed layer More than 10 times of 505 doping concentration.
The N-type epitaxy layer is N-type silicon epitaxy layer, and first packed layer 504 is P-type silicon epitaxial layer, institute It is P-type silicon epitaxial layer, p-type polysilicon layer or deielectric-coating to state the second packed layer 505.
The doping concentration of first packed layer 504 meets：The p type impurity total amount of first packed layer 504 For the first value, the total impurities of the N-type post 502 are second value, the difference of first value and the second value It is worth and is less than the 10% of the described first value for the 3rd value, the 3rd value, the 3rd value is less than the second value 10%.The setting of the doping concentration of first packed layer 504 described above enables to the difference of the groove 503 The p-type doping total amount of depth and the n-type doping total amount of the adjacent N-type post 502 reach good balance. In other embodiments, can be to described above according to the height of the requirement of N-type and the balance of p type impurity 10% is increased or decreased.
Set for thickness, preferably：The volume of first packed layer 504 is more than or equal to the whole P The half of the volume of type post；Or first packed layer 504 is covered in the lower surface of the groove 503 Thickness be more than or equal to the groove 503 depth 1/3.
In first embodiment of the invention method, it can be adjusted by the filling time that step 21 and step 22 are filled The thickness of first packed layer 504 and second packed layer 505 is saved, is specifically as follows：It is if it is assumed that complete The whole time completed corresponding to whole deep trouth 503 is 1, then can allow 30% time raising concentration described the One packed layer 504,70% time fill out second packed layer 505 of low concentration；Can also allow 25% time First packed layer 504 of raising concentration, or 75% time fill out second packed layer of low concentration 505；Can also allow 40% time raising concentration first packed layer 504, or 60% time fill out Second packed layer 505 of low concentration.This can voluntarily be selected according to the requirement of designer.
As shown in Figure 10 A to Figure 10 D, in each step of manufacture method of third embodiment of the invention superjunction devices The schematic diagram of super-junction structure, in place of the difference of third embodiment of the invention method and first embodiment of the invention method For in third embodiment of the invention method, in step 21 in the fill process of the p-type post of step 2 Also include before：
Step 20, as shown in Figure 10 B, the 3rd filling is formed in the side of the groove 503 and lower surface Layer 506, the 3rd packed layer 506 is adulterated for p-type and the doping concentration of the 3rd packed layer 506 is institute State less than the 1/2 of the doping concentration of the first packed layer 504；3rd packed layer 506 is located at the groove The thickness of 503 side be less than the groove 503 bottom width 1/5, the 3rd packed layer 506 every It is adjacent for reducing between second packed layer 505 and the side of the groove 503 and lower surface P-type post and N-type post 502 between p type impurity and N-type impurity diffusion so as to reducing conducting resistance.
Figure 10 A have been formed corresponding to the schematic diagram after the completion of step 1, at this moment groove 503, the present invention the 3rd The step of the step of embodiment method one and first embodiment of the invention method one, is identical.
After step 20, step 21 and 22 is carried out, this also step all with first embodiment of the invention method Rapid 21 and 22 is identical.The structural representation that wherein Figure 10 C correspond to after the completion of step 21, i.e. step 21 In form the first packed layer 504.The structural representation that Figure 10 D correspond to after the completion of step 22, i.e. step The second packed layer 505 is formd in 22.
The thickness of each packed layer can be adjusted by the filling time in regulating step 20 to 22, each packed layer Doping concentration also represents that the doping concentration for making the first higher packed layer 504 of concentration is 1 using normalization That is 1 unit；In addition, it is 1 to make the whole filling time again, then can be used such as in an embodiment Lower parameter realizes third embodiment of the invention method：Step 20 filling time is 5%, concentration 0.3；Step 21 filling time is 25%, concentration 1；The filling time of step 22 is 75%, concentration 0.05.This The parameter of a little embodiments is merely to the clearer explanation present invention, moreover it is possible to has other changes, according to reality Border needs to be configured.
As shown in Figure 11 A to Figure 11 D, in each step of manufacture method of fourth embodiment of the invention superjunction devices The schematic diagram of super-junction structure, in place of the difference of fourth embodiment of the invention method and first embodiment of the invention method For in fourth embodiment of the invention method, in step 22 in the fill process of the p-type post of step 2 Also include afterwards：
Step 23, as shown in Figure 11 D, the 4th packed layer 507 is formed on the surface of second packed layer 505, 4th packed layer 507 is that the doping concentration of p-type doping and the 4th packed layer 507 is described second to fill out Fill the doping concentration of layer 505 more than 2 times.
Figure 11 A have been formed corresponding to the schematic diagram after the completion of step 1, at this moment groove 503, the present invention the 4th The step of the step of embodiment method one and first embodiment of the invention method one, is identical.
Step 21 and 22 all identical with the step 21 of first embodiment of the invention method and 22.Wherein Figure 11 B Corresponding to the structural representation after the completion of step 21, i.e., the first packed layer 504 is formd in step 21.Figure 11 C Corresponding to the structural representation after the completion of step 22, i.e., the second packed layer 505 is formd in step 22.
The thickness of each packed layer can be adjusted by the filling time in regulating step 21 to 23, each packed layer Doping concentration also represents that the doping concentration for making the first higher packed layer 504 of concentration is 1 using normalization That is 1 unit；In addition, it is 1 to make the whole filling time again, then can be used such as in an embodiment Lower parameter realizes fourth embodiment of the invention method：The filling time of step 21 is 30%, concentration 1；Step 22 filling time is 50%, concentration 0.05；The filling time of step 23 is 20%, concentration 1.It is right In step 23, in other embodiments, also can be：The filling time of step 23 is 20%, concentration 2. The parameter of these embodiments is merely to the clearer explanation present invention, moreover it is possible to there are other changes, according to It is actually needed and is configured.
Also can on the basis of first embodiment of the invention method increase third embodiment of the invention method the step of 20 and fourth embodiment of the invention method step 23 formed fifth embodiment of the invention method, namely the present invention The step of 5th embodiment method two, is made up of step 20,21,22 and 23.Equally, the present invention the 5th is implemented The thickness of each packed layer can be adjusted in example by the filling time in regulating step 21 to 23, each packed layer Doping concentration also represents that the doping concentration for making the first higher packed layer 504 of concentration is 1 using normalization That is 1 unit；In addition, it is 1 to make the whole filling time again, then can be used such as in an embodiment Lower parameter realizes fifth embodiment of the invention method：The filling time of step 20 is 5%, concentration 0.4；Step Rapid 21 filling time is 25%, concentration 1；The filling time of step 22 is 50%, concentration 0.05； The filling time of step 23 is 20%, concentration 1.The parameter of these embodiments is merely to become apparent from Explanation the present invention, moreover it is possible to have other changes, be configured according to being actually needed.
The present invention is described in detail above by specific embodiment, but these are not formed to the present invention Limitation.Without departing from the principles of the present invention, those skilled in the art can also make it is many deformation and Improve, these also should be regarded as protection scope of the present invention.

Claims (15)

  1. A kind of 1. superjunction devices, it is characterised in that：Formed with multiple grooves on the first conductive type epitaxial layer, The second conductivity type columns are filled with the trench, second conductivity type columns being filled in the groove And the first conductivity type columns being made up of first conductive type epitaxial layer between the groove are alternately arranged Form super-junction structure；
    The side of the groove is that incline structure makes the bottom width of the groove be less than top width, so as to favourable The filling with second conductivity type columns is etched so as to reduce filling defect in the groove；
    Second conductivity type columns include the first packed layer and the second packed layer, and first packed layer is covered in The side of the groove and lower surface, second packed layer are superimposed upon the surface of first packed layer；Institute State the first packed layer and second packed layer and all mixed for the doping of the second conduction type and first packed layer Miscellaneous concentration is more than 2 times of the doping concentration of second packed layer, makes second conductivity type columns described The second conduction type doping total amount at the different depth of groove is mainly determined by first packed layer, so as to press down Make the groove bottom width be less than top width side incline structure to the different depth of the groove at The second conduction type doping total amount influence, so as to improve the second conductive-type at the different depth of the groove Type adulterates the balance of the first conduction type doping total amount of total amount and adjacent first conductivity type columns.
  2. 2. superjunction devices as claimed in claim 1, it is characterised in that：First conductive type epitaxial layer is First conduction type silicon epitaxy layer, first packed layer are the second conduction type silicon epitaxy layer, and described second fills out It is the second conduction type silicon epitaxy layer, the second conductivity type polysilicon layer or deielectric-coating to fill layer.
  3. 3. superjunction devices as claimed in claim 1, it is characterised in that：The inclination angle of the side of the groove is 88.4 ~89 degree of degree.
  4. 4. superjunction devices as claimed in claim 1, it is characterised in that the doping concentration of first packed layer Meet：Second conductive type impurity total amount of first packed layer is worth for first, first conductivity type columns Total impurities be second value, it is described first value and the second value difference for the 3rd value, it is described 3rd value it is small In the 10% of the described first value, the 3rd value is less than the 10% of the second value.
  5. 5. superjunction devices as claimed in claim 1, it is characterised in that：Second conductivity type columns also include 3rd packed layer, the 3rd packed layer are the doping concentration of the doping of the second conduction type and the 3rd packed layer For less than the 1/2 of the doping concentration of first packed layer；3rd packed layer is located at the side of the groove Thickness be less than the groove bottom width 1/5, the 3rd packed layer is isolated from second packed layer Between the side of the groove and lower surface, for reducing the P between adjacent p-type post and N-type post Type impurity and N-type impurity are spread so as to reduce conducting resistance.
  6. 6. the superjunction devices as described in claim 1 or 5, it is characterised in that：Second conductivity type columns are also Including the 4th packed layer, the 4th packed layer is the doping of the second conduction type and the doping of the 4th packed layer Concentration is more than 2 times of the doping concentration of second packed layer, and the 4th packed layer is superimposed upon described second The surface of packed layer.
  7. 7. the superjunction devices as described in claim 1 or 4 or 5, it is characterised in that：First packed layer Doping concentration is more than 10 times of the doping concentration of second packed layer.
  8. 8. the superjunction devices as described in claim 1 or 4 or 5, it is characterised in that：First packed layer Volume is more than or equal to the half of the volume of whole second conductivity type columns；Or first packed layer covers The thickness covered in the lower surface of the groove is more than or equal to the 1/3 of the depth of the groove.
  9. 9. superjunction devices as claimed in claim 1, it is characterised in that：First conductive type epitaxial layer is Uniform Doped structure；
    Or the overlaying structure that first conductive type epitaxial layer is the first extension sublayer and the second extension sublayer, The first extension sublayer is Uniform Doped structure, and the second extension sublayer is Uniform Doped structure, described One extension sublayer is different with the doping concentration of the second extension sublayer；
    Or the doping concentration of first conductive type epitaxial layer is in the direction from lower surface to top surface It is upper to be distributed in incremental gradient distribution or the gradient successively decreased.
  10. 10. superjunction devices as claimed in claim 1, it is characterised in that：First conduction type is N-type, second Conduction type is p-type；Or first conduction type be p-type, the second conduction type is N-type.
  11. 11. a kind of manufacture method of superjunction devices, it is characterised in that comprise the following steps：
    Step 1: the first conductive type epitaxial layer is provided, formed with multiple ditches on the first conductive type epitaxial layer Groove, the side of the groove makes the bottom width of the groove be less than top width for incline structure, so as to favourable The filling with follow-up second conductivity type columns is etched so as to reduce filling defect in the groove；
    Step 2: the second conductivity type columns are filled in the trench, described second be filled in the groove Conductivity type columns and the first conduction type being made up of first conductive type epitaxial layer between the groove Post is alternately arranged composition super-junction structure；
    The fill process of second conductivity type columns is included as follows step by step：
    Step 21, the first packed layer of filling formation for the first time is carried out, first packed layer is covered in the ditch The side of groove and lower surface；
    Step 22, carry out second filling and form the second packed layer, second packed layer is superimposed upon described the The surface of one packed layer；
    First packed layer and second packed layer are all the doping of the second conduction type and first filling The doping concentration of layer is more than 2 times of the doping concentration of second packed layer, makes second conductivity type columns The second conduction type at the different depth of the groove adulterates total amount and mainly determined by first packed layer, So as to suppress difference of the side incline structure to the groove that the bottom width of the groove is less than top width The influence of the second conduction type doping total amount of depth, so as to improve second at the different depth of the groove Conduction type adulterates the flat of the first conduction type doping total amount of total amount and adjacent first conductivity type columns Weighing apparatus.
  12. 12. the manufacture method of superjunction devices as claimed in claim 11, it is characterised in that：Described first is conductive Type epitaxial layer is the first conduction type silicon epitaxy layer, and first packed layer is the second conduction type silicon epitaxy layer, Second packed layer is the second conduction type silicon epitaxy layer, the second conductivity type polysilicon layer or deielectric-coating.
  13. 13. the manufacture method of superjunction devices as claimed in claim 11, it is characterised in that first filling The doping concentration of layer meets：Second conductive type impurity total amount of first packed layer is the first value, described the The total impurities of one conductivity type columns are second value, and the difference of first value and the second value is the 3rd value, 3rd value is less than the 10% of the described first value, 10% of the 3rd value less than the second value.
  14. 14. the manufacture method of superjunction devices as claimed in claim 11, it is characterised in that step 2 it is described Also include before step 21 in the fill process of second conductivity type columns：
    Step 20, in the side of the groove and lower surface form the 3rd packed layer, the 3rd packed layer Doping concentration for the doping of the second conduction type and the 3rd packed layer is that the doping of first packed layer is dense Less than the 1/2 of degree；3rd packed layer is located at bottom of the thickness less than the groove of the side of the groove The 1/5 of width, the 3rd packed layer are isolated from side and the bottom table of second packed layer and the groove Between face, for reducing p type impurity between adjacent p-type post and N-type post and N-type impurity diffusion so as to dropping Low on-resistance.
  15. 15. the manufacture method of superjunction devices as claimed in claim 11, it is characterised in that step 2 it is described Also include after step 22 in the fill process of second conductivity type columns：
    Step 23, the 4th packed layer is formed on the surface of second packed layer, the 4th packed layer is the Two conduction types adulterate and the doping concentration of the 4th packed layer is the doping concentration of second packed layer More than 2 times.
CN201610402272.3A 2016-06-08 2016-06-08 Superjunction devices and its manufacture method Pending CN107482060A (en)

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