CN107734323B - A kind of algorithm checking system and method - Google Patents
A kind of algorithm checking system and method Download PDFInfo
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Abstract
It includes: computer, proof of algorithm module, time-sequence control module that the present invention, which provides a kind of algorithm checking system and method, the platform,.Computer exports test video image data and pumping frame period parameter, the refreshing frequency of display panel, output selection parameter to proof of algorithm module；Proof of algorithm module carries out pumping frame to test video image data according to frame period parameter is taken out, obtain the second video image data, the second video image data is handled also according to preset video graphics hardware algorithm, obtain third video image data, and according to output selection parameter, export after second or third video image data are encoded to time-sequence control module；Time-sequence control module controls the display panel the corresponding video image of display.The present invention does not need second or third video image data carrying out frequency reducing output, so that it may verify video graphics hardware algorithm to the practical improvement of display panel.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of algorithm checking system and methods.
Background technique
The manufactured display panel come out of existing display panel manufacturing process, display effect can more or less have one
A little defects, therefore video image data would generally be handled using some video graphics hardware algorithms (TFT_LCD algorithm),
To improve the display effect of these video datas on a display panel.And video graphics hardware algorithm is the video figure according to the end PC
As software algorithm setting, video graphics hardware algorithm has the processing of same video data with video image software algorithm identical
Effect, therefore, verify video graphics hardware algorithm before, it is also necessary to first verify video image software algorithm it is whether correct.
The device of video graphics hardware algorithm and video image software algorithm correctness is verified as shown in Figure 1, the end PC exports
Test video image data, (High Definition Multimedia Interface, high-definition multimedia connect HDMI
Mouthful)/DVI (Digital Visual Interface, i.e. digital visual interface) interface converts test video image data to
LVDS (Low-Voltage Differential Signaling low-voltage differential signal) data-signal is exported to FPGA
(Field-Programmable Gate Array, field programmable gate array) unit, FPGA unit receive LVDS data letter
After number, parsing obtains test video image data, and test video image data is carried out down conversion process, is down to display panel
Refreshing frequency is exported output video data to timing control by VB1 (V-BY-one) interface hereinafter, obtain output video data
Molding block, time-sequence control module is converted into corresponding driving control signal for video data is exported, and driving control signal is led to
It crosses signal connecting plate to export to display panel, controls the display panel the corresponding video image of display.Wherein, video graphics hardware is calculated
Method is arranged inside FPGA unit.By video graphics hardware algorithm or video image software algorithm to test video picture number
Test analysis is carried out according to being handled, then to the display effect of display panel, is judged by video graphics hardware algorithm or view
Whether the video data after frequency image software algorithm process meets the requirements, to judge video graphics hardware algorithm or video figure
Whether picture software algorithm is correct, achievees the purpose that verify video graphics hardware algorithm or video image software algorithm.
But as the size of TFT display panel is increasing, resolution ratio is higher and higher, corresponding the video data volume is
Growth at double, most of video graphics hardware algorithm and video image software algorithm are all verification the verifying results under static state.
At present on the market support UD (Ultra High Definition, high-resolution, have 3840 × 2160 (4K ×
2K, 8K) and the above resolution ratio) display technology video graphics hardware algorithm and video image software algorithm, corresponding verifying
Platform is all that frequency reducing (frequency for reducing test video image data is lower than the refreshing frequency of display panel) is exported afterwards to timing control
Molding block, is controlled the display panel by time-sequence control module and is shown, is able to validate only video graphics hardware algorithm or view in this way
Whether the finally obtained data of frequency image software algorithm are correct, cannot verify video graphics hardware algorithm or video image completely
Software algorithm is to the practical improvement of display panel, video image algorithm especially relevant to display panel charge rate.
Summary of the invention
In order to solve the above technical problems, the present invention provides a kind of algorithm checking system and method, video image can be verified
Practical improvement of the hardware algorithm to display panel.
The present invention provides a kind of algorithm checking system, comprising: computer, proof of algorithm module, time-sequence control module；
The computer is connect with the proof of algorithm module communication, and being used for will according to preset video image software algorithm
Raw video image data are handled, and obtain the first video image data, and by first video image data or institute
It states raw video image data to export as test video image data to the proof of algorithm module, will also be shown that parameter information
It exports to the proof of algorithm module；Wherein, the display parameter information includes: to take out the refreshing of frame period parameter, display panel
Frequency, output selection parameter；
The proof of algorithm module is used for the time-sequence control module communication connection according to the pumping frame period parameter
The test video image data is carried out to take out frame processing, the second video image data is obtained, also according to preset video image
Hardware algorithm handles second video image data, obtains third video image data, and select according to the output
Parameter is selected, second video image data or the third video image data are exported according to the refreshing frequency to institute
State time-sequence control module；
The time-sequence control module, for according to second video image data or the third video image number
According to controlling the display panel and show corresponding video image.
Preferably, further includes: interface module；
The computer is connect by the interface module with the proof of algorithm module communication, is used for the test video
Image data and the display parameter information are exported to the interface module；
The interface module, for being obtained after being encoded the test video image data and the display parameter information
It exports to the first data-signal, and by first data-signal to the proof of algorithm module；
The proof of algorithm module is also used to receive first data-signal, and is decoded to obtain the survey
Try video image data and the display parameter information, and by second video image data or the third video image
Data are encoded to obtain the second data-signal according to the refreshing frequency, and by second data-signal export to it is described when
Sequence control module；
The time-sequence control module is also used to for second data-signal being decoded, obtains the second video figure
As data or the third video image data.
Preferably, the computer includes:
Digital Video Out Port/high-definition multimedia output port；
USB PORT COM；
Host computer is exported with the USB PORT COM, the Digital Video Out Port/high-definition multimedia respectively
Port communication connection, for the test video image data to be passed through the more matchmakers of Digital Video Out Port/fine definition
The output of body output port exports the display parameter information by the USB PORT COM.
Preferably, the interface module includes: serial line interface, digital visual interface/high-definition multimedia interface；
The serial line interface is converted into correspondence for receiving the display parameter information, and by the display parameter information
Data signals of serial output；
Digital visual interface/the high-definition multimedia interface, for receiving the test video image data, and will
The test video image data is encoded to obtain the output of the first Low Voltage Differential Signal.
Preferably, the proof of algorithm module includes: FPGA unit, further includes internal storage location；
The FPGA unit include video input decoding unit, serial-port resolution unit, read-write controller unit, at algorithm
Manage unit, video exports coding unit；
The video input decoding unit, with the digital visual interface/high-definition multimedia interface and the read-write
Controller unit communication connection is carried out for receiving first Low Voltage Differential Signal, and by first Low Voltage Differential Signal
Decoding, obtains the test video image data, and the test video image data is exported to the read-write controller list
Member；
The serial-port resolution unit is connect, for receiving with the serial line interface and the read-write controller unit communications
The data signals of serial, and parse the data signals of serial, obtains the display parameter information, and by the display parameters
Information is exported to the read-write controller unit；Wherein, the display parameter information further include: the first read-write frequency, second are read
Write frequency；
The algorithm process unit is connect with the read-write controller unit communications, for hard according to the video image
Part algorithm handles second video image data, obtains the third video image data, and the third is regarded
Frequency image data is exported to the read-write controller unit；
The read-write controller unit connect with the internal storage location and the video exports coding unit communications, is used for
According to the pumping frame period parameter, the test video image data is carried out to take out frame processing, obtains second video image
Data, and second video image data and the third video image data are deposited into according to first read-write frequency
The internal storage location, and second video image data is read from the internal storage location according to second read-write frequency, and
Second video image data is exported to the algorithm process unit；
The read-write controller unit is also used to according to the output selection parameter, according to institute from the internal storage location
It states refreshing frequency and reads second video image data or the third video image data, and by the second video figure
As data or the third video image data are exported to the video exports coding unit；
The video exports coding unit is used for the time-sequence control module communication connection by the second video figure
As data or the third video image data are encoded to obtain the second Low Voltage Differential Signal, and by second low voltage difference
Sub-signal is exported to the time-sequence control module.
Preferably, the read-write controller unit is DDR3 controller, and the internal storage location is DDR3 memory grain, packet
It includes:
First internal storage location, for storing second video image data；
Second internal storage location, for storing the third video image data；
Also, first read-write frequency and second read-write frequency are respectively less than the frequency of the test video image data
Rate.
The present invention also provides a kind of proof of algorithm methods, include the following steps:
Computer exports test video image data and display parameter information to proof of algorithm module；Wherein, the survey
Try video image data be the first video image data or raw video image data, first video image data according to
The raw video image data are handled to obtain by preset video image software algorithm, the display parameter information packet
It includes: taking out frame period parameter, the refreshing frequency of display panel, output selection parameter；
The proof of algorithm module take out at frame to the test video image data according to the pumping frame period parameter
Reason, obtain the second video image data, also according to preset video graphics hardware algorithm to second video image data into
Row processing, obtains third video image data, and according to the output selection parameter, by second video image data or
The third video image data is exported according to the refreshing frequency to time-sequence control module；
The time-sequence control module is according to second video image data or the third video image data, control
The display panel shows corresponding video image.
Preferably, " computer exports test video image data and display parameter information to proof of algorithm to the step
Module " includes:
The computer exports the test video image data and the display parameter information to interface module；
Serial line interface in the interface module receives the display parameter information, and the display parameter information is converted
It exports for corresponding data signals of serial to the proof of algorithm module；
Digital visual interface/high-definition multimedia interface in the interface module receives the test video picture number
According to, and encoded the test video image data to obtain the first Low Voltage Differential Signal and be exported to the proof of algorithm mould
Block.
Preferably, " the proof of algorithm module is according to the pumping frame period parameter to the test video figure for the step
As data carry out taking out frame processing, the second video image data is obtained, also according to preset video graphics hardware algorithm to described the
Two video image data are handled, and third video image data are obtained, and according to the output selection parameter, by described second
Video image data or the third video image data are exported according to the refreshing frequency to time-sequence control module " include:
Video input decoding unit receives first Low Voltage Differential Signal, and first Low Voltage Differential Signal is carried out
Decoding, obtains the test video image data, and the test video image data is exported to read-write controller unit；
Serial-port resolution unit receives the data signals of serial, and parses the data signals of serial, obtains the display
Parameter information, and the display parameter information is exported to the read-write controller unit；Wherein, the display parameter information is also
It include: the first read-write frequency, the second read-write frequency；
The read-write controller unit carries out pumping frame according to the pumping frame period parameter, by the test video image data
Processing, obtains second video image data, and second video image data is deposited according to first read-write frequency
Enter to internal storage location, and reads second video image data from the internal storage location according to second read-write frequency, and
Second video image data is exported to algorithm process unit；
The algorithm process unit according to the video graphics hardware algorithm to second video image data at
Reason, obtains the third video image data, and the third video image data is exported to the read-write controller unit；
The third video image data is deposited into institute according to first read-write frequency by the read-write controller unit
State internal storage location；
The read-write controller unit is according to the output selection parameter, according to the refreshing frequency from the internal storage location
Rate reads second video image data or the third video image data, and by second video image data or
Third video image data described in person is exported to video exports coding unit；
The video exports coding unit by second video image data or the third video image data into
Row coding obtains the second Low Voltage Differential Signal, and second Low Voltage Differential Signal is exported to the time-sequence control module.
Preferably, second video image data is stored in the first internal storage location by the read-write controller unit, by institute
It states third video image data and is stored in the second internal storage location；
Also, first read-write frequency and second read-write frequency are respectively less than the frequency of the test video image data
Rate.
The invention has the following beneficial effects: taking out frame processing by carrying out to test video image data, obtains the
Two video image data, then the second video image data is handled according to preset video graphics hardware algorithm, obtain
Three video image data, according to output selection parameter, by the second video image data or third video image data according to brush
New frequency is output to time-sequence control module after being encoded.When time-sequence control module controls the display panel the second video image of display
The corresponding video image of data carries out test analysis to the display effect of display panel, it can be determined that the video image in computer
Whether software algorithm is correct；When time-sequence control module controls the display panel the corresponding video figure of display third video image data
Picture carries out test analysis to the display effect of display panel, judges practical improvement of the video graphics hardware algorithm to display panel
Whether effect reaches expected requirement, whether correct can verify preset video graphics hardware algorithm.It does not need the second video
Image data and third video image data carry out frequency reducing output, but are tested according to the practical refreshing frequency of display panel
Card, can verify video graphics hardware algorithm to the practical improvement of display panel.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the functional block diagram of the algorithm checking system in background technique provided by the invention.
Fig. 2 is the functional block diagram of algorithm checking system provided by the invention.
Fig. 3 is the functional block diagram of computer provided by the invention.
Fig. 4 is the functional block diagram of interface module provided by the invention.
Fig. 5 is the functional block diagram of proof of algorithm module provided by the invention.
Fig. 6 is the time division multiplexing timing of the DDR3 controller of another embodiment of proof of algorithm method provided by the invention
Figure.
Fig. 7 is the flow chart of the another embodiment of proof of algorithm method provided by the invention.
Specific embodiment
The present invention provides a kind of algorithm checking system, as shown in Fig. 2, comprising: 1 proof of algorithm module 3 of computer, timing control
Molding block 4.
Computer 1 and 3 communication connection of proof of algorithm module, for according to preset video image software algorithm by original video
Image data is handled, and obtains the first video image data, and by the first video image data or raw video image number
It exports according to as test video image data to proof of algorithm module 3, will also be shown that parameter information is exported to proof of algorithm module
3；Wherein, display parameter information includes: to take out frame period parameter, the refreshing frequency of display panel, output selection parameter.
Proof of algorithm module 3 and 4 communication connection of time-sequence control module are used for according to pumping frame period parameter to test video figure
It is handled as data carry out pumping frame, obtains the second video image data, regarded also according to preset video graphics hardware algorithm to second
Frequency image data is handled, and third video image data is obtained, and according to output selection parameter, by the second video image data
Or third video image data is exported according to refreshing frequency to time-sequence control module 4.
Time-sequence control module 4 is used to control display surface according to the second video image data or third video image data
Plate shows corresponding video image.Specifically, time-sequence control module 4 is by the second video image data or third video image
Data are converted into corresponding driving control signal and export to display panel, control the display panel and are shown.Wherein, timing control
Pass through signal connecting plate communication connection between module 4 and display panel.
Further, as shown in Fig. 2, algorithm checking system further include: interface module 2.
Computer 1 is connect by interface module 2 with proof of algorithm module communication, is used for test video image data and display
Parameter information is exported to interface module 2.
Interface module 2 is for obtaining the first data letter after being encoded test video image data and display parameter information
Number, and the first data-signal is exported to proof of algorithm module 3.
Proof of algorithm module 3 is also used to receive the first data-signal, and the first data-signal its be decoded and tested
Video image data and display parameter information, and by the second video image data or third video image data according to refreshing frequency
Rate is encoded to obtain the second data-signal, and the second data-signal is exported to time-sequence control module 4.
Time-sequence control module 4 is also used to for the second data-signal being decoded, and obtains the second video image data or
Three video image data.
In general, taking out frame period parameter is time parameter, i.e., per at regular intervals just to raw video image data
Pumping frame is carried out, the data frame for corresponding to the period in raw video image data is obtained.
For example, the data for extracting a frame need 10 milliseconds of time, taking out frame period parameter is 60 milliseconds, in first 10 milli
Second has extracted the data of first frame as the second video image data and then by the data conduct of 60 milliseconds of extraction next frames
Second video image data.
It, can be by display color analyzer (for example, the color of CA310 model after display panel shows video image
Analyzer), test analysis is carried out to the display effect of display panel.The test video image data that computer 1 exports can pass through
Video image software algorithm is handled (for example, MATLAB or VC software is handled), to improve raw video image data aobvious
Show the display effect on panel, it, can be right when display panel it is shown that video image corresponding to the second video image data
Display panel carries out test analysis, judges whether display effect reaches expected requirement, if having reached expected requirement, sentences
Disconnected video image software algorithm is correct.
When the video image software algorithm in computer 1 is correct, then the soft method of the software can be led in proof of algorithm module 2
Hardware circuit is crossed to realize, that is to say video graphics hardware algorithm, raw video image data are calculated by video graphics hardware
The processing of method can also improve its display effect on a display panel, accordingly it is also possible to be surveyed by display color analyzer
The display effect of examination analysis third video image data on a display panel, judges whether display effect reaches expected requirement,
If having reached expected requirement, it may determine that video graphics hardware algorithm is correct.
In addition, the second video image data and third video image data are all the data taken out after frame, regarded relative to test
Frequency image data is much smaller, exports after the second video image data or third video image data are encoded to timing
Control module 4 carries out control by it and shows, do not have too big burden.
Further, as shown in figure 3, computer 1 includes: Digital Video Out Port/high-definition multimedia output port
12, USB (Universal Serial Bus, universal serial bus) PORT COM, host computer 11.
Host computer 11 respectively with USB PORT COM 13, Digital Video Out Port/high-definition multimedia output port 12
Communication connection, for test video image data to be passed through Digital Video Out Port/high-definition multimedia output port 12
Output exports display parameter information by USB PORT COM 13.
Further, as shown in figure 4, interface module 2 includes: serial line interface 22, the more matchmakers of digital visual interface/fine definition
Body interface 21.Wherein, digital visual interface that is to say DVI ((Digital Visual Interface), high-definition multimedia
Interface that is to say HDMI (High Definition Multimedia Interface).
Serial line interface 22 converts corresponding serial data for display parameter information and believes for receiving display parameter information
Number output.Serial line interface 22 believes the serial data that the display parameter information that USB PORT COM 13 exports is converted into Transistor-Transistor Logic level
Number.
Digital visual interface/high-definition multimedia interface 21 is regarded for receiving test video image data, and by test
Frequency image data is encoded to obtain corresponding first Low Voltage Differential Signal output.Low Voltage Differential Signal, that is, LVDS (Low-
Voltage Differential Signaling) signal.
Further, as shown in figure 5, proof of algorithm module 3 includes: internal storage location 32, FPGA unit 31.
FPGA unit 31 includes video input decoding unit 311, serial-port resolution unit 312, read-write controller unit
313, algorithm process unit 314, video exports coding unit 315.
Video input decoding unit 311 and digital visual interface/high-definition multimedia interface 21 and read-write controller list
First 313 communication connections, for receiving the first Low Voltage Differential Signal, and the first Low Voltage Differential Signal are decoded, are tested
Video image data, and test video image data is exported to read-write controller unit 313.
Serial-port resolution unit 312 and 313 communication connection of serial line interface 22 and read-write controller unit, for receiving serial ports number
It is believed that number, and data signals of serial is parsed, display parameter information is obtained, and display parameter information is exported to read-write controller list
Member 313；Wherein, display parameter information further include: the first read-write frequency, the second read-write frequency.
Algorithm process unit 314 and 313 communication connection of read-write controller unit, for according to video graphics hardware algorithm pair
Second video image data is handled, and obtains third video image data, and third video image data is exported to read-write
Controller unit 313.
Read-write controller unit 313 and 315 communication connection of internal storage location 32 and video exports coding unit, for according to pumping
Test video image data is carried out taking out frame processing, obtains the second video image data by frame period parameter, and by the second video figure
As data and third video image data are deposited into internal storage location 32 according to the first read-write frequency, and according to the second read-write frequency from
Internal storage location 32 reads the second video image data, and the second video image data is exported to algorithm process unit 314.Read-write
Controller unit 313 is also used to read the second video figure according to refreshing frequency from internal storage location 32 according to output selection parameter
As data perhaps third video image data and export the second video image data or third video image data to video
Exports coding unit 315.
Video exports coding unit 315 and 4 communication connection of time-sequence control module, for by the second video image data or
Third video image data is encoded to obtain the second Low Voltage Differential Signal, and the second Low Voltage Differential Signal is exported to timing control
Molding block 4.
Preferably, logical by VB1 (V-BY-one) interface between video exports coding unit 315 and time-sequence control module 4
Second Low Voltage Differential Signal is that corresponding data are transmitted according to VB1 protocol translation by news connection, VB1 interface.
Further, read-write controller unit 313 is DDR3 controller, and internal storage location 32 is DDR3 memory grain, memory
Unit 32 includes: the first internal storage location and the second internal storage location.
First internal storage location is for storing second video image data；Second internal storage location is for storing the third
Video image data.For example, the first internal storage location can be the a-quadrant of DDR3 memory grain, the second internal storage location be can be
The B area of DDR3 memory grain.
Output selection parameter can be the physical address of the first internal storage location or the physical address of the second internal storage location,
If output selection parameter is the physical address of the first internal storage location, read-write controller unit 313 then reads the second video
Image data output, conversely, then read-write controller unit 313 reads the output of third video image data.
Further, the first read-write frequency and the second read-write frequency are respectively less than the frequency of test video image data.
The present invention also provides a kind of proof of algorithm methods comprising following step:
Computer 1 exports test video image data and display parameter information to proof of algorithm module 3；Wherein, it tests
Video image data is the first video image data or raw video image data, and the first video image data is according to preset
Raw video image data are handled to obtain by video image software algorithm, display parameter information include: take out frame period parameter,
Refreshing frequency, the output selection parameter of display panel；
Proof of algorithm module 3 carries out test video image data to take out frame processing according to frame period parameter is taken out, and obtains second
Video image data handles the second video image data also according to preset video graphics hardware algorithm, obtains third
Video image data, and according to output selection parameter, by the second video image data or third video image data according to brush
New rate-adaptive pacemaker is to time-sequence control module 4；
Time-sequence control module 4 controls the display panel aobvious according to the second video image data or third video image data
Show corresponding video image.
Further, " computer exports test video image data and display parameter information to proof of algorithm mould to step
Block " includes:
Computer 1 exports test video image data and the display parameter information to interface module 2；
Serial line interface 22 in interface module 2 receives display parameter information, and converts display parameter information to corresponding
Data signals of serial is exported to proof of algorithm module 3；
Digital visual interface/high-definition multimedia interface 21 in interface module 2 receives test video image data, and
It is encoded the test video image data to obtain corresponding first Low Voltage Differential Signal and be exported to proof of algorithm module 3.
Further, " proof of algorithm module 3 carries out pumping frame to test video image data according to frame period parameter is taken out to step
Processing, obtains the second video image data, carries out also according to preset video graphics hardware algorithm to the second video image data
Processing obtains third video image data, and according to output selection parameter, by the second video image data or third video figure
Include: as data are exported according to refreshing frequency to time-sequence control module 4 "
Video input decoding unit 311 receives the first Low Voltage Differential Signal, and the first Low Voltage Differential Signal is decoded,
Test video image data is obtained, and test video image data is exported to read-write controller unit 313.
Serial-port resolution unit 312 receives data signals of serial, and parses data signals of serial, obtains display parameter information,
And display parameter information is exported to read-write controller unit 313；Wherein, display parameter information further include: the first read-write frequency,
Second read-write frequency；
Test video image data is carried out taking out frame processing, be obtained by read-write controller unit 313 according to frame period parameter is taken out
Second video image data, and the second video image data is deposited into internal storage location 32 according to the first read-write frequency, and according to
Second read-write frequency reads the second video image data from internal storage location 32, and the second video image data is exported to algorithm
Manage unit 314；
Algorithm process unit 314 is handled the second video image data according to video graphics hardware algorithm, obtains
Three video image data, and third video image data is exported to read-write controller unit 313；
Third video image data is deposited into internal storage location 32 according to the first read-write frequency by read-write controller unit 313；
Read-write controller unit 313 reads second according to refreshing frequency from internal storage location 32 according to output selection parameter
Video image data perhaps third video image data and exports the second video image data or third video image data
To video exports coding unit 315；
Second video image data or third video image data are encoded to obtain by video exports coding unit 315
Second Low Voltage Differential Signal, and the second Low Voltage Differential Signal is exported to time-sequence control module 4.
Further, the second video image data is stored in the first internal storage location by read-write controller unit 313, and third is regarded
Frequency image data is stored in the second internal storage location；
Also, the first read-write frequency and the second read-write frequency are respectively less than the frequency of test video image data.
As shown in fig. 6, wherein T represents original video in another embodiment of proof of algorithm method provided by the invention
DDR3 memory grain is written in the corresponding each frame data of original video source by the period in source and output video source, i.e. DDR3 controller
Needed for the time be T.Corresponding grey parts indicate that DDR3 controller was needed the period corresponding one in original video source
Frame data are written in DDR3 memory grain, and white portion indicates the data frame lost, and do not need to be written to DDR3 memory grain
In, after frame losing number is also corresponding with frame period parameter is taken out, such as a frame data are written into DDR3 memory grain in DDR3 controller, then
Next frame data are written in the time for being spaced 6T, then the intermediate data for also having lost 6 frames.
TFT_LCD algorithm time corresponding white portion indicates that DDR3 controller is not read and saves in DDR3 memory grain
Data, grey parts indicate that DDR3 controller will read the data in DDR3 memory grain, in one frame data of every write-in to DDR3
After in memory grain, it just can read the data in DDR3 memory grain, then the data of reading are exported to algorithm process unit 314
In, algorithm process unit 314 is handled according to video graphics hardware algorithm, and video graphics hardware algorithm will be passed through after having handled
The data of processing are written in DDR3 memory grain by DDR3 controller.Wherein, DDR3 controller is from DDR3 memory grain
Reading data needs frequency reducing to read, and corresponding frequency reducing parameter is corresponding with the refreshing frequency of display panel that computer 1 is transmitted through, according to
The refreshing frequency of display panel can determine within the unit time, need to export how many data to time-sequence control module 4.
Exporting the corresponding grey parts of video source indicates that DDR3 controller reads the data in DDR3 memory grain, DDR3 control
Device processed ceaselessly reads the data in DDR3 memory grain, the corresponding core position of read data by computer 1 be transmitted through Lai
It exports selection parameter to determine, is the data that selection output is crossed without video graphics hardware algorithm process, or pass through video figure
As the processed data of hardware algorithm.
As shown in fig. 7, host computer 11 passes through serial interface in the another embodiment of proof of algorithm method provided by the invention
Mouth 22 exports display parameter information to FPGA unit 31, and FPGA unit 31 parses serial line interface timing, obtains display parameter information
In pumping frame period parameter, output video source parameter, refreshing frequency, host computer 11 output by video image software algorithm handle
The first video image data crossed, FPGA unit 31 carry out pumping frame to the first video image data and handle to obtain the second video image
Data, according to output selection parameter, selection the second video image data of output to time-sequence control module 4；By to display panel
Display effect carry out test analysis, judge whether the display effect of the second video image data on a display panel reaches expected
It is required that judge whether the software algorithm of host computer 11 is correct.
When the software algorithm of host computer 11 is correct, then by the video graphics hardware algorithm in FPGA unit 31 according to correspondence
Video image software algorithm realize so that effect of the raw video image data Jing Guo video graphics hardware algorithm process with
The effect of video image software algorithm processing is consistent.The output of host computer 11 is without by the original of video image software algorithm processing
Video image data is to FPGA unit 31；FPGA unit 31 carries out pumping frame to raw video image data and handles to obtain the second video
Image data handles the second video image data further according to preset video graphics hardware algorithm, obtains third video
Image data, according to output selection parameter, selection output third video image data；The display effect of display panel is surveyed
Examination analysis processes the display effect of video image data on a display screen by video image software algorithm by comparison, tests
Whether the video graphics hardware algorithm for demonstrate,proving FPGA unit 31 is correct.
In conclusion algorithm checking system provided by the invention and proof of algorithm method, by test video picture number
According to pumping frame processing is carried out, the second video image data is obtained, then the second video image data is hard according to preset video image
Part algorithm is handled, and third video image data is obtained, according to output selection parameter, by the second video image data or the
Three video image data are output to time-sequence control module 4 after being encoded according to refreshing frequency.The control display of time-sequence control module 4
The corresponding video image of the second video image data of Display panel, the display by display screen color analysis instrument to display panel
Effect carries out test analysis, it can be determined that whether the video image software algorithm in computer 1 is correct.
Time-sequence control module 4 controls the display panel the corresponding video image of display third video image data, passes through display
Shield color analysis instrument and test analysis is carried out to the display effect of display panel, judges video graphics hardware algorithm to display panel
Practical improvement whether reach expected requirement, so that whether verify preset video graphics hardware algorithm correct.It does not need
Second video image data or third video image data are subjected to frequency reducing output, so that it may verify video graphics hardware algorithm
To the practical improvement of display panel.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be said that
Specific implementation of the invention is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs, exist
Under the premise of not departing from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to of the invention
Protection scope.
Claims (10)
1. a kind of algorithm checking system characterized by comprising computer, proof of algorithm module, time-sequence control module；
The computer is connect with the proof of algorithm module communication, and being used for will be original according to preset video image software algorithm
Video image data is handled, and obtains the first video image data, and by first video image data or the original
Beginning video image data is exported as test video image data to the proof of algorithm module, will also be shown that parameter information exports
To the proof of algorithm module；Wherein, the display parameter information include: take out frame period parameter, the refreshing frequency of display panel,
Export selection parameter；
The proof of algorithm module is used for according to the pumping frame period parameter with the time-sequence control module communication connection to institute
It states test video image data to carry out taking out frame processing, the second video image data is obtained, also according to preset video graphics hardware
Algorithm handles second video image data, obtains third video image data, and select to join according to the output
Number, by second video image data or the third video image data according to the refreshing frequency export to it is described when
Sequence control module；
The time-sequence control module, for according to second video image data or the third video image data, control
It makes the display panel and shows corresponding video image.
2. algorithm checking system according to claim 1, which is characterized in that further include: interface module；
The computer is connect by the interface module with the proof of algorithm module communication, is used for the test video image
Data and the display parameter information are exported to the interface module；
The interface module, for obtaining after being encoded the test video image data and the display parameter information
One data-signal, and first data-signal is exported to the proof of algorithm module；
The proof of algorithm module is also used to receive first data-signal, and is decoded to obtain the test view
Frequency image data and the display parameter information, and by second video image data or the third video image data
It is encoded to obtain the second data-signal according to the refreshing frequency, and second data-signal is exported to the timing control
Molding block；
The time-sequence control module is also used to for second data-signal being decoded, obtains the second video image number
According to or the third video image data.
3. algorithm checking system according to claim 2, which is characterized in that the computer includes:
Digital Video Out Port/high-definition multimedia output port；
USB PORT COM；
Host computer, respectively with the USB PORT COM, the Digital Video Out Port/high-definition multimedia output port
Communication connection, for the test video image data is defeated by the Digital Video Out Port/high-definition multimedia
Exit port output exports the display parameter information by the USB PORT COM.
4. algorithm checking system according to claim 3, which is characterized in that the interface module includes: serial line interface, number
Word video interface/high-definition multimedia interface；
The serial line interface is converted into corresponding string for receiving the display parameter information, and by the display parameter information
Mouth data-signal output；
Digital visual interface/the high-definition multimedia interface, for receiving the test video image data, and will be described
Test video image data is encoded to obtain the output of the first Low Voltage Differential Signal.
5. algorithm checking system according to claim 4, which is characterized in that the proof of algorithm module includes: FPGA mono-
Member further includes internal storage location；
The FPGA unit includes video input decoding unit, serial-port resolution unit, read-write controller unit, algorithm process list
Member, video exports coding unit；
The video input decoding unit, with the digital visual interface/high-definition multimedia interface and the Read-write Catrol
The connection of device unit communications, is decoded for receiving first Low Voltage Differential Signal, and by first Low Voltage Differential Signal,
The test video image data is obtained, and the test video image data is exported to the read-write controller unit；
The serial-port resolution unit is connect with the serial line interface and the read-write controller unit communications, described for receiving
Data signals of serial, and parse the data signals of serial, obtains the display parameter information, and by the display parameter information
It exports to the read-write controller unit；Wherein, the display parameter information further include: the first read-write frequency, the second read-write frequency
Rate；
The algorithm process unit is connect with the read-write controller unit communications, for being calculated according to the video graphics hardware
Method handles second video image data, obtains the third video image data, and by the third video figure
As data are exported to the read-write controller unit；
The read-write controller unit is connect with the internal storage location and the video exports coding unit communications, is used for basis
The test video image data is carried out taking out frame processing, obtains second video image data by the pumping frame period parameter,
And second video image data and the third video image data are deposited into according to first read-write frequency described
Internal storage location, and read second video image data from the internal storage location according to second read-write frequency, and by institute
The second video image data is stated to export to the algorithm process unit；
The read-write controller unit is also used to according to the output selection parameter, according to the brush from the internal storage location
New frequency reads second video image data or the third video image data, and by the second video image number
According to or the third video image data export to the video exports coding unit；
The video exports coding unit is used for the time-sequence control module communication connection by the second video image number
According to or the third video image data encoded to obtain the second Low Voltage Differential Signal, and second low-voltage differential is believed
Number output is to the time-sequence control module.
6. algorithm checking system according to claim 5, which is characterized in that the read-write controller unit is DDR3 control
Device, the internal storage location are DDR3 memory grain comprising:
First internal storage location, for storing second video image data；
Second internal storage location, for storing the third video image data；
Also, first read-write frequency and second read-write frequency are respectively less than the frequency of the test video image data.
7. a kind of proof of algorithm method, which is characterized in that include the following steps:
Computer exports test video image data and display parameter information to proof of algorithm module；Wherein, the test view
Frequency image data is the first video image data or raw video image data, and first video image data is according to default
Video image software algorithm the raw video image data are handled to obtain, the display parameter information include: take out
Frame period parameter, the refreshing frequency of display panel, output selection parameter；
The proof of algorithm module carries out the test video image data according to the pumping frame period parameter to take out frame processing, obtains
To the second video image data, also according to preset video graphics hardware algorithm to second video image data at
Reason, obtains third video image data, and according to the output selection parameter, by second video image data or described
Third video image data is exported according to the refreshing frequency to time-sequence control module；
The time-sequence control module is according to second video image data or the third video image data, described in control
Display panel shows corresponding video image.
8. proof of algorithm method according to claim 7, which is characterized in that " computer is by test video image for the step
Data and display parameter information are exported to proof of algorithm module " include:
The computer exports the test video image data and the display parameter information to interface module；
Serial line interface in the interface module receives the display parameter information, and converts the display parameter information to pair
The data signals of serial answered is exported to the proof of algorithm module；
Digital visual interface/high-definition multimedia interface in the interface module receives the test video image data,
And it is encoded the test video image data to obtain the first Low Voltage Differential Signal and be exported to the proof of algorithm module.
9. proof of algorithm method according to claim 8, which is characterized in that step " the proof of algorithm module root
The test video image data is carried out according to the pumping frame period parameter to take out frame processing, obtains the second video image data, also
Second video image data is handled according to preset video graphics hardware algorithm, obtains third video image number
According to, and according to the output selection parameter, by second video image data or the third video image data according to
The refreshing frequency is exported to time-sequence control module " include:
Video input decoding unit receives first Low Voltage Differential Signal, and first Low Voltage Differential Signal is solved
Code, obtains the test video image data, and the test video image data is exported to read-write controller unit；
Serial-port resolution unit receives the data signals of serial, and parses the data signals of serial, obtains the display parameters
Information, and the display parameter information is exported to the read-write controller unit；Wherein, the display parameter information is also wrapped
It includes: the first read-write frequency, the second read-write frequency；
The read-write controller unit take out at frame according to the pumping frame period parameter, by the test video image data
Reason, obtains second video image data, and second video image data is stored according to first read-write frequency
Second video image data is read from the internal storage location to internal storage location, and according to second read-write frequency, and will
Second video image data is exported to algorithm process unit；
The algorithm process unit is handled second video image data according to the video graphics hardware algorithm, is obtained
It exports to the third video image data, and by the third video image data to the read-write controller unit；
The third video image data is deposited into described by the read-write controller unit according to first read-write frequency
Memory cell；
The read-write controller unit is read from the internal storage location according to the refreshing frequency according to the output selection parameter
Take the second video image data perhaps third video image data and by second video image data or institute
Third video image data is stated to export to video exports coding unit；
The video exports coding unit compiles second video image data or the third video image data
Code obtains the second Low Voltage Differential Signal, and second Low Voltage Differential Signal is exported to the time-sequence control module.
10. proof of algorithm method according to claim 9, which is characterized in that the read-write controller unit is by described
Two video image data are stored in the first internal storage location, and the third video image data is stored in the second internal storage location；
Also, first read-write frequency and second read-write frequency are respectively less than the frequency of the test video image data.
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| CN108535899B (en) * | 2018-04-13 | 2021-06-01 | Tcl华星光电技术有限公司 | TFT-LCD data stream detection method, electronic device and computer readable storage medium |
| CN108900830B (en) * | 2018-05-25 | 2020-09-18 | 南京理工大学 | Platform for verifying accuracy of infrared video image processing algorithm |
| CN111090405B (en) * | 2019-12-24 | 2024-06-07 | 北京航天飞腾装备技术有限责任公司 | Simulated flying and bullet throwing process device for algorithm verification |
| CN111292668B (en) * | 2020-03-30 | 2022-09-27 | Tcl华星光电技术有限公司 | Method and device for adjusting refresh frequency of display panel |
| CN111641823B (en) * | 2020-05-06 | 2021-08-27 | 深圳市爱协生科技有限公司 | MIPI interface-based image algorithm verification system |
| CN112486440B (en) * | 2020-11-05 | 2024-03-19 | Tcl华星光电技术有限公司 | Algorithm verification method and algorithm verification system |
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Address after: No.9-2 Tangming Avenue, Guangming New District, Shenzhen, Guangdong 518000 Patentee after: TCL China Star Optoelectronics Technology Co.,Ltd. Address before: No.9-2 Tangming Avenue, Guangming New District, Shenzhen, Guangdong 518000 Patentee before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |