CN112669738A - Display data debugging system and display data debugging method - Google Patents
Display data debugging system and display data debugging method Download PDFInfo
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Abstract
The application discloses a display data debugging system and a display data debugging method, which comprise an upper computer, a field programmable gate array, a display panel to be debugged and a color analyzer; the control instruction sent by the upper computer controls the field programmable logic gate array to output the video data with the corresponding bit width, the bit width limitation of the PC display card on the video data is removed, the using quantity of the adapter plate is reduced, and the debugging of the display data is more convenient and efficient.
Description
Technical Field
The application relates to the technical field of display, in particular to a display data debugging system and a display data debugging system.
Background
After the refresh rate, resolution and size of the display panel are improved, the internal routing density length is increased, the parasitic capacitance and the resistance-capacitance (RC delay) are more serious, and the resolution of high-end display products is generally required to be very high, so that the charging rate of each sub-pixel is inconsistent, and the display effect of the panel is not uniform.
In order to solve the above problems, each panel manufacturer adopts a charging compensation function algorithm added in a time sequence controller (Tcon) or a System On Chip (SOC, System-On-a-Chip), and when the charging compensation algorithm is started, a data compensation table corresponding to the display panel needs to be written in, so that real-time compensation processing can be performed On video signals, and the image quality of screen display is improved.
The working flow of the existing charging compensation algorithm debugging system is as follows:
a) a PC (Personal Computer) video card outputs 4K (corresponding resolution) 8bits signals, and the signals are transferred and output through a DP (display port), converted into DVI signals through a DP/DVI (Digital Visual Interface) jig board, and control an FPGA (Field Programmable Gate Array) to output 4K 8bits LVDS (Low-Voltage Differential Signaling).
b) The signal transfer board converts the LVDS into a V-by-one (digital interface standard developed specially for image transmission) signal and transmits the V-by-one signal to a time sequence controller (Tcon IC) on a C-board (C-board), and the Tcon IC transmits the V-by-one signal to a Data driver (Data IC) and finally displays a picture on a liquid crystal panel.
c) The color analyzer performs optical measurement of the display image, and the measured data is returned to the PC.
d) And the PC stores and processes the data, and the display card outputs signals again to repeat the process, so that the whole debugging action is finally realized, and a debugging data table is produced.
According to the working process, the resolution and the signal bit depth of the output signal of the debugging system are limited by the configuration of the PC display card, namely the front-end PC display card is configured to be 4K 8bits, and the display panel cannot display the picture of 8K 10bits, so that a computer with corresponding resolution needs to be found when a debugging platform is set up during actual debugging.
The DP/DVI adapter plate is used for converting DP type interface signals into DVI type interface signals, each DP interface output signal of a 4K computer is 2K, and when a 4K display screen charging compensation algorithm is debugged, 2 adapter plates are needed; similarly, when the 8K display screen algorithm is debugged, each DP interface of the 8K computer outputs 2K signals, and 4 adapter plates are needed. Moreover, when the debugging platform is actually built, the adapter plate is easily damaged due to improper operation.
Disclosure of Invention
The application provides a display data debugging system, which solves the problems that the bit width of a video signal output by the display data debugging system depends on the configuration of a PC display card and more adapter plates are needed.
In a first aspect, the present application provides a display data debugging system, which includes an upper computer, a field programmable gate array, a display panel to be debugged, and a color analyzer; the upper computer is used for generating a control instruction, receiving and outputting a corresponding debugging data table according to the color data; the field programmable gate array is connected with the upper computer and used for outputting video data with corresponding bit width according to the control instruction; the display panel to be debugged is connected with the field programmable gate array and is used for receiving the video data to display a corresponding test picture; and the color analyzer is connected with the display panel to be debugged and the upper computer and is used for detecting the test picture to obtain corresponding color data.
Based on the first aspect, in a first implementation manner of the first aspect, the field programmable gate array includes a storage unit, a bit width conversion unit, and a control unit; a storage unit for storing video data; the bit width conversion unit is used for carrying out bit width conversion on the video data so as to output the video data with corresponding bit width; and the control unit is connected with the upper computer, the storage unit and the bit width conversion unit and used for calling the video data to the bit width conversion unit according to the control instruction and indicating the bit width conversion unit to perform corresponding bit width conversion.
Based on the first implementation manner of the first aspect, in the second implementation manner of the first aspect, the bit width is 8bits or 10 bits.
In a third implementation manner of the first implementation manner, the upper computer is connected with the control unit through a two-wire serial data bus.
In a fourth embodiment of the first aspect, based on the first aspect, the color analyzer is model CA310 or CA 410.
In a fifth implementation manner of the first aspect, based on the first implementation manner of the first aspect, the field programmable gate array is disposed on the PG circuit board; the PG circuit board is also provided with a signal switching module; the signal switching module is used for converting the video signal from an LVDS type to a V-By-One type.
In a sixth implementation manner of the first aspect, based on the fifth implementation manner of the first aspect, the display panel to be tested comprises a timing controller located on a C circuit board; the signal switching module and the time schedule controller transmit video signals in a V-By-One signal mode.
In a seventh implementation manner of the first aspect, based on the sixth implementation manner of the first aspect, the display panel to be tested further comprises an X circuit board and a data driving IC; the output end of the C circuit board is connected with the input end of the X circuit board through a MINI-LVDS interface or a P2P interface; the output end of the X circuit board is connected with the input end of the data driving IC.
In an eighth implementation manner of the first aspect, in the sixth implementation manner of the first aspect, the C circuit board is further provided with a gray scale circuit for providing a gray scale signal, a potential conversion circuit for providing a potential signal, and a direct current conversion circuit.
In a second aspect, the present application provides a display data debugging method, including: the upper computer outputs a corresponding control instruction; the field programmable gate array outputs video data with corresponding bit width according to the control instruction; the display panel to be debugged displays a corresponding test picture according to the received video data; the color analyzer outputs corresponding color data according to the detected test picture; and the upper computer stores and processes the color data and outputs a control instruction of the next round until the upper computer generates a debugging data table of the panel to be displayed according to the color data of at least one round.
According to the display data debugging system and the display data debugging method, the field programmable logic gate array is controlled to output the video data with the corresponding bit width through the control instruction sent by the upper computer, the bit width limitation of the PC display card on the video data is removed, the using number of the adapter plates is reduced, and the debugging of the display data is more convenient and efficient.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a display data debugging system according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram of a second display data debugging system according to an embodiment of the present application.
Fig. 3 is a schematic flowchart of a display data debugging method according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
As shown in fig. 1, the present embodiment provides a display data debugging system, which includes an upper computer 100, a field programmable gate array 200, a display panel 300 to be debugged, and a color analyzer 400; the upper computer 100 is used for generating a control instruction, receiving and outputting a corresponding debugging data table according to the color data; the field programmable gate array 200 is connected with the upper computer 100 and is used for outputting video data with corresponding bit width according to the control instruction; the display panel 300 to be debugged is connected with the field programmable gate array 200 and is used for receiving the video data to display a corresponding test picture; and a color analyzer 400 connected to the display panel 300 to be debugged and the upper computer 100, for detecting the test image to obtain corresponding color data.
It can be understood that the display panel 300 to be debugged in this embodiment is a debugging object of the display data debugging system, is not included in the display data debugging system, and is only for convenience of description, so as to more clearly show the signal trend relationship in the display data debugging system. The display data debugging system may be, but not limited to, a liquid crystal panel, and may also be other self-luminous display panels, for example, an OLED display panel, a mini-LED display panel, or a micro-LED display device.
It can be understood that, in the working process of this embodiment, the upper computer 100 only needs to send a corresponding control instruction to the field programmable gate array 200, which saves the conversion process of the video data from the upper computer 100 to the field programmable gate array 200, i.e., saves the use of a corresponding adapter board; moreover, the field programmable gate array 200 can output video data with corresponding bit width according to the control instruction, and solves the problem that the traditional technical scheme depends on the configuration of a PC (personal computer) display card, so that the PC configured by any display card outputs the control instruction, and the FPGA is controlled to generate pictures with required resolution and bit depth, namely, a debugging system does not require the configuration of the PC display card to be 4K or 8K, and does not need a DP/DVI adapter plate, thereby greatly simplifying a debugging platform, improving the applicability of the debugging system, and saving resources, and particularly, the field programmable gate array 200 provides debugging possibility for data compensation of panels and signals with 8K, 10bit or higher requirements, and also provides a reference idea for development of other debugging systems.
As shown in fig. 2, in one embodiment, the field programmable gate array 200 includes a storage unit 210, a bit width conversion unit 230, and a control unit 220; a storage unit 210 for storing video data; a bit width conversion unit 230, configured to perform bit width conversion on the video data to output video data with a corresponding bit width; and a control unit 220, connected to the upper computer 100, the storage unit 210 and the bit width conversion unit 230, for calling the video data to the bit width conversion unit 230 according to the control instruction, and indicating the bit width conversion unit 230 to perform corresponding bit width conversion.
It can be understood that the bit width conversion that can be performed by the field programmable gate array 200 at present can satisfy the bit width conversion of the display data, after all, the bit width conversion of the current display data uses more display data for conversion into 8bits, and the higher end requirement is the display data for conversion into 10 bits.
In one embodiment, the bit width may be, but is not limited to, 8bits or 10bits, or 12bits, or 14bits, or 16bits or more.
In one embodiment, the host computer 100 and the control unit 220 may be connected via a two-wire serial data bus, but not limited thereto, and may also be a full-duplex synchronous serial bus.
In one embodiment, the model of the color analyzer 400 may be, but is not limited to, CA310 or CA410, and may be other optical instruments that can achieve brightness and color collection of a display screen.
In one embodiment, the field programmable gate array 200 is disposed on the PG circuit board; the PG circuit board is also provided with a signal switching module; the signal switching module is used for converting the video signal from an LVDS type to a V-By-One type.
It can be understood that the field programmable gate array 200 and the signal switching module are disposed on the same PG circuit board, which can reduce the occupied space of the display data debugging system and increase the portability of the display data debugging system.
In one embodiment, the display panel to be tested comprises a time sequence controller positioned on a C circuit board; the signal switching module and the time schedule controller transmit video signals in a V-By-One signal mode.
In one embodiment, the display panel to be tested further comprises an X circuit board and a data driving IC; the output end of the C circuit board is connected with the input end of the X circuit board through a MINI-LVDS interface or a P2P interface; the output end of the X circuit board is connected with the input end of the data driving IC.
In one embodiment, the C circuit board is further provided with a gray scale circuit for providing a gray scale signal, a potential conversion circuit for providing a potential signal, and a direct current conversion circuit.
It is understood that the potential signal output by the potential conversion circuit includes a high potential signal and/or a low potential signal for turning on the thin film transistor. The direct current conversion circuit is used for providing adaptive direct current voltage for the related electrical units.
It can be understood that the time schedule controller, the gray scale circuit, the potential conversion circuit and the direct current conversion circuit are all integrated on the C circuit board, so that the mutual routing can be reduced, and the occupied space of the C circuit board is reduced.
It can be understood that the working process of the display data debugging system provided by the present disclosure is as follows:
1) and the PC sends out a control instruction through the USB-to-IIC jig board to control the FPGA to output the LVDS signal of 8/10 bits.
2) The signal transfer board converts the LVDS into a V-by-one signal and transmits the V-by-one signal to a Tcon IC on the C-board, the Tcon IC transmits the V-by-one signal to a Data IC, and finally the liquid crystal panel displays a picture.
3) And color analyzer 400CA310/CA410 performs optical measurement of the display screen, and the measured color data is returned to PC.
4) And the PC stores and processes the data, issues an instruction again to control the FPGA to output a corresponding LVDS signal, repeats the process, finally realizes the whole debugging action and outputs a debugging data table.
The scheme can simplify the original debugging platform, cost reduction (cost down) is carried out while the debugging function is guaranteed, and the design is also suitable for other debugging platforms which need to generate high resolution and high signal bits.
As shown in fig. 3, in one embodiment, the present application provides a display data debugging method, which includes the following steps:
step S10: the upper computer 100 outputs a corresponding control instruction.
Step S20: the fpga 200 outputs video data with corresponding bit width according to the control instruction.
Step S30: the display panel 300 to be debugged displays a corresponding test picture according to the received video data.
Step S40: the color analyzer 400 outputs corresponding color data according to the detected test image.
And step S50: the upper computer 100 stores and processes the color data, and outputs a control instruction of the next round until the upper computer 100 generates a debugging data table of the panel to be displayed according to the color data of at least one round.
It can be understood that the display data debugging method provided by the embodiment has no requirement on the setting of the PC display card and does not need a DVI & DP adapter board, thereby improving the applicability of debugging and saving resources.
It can be understood that the display data debugging method or the display data debugging system provided by the present disclosure can simplify the existing debugging platform of the charge compensation algorithm, achieve low cost (cost down) while ensuring the debugging function, and is also applicable to other debugging or optical metrology platforms that need to generate similar signals.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The display data debugging system provided by the embodiment of the present application is introduced in detail, a specific example is applied in the description to explain the principle and the implementation of the present application, and the description of the embodiment is only used to help understanding the technical scheme and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A display data debugging system, comprising:
the upper computer is used for generating a control instruction, receiving and outputting a corresponding debugging data table according to the color data;
the field programmable gate array is connected with the upper computer and used for outputting video data with corresponding bit width according to the control instruction;
the display panel to be debugged is connected with the field programmable gate array and used for receiving the video data to display a corresponding test picture; and
and the color analyzer is connected with the display panel to be debugged and the upper computer and is used for detecting the test picture to obtain the corresponding color data.
2. The display data debugging system of claim 1, wherein the field programmable gate array comprises:
a storage unit for storing the video data;
the bit width conversion unit is used for performing bit width conversion on the video data to output the video data with corresponding bit width; and
and the control unit is connected with the upper computer, the storage unit and the bit width conversion unit and used for calling the video data to the bit width conversion unit according to the control instruction and indicating the bit width conversion unit to perform corresponding bit width conversion.
3. The display data debugging system of claim 2, wherein the bit width is 8bits or 10 bits.
4. The display data debugging system of claim 2, wherein the upper computer is connected to the control unit via a two-wire serial data bus.
5. The display data debugging system of claim 1, wherein the color analyzer is model CA310 or CA 410.
6. The display data debugging system of claim 2, wherein the field programmable gate array is disposed on a PG circuit board; the PG circuit board is also provided with a signal switching module; the signal switching module is used for converting the video signal from an LVDS type to a V-By-One type.
7. The display data debugging system of claim 6, wherein the display panel to be tested comprises a timing controller on a C-circuit board; the signal switching module and the time sequence controller transmit the video signal in a V-By-One signal mode.
8. The display data debugging system of claim 7, wherein the display panel to be tested further comprises an X circuit board and a data driving IC;
the output end of the C circuit board is connected with the input end of the X circuit board through a MINI-LVDS interface or a P2P interface; and the output end of the X circuit board is connected with the input end of the data drive IC.
9. The system for debugging display data according to claim 7, wherein a gray scale circuit for providing a gray scale signal, a potential conversion circuit for providing a potential signal, and a direct current conversion circuit are further disposed on the C circuit board.
10. A display data debugging method is characterized by comprising the following steps:
the upper computer outputs a corresponding control instruction;
the field programmable gate array outputs video data with corresponding bit width according to the control instruction;
the display panel to be debugged displays a corresponding test picture according to the received video data;
the color analyzer outputs corresponding color data according to the detected test picture; and
and the upper computer stores and processes the color data and outputs a control instruction of the next round until the upper computer generates a debugging data table of the panel to be displayed according to the color data of at least one round.
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