CN107733383B - Transimpedance amplifying circuit and design method thereof - Google Patents
Transimpedance amplifying circuit and design method thereof Download PDFInfo
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- CN107733383B CN107733383B CN201710865227.6A CN201710865227A CN107733383B CN 107733383 B CN107733383 B CN 107733383B CN 201710865227 A CN201710865227 A CN 201710865227A CN 107733383 B CN107733383 B CN 107733383B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
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Abstract
The invention discloses a transimpedance amplification circuit, and relates toThe field of optical communications, including transimpedance amplifiers A1A first capacitor C1A first resistor R1And a first MOS transistor Q1First resistance R1And a first MOS transistor Q1Connected in series with the first capacitor C1In parallel, a first capacitor C1One terminal and a transimpedance amplifier A1Is connected with the other end of the inverting input end of the amplifier A, and the other end of the inverting input end of the amplifier A is connected with the transimpedance amplifier A1Are connected with each other. According to the transimpedance amplification circuit provided by the invention, through the voltage-controlled MOS tube equivalent resistance, the MOS tube is small in size and production difficulty, larger parasitic capacitance cannot be generated, the bandwidth is larger, and the application range is wider.
Description
Technical Field
The invention relates to the field of optical communication, in particular to a transimpedance amplification circuit and a design method thereof.
Background
In the era of rapid development of multimedia and network technologies, data volume is exponentially and explosively increased, optical fiber communication is widely applied due to the characteristics of rapid transmission and large communication traffic, and in the optical fiber communication, small current needs to be converted into acceptable voltage, so that subsequent circuit processing is facilitated.
Referring to fig. 1, in the prior art, at a receiving end of an optical communication system, a photodiode LED receives an optical signal, then a small current is converted into a large voltage through a trans-impedance amplifying circuit, and then the large voltage is passed through a limiting amplifier a2And converting the large voltage output by the transimpedance amplification circuit into a voltage acceptable by a user. Usually the transimpedance amplifier circuit comprises a transimpedance amplifier a connected in parallel1And a second resistor R2A second resistance R2Are connected in parallel with a second capacitor C2A second capacitor C2As parasitic capacitance, a second capacitance C2Is connected across the trans-impedance amplifier A1The input and output terminals of the capacitor are easy to form miller effect, resulting in amplification of the cross-over capacitance.
To increase the conversion efficiency, the second resistor R is usually used2The resistance is large, which can be up to several hundred K ohm, resulting in large area, not only increasing the production difficulty, but also generating larger parasitic capacitance. A cross-over capacitor amplifying and a second resistor R2The generated parasitic capacitance causes the circuit to have smaller bandwidth, part of high-frequency signals cannot be amplified, and the application range is small.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a transimpedance amplification circuit which has the advantages of small size of an MOS (metal oxide semiconductor) tube, small production difficulty, no generation of larger parasitic capacitance, larger bandwidth and wider application range through the equivalent resistance of the MOS tube controlled by voltage.
In order to achieve the above purposes, the technical scheme adopted by the invention is as follows:
a transimpedance amplifier circuit comprises a transimpedance amplifier A1A first capacitor C1A first resistor R1And a first MOS transistor Q1The first resistor R1And a first MOS transistor Q1Connected in series with the first capacitor C1In parallel, the first capacitor C1One end of the resistor is connected with the trans-impedance amplifier A1Is connected with the other end of the inverting input end of the transimpedance amplifier A1Are connected with each other.
On the basis of the technical scheme, the first MOS tube Q1Is an NMOS tube.
The invention also provides a design method of the transimpedance amplification circuit, which comprises the following steps:
designing an original transimpedance amplification circuit comprising a transimpedance amplifier A1A second capacitor C2And a second resistor R2Said second capacitor C2And a second resistor R2In parallel, the second capacitor C2One end of the resistor is connected with the trans-impedance amplifier A1Is connected with the other end of the inverting input end of the transimpedance amplifier A1The output ends of the two are connected;
obtaining a second resistor R according to the original transimpedance amplifying circuit2The resistance value of (1);
according to the second resistance R2Is correspondingly matched with the first resistor R1And a first MOS transistor Q1Make the first resistor R1And a first MOS transistor Q1Is equal to the second resistor R2The resistance value of (c).
On the basis of the technical scheme, the first resistor R is matched1And a first MOS transistor Q1Method (2)The following were used:
designing an equivalent matching circuit which comprises two parallel branches and an operational amplifier A3One of the branch lines is a second MOS transistor Q2And a second resistor R2Are connected in series in sequence, and the other branch is composed of a third MOS tube Q3A third resistor R3And a fourth MOS transistor Q4Sequentially connected in series, the operational amplifier A3And the positive input end of the second MOS tube Q2Is connected to the output terminal of the operational amplifier A3And the reverse input end of the third MOS tube Q3Is connected to the output terminal of the operational amplifier A3And the output end of the fourth MOS tube Q4The two branches are connected in parallel and then connected in series with a fifth MOS tube Q5The fifth MOS transistor Q5The source of (2) is grounded;
for the second MOS tube Q2And a third MOS transistor Q3Applying the same bias voltage to adjust the third resistor R3Until the operational amplifier A3The fourth MOS tube Q is obtained when the state reaches the virtual short state4A gate voltage of;
matching the first resistance R1And a first MOS transistor Q1Make the first resistor R1Is equal to the third resistor R3The resistance value of the first MOS tube Q1The bias voltage of the grid is equal to that of the fourth MOS tube Q4The gate voltage of (c).
On the basis of the technical scheme, the first MOS tube Q1Is an NMOS tube.
On the basis of the technical scheme, the second MOS tube Q2And a third MOS transistor Q3Are all PMOS tubes.
On the basis of the above technical scheme, the fourth MOS transistor Q4And a fifth MOS transistor Q5Are all NMOS tubes.
Compared with the prior art, the invention has the advantages that:
(1) according to the transimpedance amplification circuit, the MOS tube equivalent resistance is controlled through voltage, the MOS tube is small in size and small in production difficulty, large parasitic capacitance cannot be generated, the bandwidth is large, and the application range is wide;
(2) the transimpedance amplifier circuit of the present invention includes a first resistor R1Can effectively share partial voltage, so that the first MOS transistor Q1Voltage difference between drain and sourcedsLower, thereby increasing the first MOS transistor Q1Increase the linearity of the transimpedance amplifier A1The gain of (2) can convert small current into larger voltage, and the effect is better.
Drawings
FIG. 1 is a schematic diagram of a transimpedance amplifier circuit according to the prior art;
FIG. 2 is a schematic diagram of a transimpedance amplifier circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an equivalent matching circuit in an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Referring to fig. 2, an embodiment of the invention provides a transimpedance amplifier circuit including a transimpedance amplifier a1A first capacitor C1A first resistor R1And a first MOS transistor Q1First resistance R1And a first MOS transistor Q1Connected in series with the first capacitor C1In parallel, a first capacitor C1One terminal and a transimpedance amplifier A1Is connected with the other end of the inverting input end of the amplifier A, and the other end of the inverting input end of the amplifier A is connected with the transimpedance amplifier A1Are connected with each other. First MOS transistor Q1Is an NMOS tube.
The transimpedance amplification circuit of the embodiment of the invention comprises a first resistor R1Can effectively share partial voltage, so that the first MOS transistor Q1Voltage difference between drain and sourcedsLower, thereby increasing the first MOS transistor Q1Increase the linearity of the transimpedance amplifier A1The gain of (2) can convert small current into larger voltage, and the effect is better.
According to the transimpedance amplification circuit, the MOS tube equivalent resistance is controlled through voltage, the MOS tube is small in size and small in production difficulty, large parasitic capacitance cannot be generated, the bandwidth is large, and the application range is wide.
The invention also provides a design method of the transimpedance amplification circuit, which comprises the following steps:
designing an original transimpedance amplifier circuit comprising a transimpedance amplifier A1A second capacitor C2And a second resistor R2A second capacitor C2And a second resistor R2Parallel connection, a second capacitor C2One terminal and a transimpedance amplifier A1Is connected with the other end of the inverting input end of the amplifier A, and the other end of the inverting input end of the amplifier A is connected with the transimpedance amplifier A1As shown in fig. 1;
obtaining a second resistor R according to the original transimpedance amplifying circuit2The resistance value of (1);
according to the second resistance R2Is correspondingly matched with the first resistor R1And a first MOS transistor Q1Make the first resistor R1And a first MOS transistor Q1Is equal to the second resistor R2The resistance value of (c).
In the embodiment of the invention, the first resistor R is matched1And a first MOS transistor Q1The method comprises the following steps:
designing an equivalent matching circuit, as shown in FIG. 3, the equivalent matching circuit includes two parallel branches and an operational amplifier A3One branch of the MOS transistor is connected with a second MOS transistor Q2And a second resistor R2Sequentially connected in series, and the other branch is composed of a third MOS transistor Q3A third resistor R3And a fourth MOS transistor Q4Serially connected in sequence, an operational amplifier A3Positive input end and second MOS tube Q2Are connected to the output of an operational amplifier A3And the reverse input end of the third MOS transistor Q3Are connected to the output of an operational amplifier A3And the output end of the fourth MOS transistor Q4The two branches are connected in parallel and then connected in series with a fifth MOS tube Q5Fifth MOS transistor Q5The source electrode of the transistor is grounded, and a fifth MOS tube Q5Bias voltage of the gate electrode is Vbiasn；
For the second MOS tube Q2And a third MOS transistor Q3Applying the same bias voltage VbiaspAdjusting the third resistance R3Resistance value ofUp to operational amplifier A3Reaches an imaginary short state, at which time the operational amplifier A3Voltage V at the positive input+Equal to the voltage V of the inverting input-To obtain a fourth MOS transistor Q4Gate voltage V ofg；
Matching the first resistance R1And a first MOS transistor Q1Make the first resistor R1Is equal to the third resistor R3Resistance value of, the first MOS transistor Q1The bias voltage of the grid is equal to that of the fourth MOS tube Q4Gate voltage V ofg。
First MOS transistor Q1Is an NMOS transistor, a second MOS transistor Q2And a third MOS transistor Q3Are PMOS tubes, the fourth MOS tube Q4And a fifth MOS transistor Q5Are all NMOS tubes.
In the design method of the transimpedance amplification circuit in the embodiment of the invention, the second MOS transistor Q is used2And a third MOS transistor Q3Applying the same bias voltage VbiaspAdjusting the third resistance R3Until the operational amplifier A3The virtual short state is reached, so that the voltage and the current on the two branches are the same, and the third resistor R can be enabled3And a fourth MOS transistor Q4Is equal to the second resistor R2The resistance value of the two branches is equivalent to match, the circuit is simple, and the design is convenient.
The present invention is not limited to the above-described embodiments, and it will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the principle of the present invention, and such modifications and improvements are also considered to be within the scope of the present invention. Those not described in detail in this specification are within the skill of the art.
Claims (4)
1. A design method of a transimpedance amplifier circuit comprises a transimpedance amplifier A1A first capacitor C1A first resistor R1And a first MOS transistor Q1The first resistor R1And a first MOS transistor Q1Connected in series with the first capacitor C1In parallel, theA first capacitor C1One end of the resistor is connected with the trans-impedance amplifier A1Is connected with the other end of the inverting input end of the transimpedance amplifier A1The output ends of the two are connected;
the design method is characterized by comprising the following steps:
designing an original transimpedance amplification circuit comprising a transimpedance amplifier A1A second capacitor C2And a second resistor R2Said second capacitor C2And a second resistor R2In parallel, the second capacitor C2One end of the resistor is connected with the trans-impedance amplifier A1Is connected with the other end of the inverting input end of the transimpedance amplifier A1The output ends of the two are connected;
obtaining a second resistor R according to the original transimpedance amplifying circuit2The resistance value of (1);
according to the second resistance R2Is correspondingly matched with the first resistor R1And a first MOS transistor Q1Make the first resistor R1And a first MOS transistor Q1Is equal to the second resistor R2The resistance value of (1);
matching the first resistance R1And a first MOS transistor Q1The method comprises the following steps:
designing an equivalent matching circuit which comprises two parallel branches and an operational amplifier A3One of the branch lines is a second MOS transistor Q2And a second resistor R2Are connected in series in sequence, and the other branch is composed of a third MOS tube Q3A third resistor R3And a fourth MOS transistor Q4Sequentially connected in series, the operational amplifier A3And the positive input end of the second MOS tube Q2Is connected to the output terminal of the operational amplifier A3And the reverse input end of the third MOS tube Q3Is connected to the output terminal of the operational amplifier A3And the output end of the fourth MOS tube Q4The two branches are connected in parallel and then connected in series with a fifth MOS tube Q5The fifth MOS transistor Q5The source of (2) is grounded;
for the second MOS tube Q2And a third MOS transistor Q3Applying the same bias voltage to adjust the third resistor R3Until the operational amplifier A3The fourth MOS tube Q is obtained when the state reaches the virtual short state4A gate voltage of;
matching the first resistance R1And a first MOS transistor Q1Make the first resistor R1Is equal to the third resistor R3The resistance value of the first MOS tube Q1The bias voltage of the grid is equal to that of the fourth MOS tube Q4The gate voltage of (c).
2. The method for designing a transimpedance amplifier circuit according to claim 1, characterized in that: the first MOS transistor Q1Is an NMOS tube.
3. The method for designing a transimpedance amplifier circuit according to claim 1, characterized in that: the second MOS transistor Q2And a third MOS transistor Q3Are all PMOS tubes.
4. The method for designing a transimpedance amplifier circuit according to claim 1, characterized in that: the fourth MOS transistor Q4And a fifth MOS transistor Q5Are all NMOS tubes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710865227.6A CN107733383B (en) | 2017-09-22 | 2017-09-22 | Transimpedance amplifying circuit and design method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710865227.6A CN107733383B (en) | 2017-09-22 | 2017-09-22 | Transimpedance amplifying circuit and design method thereof |
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| Publication Number | Publication Date |
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| CN107733383A CN107733383A (en) | 2018-02-23 |
| CN107733383B true CN107733383B (en) | 2020-10-30 |
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| CN109787566A (en) * | 2019-03-11 | 2019-05-21 | 广州华欣电子科技有限公司 | A kind of infrared signal amplifying circuit, processing circuit and infrared touch panel |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7304543B2 (en) * | 2005-12-28 | 2007-12-04 | Pmc-Sierra Israel Ltd. | Burst-mode TIA (trans-impedance amplifier) |
| EP2003774A1 (en) * | 2007-06-15 | 2008-12-17 | Honeywell International Inc. | Variable gain constant bandwidth trans-impedance amplifier for fiber optic rate sensor |
| CN102055421A (en) * | 2009-11-05 | 2011-05-11 | 扬智科技股份有限公司 | Differential to single-end amplifier with gain control |
| CN103368502A (en) * | 2012-03-28 | 2013-10-23 | 德州仪器公司 | Compensating circuit and method of amplifier driving large capacitive load |
-
2017
- 2017-09-22 CN CN201710865227.6A patent/CN107733383B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7304543B2 (en) * | 2005-12-28 | 2007-12-04 | Pmc-Sierra Israel Ltd. | Burst-mode TIA (trans-impedance amplifier) |
| EP2003774A1 (en) * | 2007-06-15 | 2008-12-17 | Honeywell International Inc. | Variable gain constant bandwidth trans-impedance amplifier for fiber optic rate sensor |
| CN102055421A (en) * | 2009-11-05 | 2011-05-11 | 扬智科技股份有限公司 | Differential to single-end amplifier with gain control |
| CN103368502A (en) * | 2012-03-28 | 2013-10-23 | 德州仪器公司 | Compensating circuit and method of amplifier driving large capacitive load |
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Effective date of registration: 20201224 Address after: 430000, 2nd floor, optical communication industrial building, Fenghuo Road, Guandong Industrial Park, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: WUHAN FISILINK MICROELECTRONICS TECHNOLOGY Co.,Ltd. Address before: 430000 No. 6, High-tech Fourth Road, Donghu High-tech Development Zone, Wuhan City, Hubei Province Patentee before: FIBERHOME TELECOMMUNICATION TECHNOLOGIES Co.,Ltd. Patentee before: WUHAN FISILINK MICROELECTRONICS TECHNOLOGY Co.,Ltd. |
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