CN107729271B - Double-bus E-FLASH control circuit with self-test function - Google Patents
Double-bus E-FLASH control circuit with self-test function Download PDFInfo
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- CN107729271B CN107729271B CN201711010489.0A CN201711010489A CN107729271B CN 107729271 B CN107729271 B CN 107729271B CN 201711010489 A CN201711010489 A CN 201711010489A CN 107729271 B CN107729271 B CN 107729271B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The invention relates to a double-bus type E-FLASH control circuit with a self-testing function, which comprises a testing module for testing an E-FLASH unit and a bus interface module capable of realizing the operation of the E-FLASH unit, wherein the bus interface module is connected with a control module; the bus interface module comprises an AHB bridge connected with the control module and a configuration register connected with the control module, the configuration register is connected with the IPS bridge, and the configuration register is connected with the E-FLASH unit; and the E-FLASH unit is operated by matching the AHB bridge and the IPS bridge, or the E-FLASH unit is directly operated by the IPS bridge. The invention has simple structure, flexible use and high reliability, and can meet the requirements of testing and controlling the E-FLASH in the SoC.
Description
Technical Field
The invention relates to a control circuit, in particular to a double-bus type E-FLASH control circuit with a self-test function, and belongs to the technical field of SoC.
Background
With the continuous improvement of the performance of integrated circuits and the rapid development of communication technologies, SoC-type circuits become more and more popular; SoC is a short for system on chip, which takes CPU as core and forms a product with software and hardware working together based on general and customized IP (intellectual property). The flexible configuration of the SoC can be realized through software programming, the embedded FLASH can store programming data, and meanwhile, the E-FLASH is distinguished by the characteristics of low cost, high stability and flexible use, and the wide application of the E-FLASH enables an E-FLASH controller to become an essential part in a SoC system.
At present, a scheme using an E-FLASH controller exists, but the configuration of data and time sequence is not flexible enough, hardware codes need to be modified aiming at different types of E-FLASH, the complexity of design is increased invisibly, the E-FLASH does not have a self-test function, a debug (debugging) function is lost invisibly, and the debugging and fault diagnosis of the E-FLASH are not convenient.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, provides the double-bus type E-FLASH control circuit with the self-test function, has simple structure, flexible use and high reliability, and can meet the requirements of the SoC on the test and control of the E-FLASH.
According to the technical scheme provided by the invention, the double-bus type E-FLASH control circuit with the self-test function comprises a test module for testing the E-FLASH unit and a bus interface module capable of realizing the operation of the E-FLASH unit, wherein the bus interface module is connected with the control module;
the bus interface module comprises an AHB bridge connected with the control module and a configuration register connected with the control module, the configuration register is connected with the IPS bridge, and the configuration register is connected with the E-FLASH unit;
and the E-FLASH unit is operated by matching the AHB bridge and the IPS bridge, or the E-FLASH unit is directly operated by the IPS bridge.
The operation of the E-FLASH unit is directly realized through the IPS bridge, and comprises data erasing, data reading or data writing; when the E-FLASH unit is operated, the configuration register is configured to control the E-FLASH unit to complete the required operation.
The operations of the E-FLASH unit by matching the AHB bridge and the IPS bridge comprise data erasing, data reading or data writing; when the E-FLASH unit is operated, the configuration register is configured through the IPS bridge, the AHB bridge transmits operation control information to the control module, and the control module enables the E-FLASH unit to complete required operation according to the operation control information.
The operation control information transmitted by the AHB bridge to the control module comprises address information or data information.
The control module is connected with the data buffering module, address information of data in the operation process of the E-FLASH unit can be stored through the data buffering module, and the control module can directly read the address information stored in the data buffering module.
When the E-FLASH unit is tested, a test instruction and configuration parameters are input to the test module in series, corresponding configuration is carried out on test operation to be executed according to the configuration parameters, corresponding test excitation is generated, corresponding test is carried out on the E-FLASH unit, and the test module can output a test result of the E-FLASH unit.
The invention has the advantages that: the bus interface module comprises an AHB bridge and an IPS bridge, wherein the IPS bridge is mainly responsible for configuring the configuration register, and the AHB bridge is matched with the configuration register to transmit information such as data, addresses and the like to the control module and simultaneously can read internal data of the E-FLASH unit; the control module realizes data and address latching so as to complete erasing, reading and writing operations; the test module outputs data, addresses and control signals to the E-FLASH unit through an external serial port, various test operations on the E-FLASH unit are achieved, the structure is simple, the use is flexible, the reliability is high, and the requirement of embedded E-FLASH control in the SoC can be met.
Drawings
FIG. 1 is a block diagram of the present invention.
FIG. 2 is a detailed block diagram of the dual bus interface module and the control module according to the present invention.
FIG. 3 is a schematic diagram of the self-testing E-FLASH module of the present invention.
Description of reference numerals: 100-bus interface module, 101-control module, 102-test module, 103-E-FLASH unit, 104-self-test E-FLASH module, 105-AHB bridge, 106-IPS bridge, 107-configuration register, 108-data buffer module, 109-self-test circuit, 110-first selector, 111-second selector, 112-third selector and 113-fourth selector.
Detailed Description
The invention is further illustrated by the following specific figures and examples.
As shown in fig. 1 and 2: in order to meet the requirements of testing and controlling the E-FLASH in the SoC, the invention comprises a testing module 102 for testing an E-FLASH unit 103 and a bus interface module 100 capable of realizing the operation of the E-FLASH unit 103, wherein the bus interface module 100 is connected with a control module 101;
the bus interface module 100 comprises an AHB bridge 105 connected with the control module 101 and a configuration register 107 connected with the control module 101, wherein the configuration register 107 is connected with an IPS bridge 106, and the configuration register 107 is connected with the E-FLASH unit 103;
the E-FLASH cell 103 is operated as desired by the AHB bridge 105 in cooperation with the IPS bridge 106, or the E-FLASH cell 103 is operated as desired directly by the IPS bridge 106.
Specifically, the E-FLASH unit 103 may adopt a conventional chip, the E-FASH unit 103 and the test module 102 form a self-test E-FLASH module 104, the control module 101 is connected to the self-test E-FLASH module 104 through the bus interface module 100, the test on the E-FLASH unit 103 can be realized through the self-test-FLASH module 104, and the operation on the E-FLASH unit 103 can be realized through the cooperation of the control module 101 and the bus interface module 100.
The bus interface module 100 includes an AHB (PLB 2 AHB) bridge 105, an ips (opbtoips) bridge 106, and a configuration register 107; the configuration of the configuration register 107 can be realized through the IPS bridge 106, and data information, address information, and the like can be transmitted to the control module 101 through the AHB bridge 105; namely, two flexibly configured bus structures of the AHB bridge 105 and the IPS bridge 106 are not interfered with each other, so that the accuracy and the high efficiency of the operation of the E-FLASH unit 103 are ensured.
Further, the operation of the E-FLASH unit 103, including data erasing, data reading or data writing, is directly implemented through the IPS bridge 106; when the E-FLASH unit 103 is operated, the configuration register 107 is configured to control the E-FLASH unit 103 to complete the required operation.
In the embodiment of the present invention, the configuration register 107 hung on the IPS bridge 106 is configured by the IPS bridge 106, and the operations of erasing, reading, writing, and the like on the E-FLASH unit 103 are independently implemented, which is specifically implemented in a manner that: the configuration registers 107 are grouped into four broad categories in total: E-FLASH port control signal, data register, address register and other control register, other control register mainly include: write data MASK control, ECC switch control, etc., the E-FLASH port control signals are mainly: erase, Program, Xe, Ye, etc. In specific implementation, the configuration of the configuration register 107 is implemented by using a common technical means in the technical field, and a specific configuration process is determined according to the type of the configuration register 107 and the type of the E-FLASH unit 103, which is known to those skilled in the art and will not be described herein again.
The method for implementing the erasing, reading and writing operations of the E-FLASH unit 103 through the IPS bridge 106 comprises the steps of firstly completing the configuration of a data register and an address register in a configuration register 107, configuring an address and data to be written, a read address, an erased address and the like into the configuration register 107, then configuring other control registers, starting an ECC control switch if ECC verification is needed, after three types of configuration are completed, finally configuring erasing, reading and writing time sequence waveforms, configuring port control signals according to the port time sequence of the corresponding E-FLASH unit 103, configuring signal change once every time, then delaying time sequence configuration for control, loading the E-FLASH port with the previously configured address and data, and automatically completing the erasing, reading and writing operations of the E-FLASH after the control signals are configured.
Further, the operations performed on the E-FLASH unit 103 by the AHB bridge 105 in cooperation with the IPS bridge 106 include data erasing, data reading, or data writing; when the E-FLASH unit 103 is operated, the configuration register 107 is configured through the IPS bridge 106, the AHB bridge 105 transmits operation control information into the control module 101, and the control module 101 makes the E-FLASH unit 103 complete a required operation according to the operation control information.
In the embodiment of the present invention, when the E-FLASH unit 103 is operated by matching the AHB bridge 105 and the IPS bridge 106, the IPS bridge 106 is responsible for configuring the configuration register 107, and controls the state of the internal state machine of the control module 101 after configuring the configuration register 107, the state machines can automatically generate the control signal required by the E-FLASH port, and the control module 101 can be obtained by using a conventional chip, which is known to those skilled in the art and will not be described herein again. If the write operation is performed, the configuration register 107 is configured first, a PGM signal is turned on (program operation is started), then, the AHB bridge 105 performs the write operation of data, the control module 101 automatically latches data and addresses sent by the AHB bridge 105, and after the IPS bridge 106 configures the configuration register 107 and turns on the EHV signal (environment is ready, control signal generation is started), the state machine in the control module 101 automatically generates an E-FLASH port control signal to complete the write operation on the E-FLASH, and when the DONE is high, the corresponding signal is cleared (DONE indicates that the operation is completed, and the value in the register, such as EHV PGM, is cleared).
In addition, the control module 101 is connected to the data buffering module 108, the data buffering module 108 can store address information of data in the operating process of the E-FLASH unit 103, and the control module 101 can directly read the address information stored in the data buffering module 108.
In the embodiment of the present invention, the data buffering module 108 buffers the address information of the data, so that the consumption of repeatedly reading the data from the FLASH unit 103 can be reduced.
When the E-FLASH unit 103 is tested, a test instruction and configuration parameters are serially input to the test module 102, corresponding configuration is performed on test operations to be executed according to the configuration parameters, corresponding test stimuli are generated to perform corresponding tests on the E-FLASH unit 103, and the test module 102 can output test results on the E-FLASH unit 103.
In the embodiment of the present invention, the self-test module 102 includes a self-test circuit 109, a Flash _ out terminal of the self-test circuit 109 is connected to the bus data and a Dout terminal of the E-Flash unit 103 through a first selector 110, and serial input and output can be realized through the self-test circuit 109. The first output terminal of the bus data and self-test circuit 109 is connected to the Din terminal (data terminal) of the E-FLASH unit 103 through the second selector 111, the second output terminal of the bus address and self-test circuit 109 is connected to the Addr terminal (address terminal) of the E-FLASH unit 103 through the second selector 112, and the third output terminal of the bus control signal and self-test circuit 109 is connected to the control signal terminal of the E-FLASH unit 103 through the third selector 113, as shown in fig. 3.
When the E-FLASH unit 103 is in a non-test state, the Din terminal, the Addr terminal, and the control signal terminal are respectively connected to the bus data, the bus address information, and the bus control signal, so as to implement the required operation on the E-FLASH unit 103. When the E-FLASH unit 103 needs to be tested, the self-test circuit 109 is used for receiving the serial test instruction and the configuration parameters, the self-test circuit 109 generates corresponding test excitation according to the test instruction and the configuration parameters, the test excitation is loaded to the E-FLASH unit 103, the E-FLASH unit 103 can be tested, and the test result of the E-FLASH unit 103 is output. The self-test circuit 109 may be implemented in a conventional circuit form, as long as it can receive and recognize an external test command and configuration parameters, and generate a test stimulus to be loaded to the E-FLASH unit 103, and the specific implementation form is well known to those skilled in the art and will not be described herein again.
The bus interface module 100 of the invention comprises an AHB bridge 105 and an IPS bridge 106, wherein the IPS bridge 106 is mainly responsible for configuring a configuration register 107, the AHB bridge 105 is matched with the configuration register to transmit information such as data, addresses and the like to a control module 101, and simultaneously, the internal data of an E-FLASH unit 103 can be read; the control module 101 latches data and addresses to complete erasing, reading and writing operations; the test module 102 outputs data, addresses and control signals to the E-FLASH unit 103 through an external serial port, various test operations on the E-FLASH unit 103 are realized, the structure is simple, the use is flexible, the reliability is high, and the requirement of embedded E-FLASH control in the SoC can be met.
Claims (3)
1. A double-bus type E-FLASH control circuit with a self-test function is characterized in that: the device comprises a testing module (102) for testing the E-FLASH unit (103) and a bus interface module (100) capable of realizing the operation of the E-FLASH unit (103), wherein the bus interface module (100) is connected with a control module (101);
the bus interface module (100) comprises an AHB bridge (105) connected with the control module (101) and a configuration register (107) connected with the control module (101), wherein the configuration register (107) is connected with an IPS bridge (106), and the configuration register (107) is connected with the E-FLASH unit (103);
the E-FLASH unit (103) is operated by matching the AHB bridge (105) with the IPS bridge (106), or the E-FLASH unit (103) is directly operated by the IPS bridge (106);
the operation of the E-FLASH unit (103) is directly realized through the IPS bridge (106), wherein the operation comprises data erasing, data reading or data writing; when the E-FLASH unit (103) is operated, the configuration register (107) is configured to control the E-FLASH unit (103) to complete the required operation;
the operation of the E-FLASH unit (103) by the cooperation of the AHB bridge (105) and the IPS bridge (106) comprises data erasing, data reading or data writing; when the E-FLASH unit (103) is operated, the configuration register (107) is configured through the IPS bridge (106), the AHB bridge (105) transmits operation control information into the control module (101), and the control module (101) enables the E-FLASH unit (103) to complete required operation according to the operation control information;
the operation control information transmitted by the AHB bridge (105) to the control module (101) comprises address information or data information.
2. The dual bus type E-FLASH control circuit with self-test function of claim 1, wherein: the control module (101) is connected with the data buffering module (108), the data buffering module (108) can store address information of data in the operation process of the E-FLASH unit (103), and the control module (101) can directly read the address information stored in the data buffering module (108).
3. The dual bus type E-FLASH control circuit with self-test function of claim 1, wherein: when the E-FLASH unit (103) is tested, a test instruction and configuration parameters are input to the test module (102) in series, test operations to be executed are configured correspondingly according to the configuration parameters, corresponding test stimuli are generated so as to test the E-FLASH unit (103) correspondingly, and the test module (102) can output test results of the E-FLASH unit (103).
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| CN201711010489.0A CN107729271B (en) | 2017-10-26 | 2017-10-26 | Double-bus E-FLASH control circuit with self-test function |
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| CN109656626B (en) * | 2018-12-11 | 2022-05-17 | 中国航空工业集团公司西安航空计算技术研究所 | SD card data self-carrying method and device based on AHB bus |
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