CN107689326A - A kind of wafer thining method and device - Google Patents
A kind of wafer thining method and device Download PDFInfo
- Publication number
- CN107689326A CN107689326A CN201610638222.5A CN201610638222A CN107689326A CN 107689326 A CN107689326 A CN 107689326A CN 201610638222 A CN201610638222 A CN 201610638222A CN 107689326 A CN107689326 A CN 107689326A
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 49
- 238000007789 sealing Methods 0.000 claims abstract description 42
- 238000001035 drying Methods 0.000 claims abstract description 27
- 238000001312 dry etching Methods 0.000 claims abstract description 21
- 230000002093 peripheral effect Effects 0.000 claims abstract description 15
- 229910020323 ClF3 Inorganic materials 0.000 claims abstract description 10
- 239000007789 gas Substances 0.000 claims description 67
- 238000009792 diffusion process Methods 0.000 claims description 9
- 239000011261 inert gas Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 235000012431 wafers Nutrition 0.000 description 124
- 238000005516 engineering process Methods 0.000 description 6
- 230000008859 change Effects 0.000 description 4
- 238000000227 grinding Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000011946 reduction process Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02016—Backside treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02035—Shaping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The present invention provides a kind of wafer thining method and device, this method comprise the following steps：A wafer is provided, the wafer includes front and back, and the front is formed with IC naked cores；The wafer frontside is put into dry-process etching cavity down, the peripheral edge of the wafer is blocked using sealing ring, only exposes the central area of the thinned wafer rear of needs；It is passed through etching gas ClF3Dry etching is carried out to preset thickness to the central area of the wafer rear, obtains thinned wafer.Damaged present invention, avoiding mechanical lapping to caused by wafer; by setting up sealing ring and edge-protected gas; the dry etching of high-speed can be carried out to the central area of wafer rear; relative to the TAIKO techniques of prior art; this invention simplifies processing step; production cost is reduced, improves product yield.
Description
Technical field
The present invention relates to microelectronics technology, more particularly to a kind of wafer thining method and device.
Background technology
As memory and power device etc. towards the direction of smaller szie, higher performance using developing, to thin wafer
Demand is also growing.Thinner wafer can bring numerous benefits, including ultra-thin encapsulation, and thus bring smaller chi
Very little profile, in addition to improved electric property and more preferable heat dispersion.At this stage, most conventional semiconductor application reduction process
For grinding.TAIKO techniques are the wafer rear grinding techniques developed by Science and Technology Ltd. of enlightening Cisco, this technology and conventional
Back side grinding is different, when being ground to chip, will retain the marginal portion of chip periphery, only slim to carrying out being ground in circle
Change.It is this to stay the TAIKO wafers on side to have important application in power device and BSI type cmos image sensors in wafer periphery.
TAIKO techniques need especially fine milling tool, such as Patent No. JP2007173487A patent document institute
The device of record, this make it that the processing cost of TAIKO techniques is high.In addition, in the manufacturing step of IC top level structures, by machinery
The stress that grinding triggers can cause the rupture of wafer, such as power device to need to cover the polyimides of about 5 μ m-thicks, in wafer
Rupture nearly all occurs when being thinned to 100 μm.Patent No. JP2007335659A patent document provides to be subtracted using wet method
The method of thin making TAIKO wafers, however it is more the step of this method needs, it is cumbersome.
Therefore, wafer breakage, simple to operate, lower-cost wafer thining method can be reduced by being necessary to seek one kind in fact,
To obtain required TAIKO wafers.
The content of the invention
Prior art in view of the above, it is an object of the invention to provide a kind of wafer thining method and device, it is used for
Solve the problems, such as to easily cause wafer breakage, complex process, cost height etc. when making TAIKO wafers in the prior art.
In order to achieve the above objects and other related objects, the present invention provides a kind of wafer thining method, comprises the following steps：
A wafer is provided, the wafer includes front and back, and the front is formed with IC naked cores；
The wafer frontside is put into dry-process etching cavity down, the periphery sides of the wafer are blocked using sealing ring
Edge, only expose the central area of the thinned wafer rear of needs；
It is passed through etching gas ClF3Dry etching is carried out to preset thickness to the central area of the wafer rear, subtracted
Thin wafer.
Preferably, the periphery sides of wafer described in edge-protected gas shield are passed through in the space blocked by the sealing ring
Edge.
It is further preferred that the edge-protected gas is inert gas.
It is further preferred that the edge-protected gas is H2、He、Ar、N2In one or more.
It is further preferred that the edge-protected gas is from the wafer sky introduced below blocked by the sealing ring
Between.
Preferably, when carrying out dry etching, the carrying gas being passed through is H2、He、Ar、N2In one or more.
Preferably, when carrying out dry etching, pressure is 500-1000Torr in the dry-process etching cavity.
Preferably, when carrying out dry etching, the wafer is heated.
It is further preferred that the wafer is heated to 450 DEG C from room temperature.
In order to achieve the above objects and other related objects, the present invention also provides a kind of wafer thinning device, including：
Dry-process etching cavity；
Wafer warm table, in the dry-process etching cavity；
Sealing ring, it is installed in the dry-process etching cavity, is placed on the periphery of the wafer warm table；The sealing ring
Top is higher than the wafer warm table and blocks the peripheral edge of the wafer warm table, adds in the sealing ring and the wafer
Certain space is formed between thermal station；
Etching gas are passed through mouth, positioned at the top of the wafer warm table.
Preferably, the wafer thinning device is passed through mouth including edge-protected gas, and the edge-protected gas is passed through mouth
Between the bottom of the sealing ring and the wafer warm table.
Preferably, the wafer thinning device includes choke valve, and the choke valve is located at the dry-process etching cavity bottom.
Preferably, the wafer thinning device includes gas diffusion plate, and the gas diffusion plate is located at the etching gas
It is passed through between mouth and the wafer warm table.
As described above, the wafer thining method and device of the present invention, have the advantages that：
The present invention utilizes ClF3Dry etching carries out being thinned for wafer rear central area, and blocks wafer using sealing ring
Peripheral edge, jointing edge protective gas, protect the peripheral edge of wafer, side stayed in wafer periphery so as to be made
TAIKO wafers.Damaged present invention, avoiding mechanical lapping to caused by wafer, by setting up sealing ring and edge-protected gas,
The dry etching of high-speed can be carried out to the central area of wafer rear, relative to the TAIKO techniques of prior art, the present invention
Processing step is simplified, reduces production cost, improves product yield.
Brief description of the drawings
Fig. 1 is shown as the schematic diagram of wafer thining method provided in an embodiment of the present invention.
Fig. 2 is shown as the schematic diagram of wafer thinning device provided in an embodiment of the present invention.
Component label instructions
S1~S3 steps
1 dry-process etching cavity
2 wafer warm tables
3 sealing rings
4 etching gas are passed through mouth
5 edge-protected gases are passed through mouth
6 choke valves
7 gas diffusion plates
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.It should be noted that in the case where not conflicting, following examples and implementation
Feature in example can be mutually combined.
It should be noted that the diagram provided in following examples only illustrates the basic structure of the present invention in a schematic way
Think, only show the component relevant with the present invention in schema then rather than according to component count, shape and the size during actual implement
Draw, kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its assembly layout kenel
It is likely more complexity.
Referring to Fig. 1, the embodiment of the present invention provides a kind of wafer thining method, comprise the following steps：
S1 provides a wafer, and the wafer includes front and back, and the front is formed with IC naked cores；
The wafer frontside is put into dry-process etching cavity by S2 down, and the periphery sides of the wafer are blocked using sealing ring
Edge, only expose the central area of the thinned wafer rear of needs；
S3 is passed through etching gas ClF3Dry etching is carried out to preset thickness to the central area of the wafer rear, obtained
Thinned wafer.
As the preferred scheme of the present invention, edge-protected gas can be passed through in the space blocked by the sealing ring and is protected
Protect the peripheral edge of the wafer.Specifically, the edge-protected gas can be inert gas.Preferably, the edge is protected
It can be H to protect gas2、He、Ar、N2In one or more.Preferably, the edge-protected gas is from the lower section of the wafer
It is passed through in the space blocked by the sealing ring.
Specifically, when carrying out dry etching, the carrying gas being passed through can be H2、He、Ar、N2In one or more；Institute
It can be 500-1000Torr to state the pressure in dry-process etching cavity.Specifically, when carrying out dry etching, can heat described
Wafer, for example, the wafer is heated into 450 DEG C from room temperature.
This method utilizes ClF3Dry etching carries out being thinned for wafer rear central area, and blocks wafer using sealing ring
Peripheral edge, jointing edge protective gas, protect the peripheral edge of wafer, side stayed in wafer periphery so as to be made
TAIKO wafers.
Referring to Fig. 2, the embodiment of the present invention also provides a kind of wafer thinning device, including：Dry-process etching cavity 1, wafer
Warm table 2, sealing ring 3 and etching gas are passed through mouth 4.Wherein, wafer warm table 2 is located in the dry-process etching cavity 1；Sealing
Ring 3 is installed in the dry-process etching cavity 1, and is placed on the periphery of the wafer warm table 2；The top of the sealing ring 3 is high
In the wafer warm table 2 and the peripheral edge of the wafer warm table 2 is blocked, is heated in the sealing ring 3 and the wafer
Formed with certain space between platform 2；Etching gas are passed through the top that mouth 4 is located at the wafer warm table 2.
As the preferred scheme of the present invention, the wafer thinning device is also passed through mouth 5, the side including edge-protected gas
Edge protective gas is passed through mouth 5 and is located between bottom and the wafer warm table 2 of the sealing ring 3.
Specifically, the wafer thinning device also includes choke valve 6, and the choke valve 6 is located at the dry-process etching cavity 1
Bottom, the choke valve 6 can discharge the gas in the dry-process etching cavity 1, for controlling in the dry-process etching cavity 1
Air pressure.
Preferably, the wafer thinning device also includes gas diffusion plate 7, and the gas diffusion plate 7 is located at the etching
Gas is passed through between mouth 4 and the wafer warm table 2, for making the etching gas be passed through the etching gas diffusion of the introducing of mouth 4
Uniformly, be advantageous to uniformly etch, obtain preferable etching surface.Gas diffusion plate 7 can include multiple pod apertures or multiple
Guiding gutter, or other structures for diffusive gas flow.
The wafer thining method of the present invention can be realized using this wafer thinning device.Wherein, the sealing ring 3 is used as and matched somebody with somebody
Part is installed in the dry-process etching cavity 1, can be used fixed mechanism fixed position, can be taken out replacing.Can be according to reality
The TAIKO crystal circle structures needed design and processed the sealing ring 3 of different shape and size.For example, different edges can be equipped with
The sealing ring of size is preparing the TAIKO wafers of corresponding edge size.In addition, the height adjustable of the wafer warm table 2, adds
During the wafer of work different-thickness, it can be adapted to by adjusting the height of wafer warm table to adjust.
Technical scheme is described in detail below by specific example.
First, there is provided a piece of wafer for needing reduction processing.Typically Silicon Wafer.It is naked formed with IC in the front of wafer
Core.
Then, the wafer is put into the dry-process etching cavity 1 of above-mentioned wafer thinning device, makes the face down of the wafer
It is placed on wafer warm table 2.In practical operation, the ad-hoc location that wafer can be placed on wafer warm table 2, and keep brilliant
Round position does not change, it is for instance possible to use electrostatic chuck, vacuum cup or other suitable fixed mechanisms are fixed.
The sealing ring 3 that following selecting structure size corresponds to actual needs, such as the sealing ring with particular edge size
3, it is installed in dry-process etching cavity 1, is fastened in the periphery of the wafer warm table 2, sealing ring 3 is blocked the wafer
Peripheral edge, only expose the central area of the thinned wafer rear of needs.
During specific placement wafer, first by the lifting of sealing ring 3, after placing wafer, then sealing ring is fallen into installation and fixed.
Now, certain space is left between the sealing ring 3 and the wafer warm table 2, it is necessary to the crystal round fringes of protection
In the space.For the wafer periphery edge for preferably protecting needs to retain, edge-protected gas can be passed through in the space
Body, make there is no etching gas to enter reaction during dry etching.Under the limitation of sealing ring and the protection of edge-protected gas,
The central area of thinned wafer rear only in need is etched thinned.In the present embodiment, edge-protected gas is protected by edge
Shield gas is passed through mouth 5 and introduced, and edge-protected gas is passed through mouth 5 and is located between bottom and the wafer warm table 2 of sealing ring 3, so
For edge-protected gas from the space introduced below surrounded by the sealing ring of the wafer, protection air-flow from the bottom up can
Effectively to prevent etching gas from entering the space.
After device is adjusted, you can be passed through etching gas ClF3Dry method quarter is carried out to the central area of the wafer rear
Erosion, it is etched to preset thickness stopping, you can obtaining thinned wafer.Utilize ClF3Gas can carry out the quarter of high-speed to wafer
Erosion, accelerate the time of reduction process.Etching gas ClF3Mouth 4 can be passed through from the etching gas above wafer warm table 2
Introduce.It can be H to carry gas2、He、Ar、N2In one or more, in the present embodiment, carry gas also from wafer warm table
2 top introduces.Etching gas so in dry-process etching cavity 1 flow from top to bottom., can be with after etching gas are down passed through
Reacted after being spread uniformly via gas diffusion plate 7 with wafer, so as to can obtain the preferable etched surface of surface appearance.
During dry etching, the pressure in dry-process etching cavity 1, which can utilize, is located at the bottom of dry-process etching cavity 1
The choke valve 6 in portion is controlled between 500-1000Torr.Wafer is heated by wafer warm table 2, in the present embodiment, by institute
State wafer and be heated to 450 DEG C from room temperature.
The thinned wafer finally given can be applied to power device and BSI types cmos image sensing as TAIKO wafers
In device, its back side central area is uniformly thinned to preset thickness, and peripheral edge remains original thickness.
In summary, the present invention utilizes ClF3Dry etching carries out being thinned for wafer rear central area, and utilizes sealing
Ring blocks the peripheral edge of wafer, jointing edge protective gas, the peripheral edge of wafer is protected, so as to be made in wafer periphery
Stay the TAIKO wafers on side.Damaged present invention, avoiding mechanical lapping to caused by wafer, by setting up sealing ring and edge-protected
Gas, the dry etching of high-speed can be carried out to the central area of wafer rear, relative to the TAIKO techniques of prior art,
This invention simplifies processing step, reduces production cost, improves product yield.So the present invention effectively overcome it is existing
Various shortcoming in technology and have high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (13)
1. a kind of wafer thining method, it is characterised in that comprise the following steps：
A wafer is provided, the wafer includes front and back, and the front is formed with IC naked cores；
The wafer frontside is put into dry-process etching cavity down, the peripheral edge of the wafer is blocked using sealing ring, only
Expose the central area of the thinned wafer rear of needs；
It is passed through etching gas ClF3Dry etching is carried out to preset thickness to the central area of the wafer rear, obtained thinned
Wafer.
2. wafer thining method according to claim 1, it is characterised in that：Lead in the space blocked by the sealing ring
Enter the peripheral edge of wafer described in edge-protected gas shield.
3. wafer thining method according to claim 2, it is characterised in that：The edge-protected gas is inert gas.
4. wafer thining method according to claim 2, it is characterised in that：The edge-protected gas is H2、He、Ar、N2
In one or more.
5. wafer thining method according to claim 2, it is characterised in that：The edge-protected gas is under the wafer
Side is passed through the space blocked by the sealing ring.
6. wafer thining method according to claim 1, it is characterised in that：When carrying out dry etching, the carrying gas that is passed through
Body is H2、He、Ar、N2In one or more.
7. wafer thining method according to claim 1, it is characterised in that：When carrying out dry etching, the dry etching
Pressure is 500-1000Torr in cavity.
8. wafer thining method according to claim 1, it is characterised in that：When carrying out dry etching, the wafer is heated.
9. wafer thining method according to claim 8, it is characterised in that：The wafer is heated to 450 DEG C from room temperature.
A kind of 10. wafer thinning device, it is characterised in that including：
Dry-process etching cavity；
Wafer warm table, in the dry-process etching cavity；
Sealing ring, it is installed in the dry-process etching cavity, is placed on the periphery of the wafer warm table；The top of the sealing ring
Higher than the wafer warm table and the peripheral edge of the wafer warm table is blocked, in the sealing ring and the wafer warm table
Between form certain space；
Etching gas are passed through mouth, positioned at the top of the wafer warm table.
11. wafer thinning device according to claim 10, it is characterised in that：The wafer thinning device is protected including edge
Shield gas is passed through mouth, and the edge-protected gas is passed through mouth and is located between bottom and the wafer warm table of the sealing ring.
12. wafer thinning device according to claim 10, it is characterised in that：The wafer thinning device includes throttling
Valve, the choke valve are located at the dry-process etching cavity bottom.
13. wafer thinning device according to claim 10, it is characterised in that：The wafer thinning device expands including gas
Fall apart, the gas diffusion plate is located at the etching gas and is passed through between mouth and the wafer warm table.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610638222.5A CN107689326A (en) | 2016-08-05 | 2016-08-05 | A kind of wafer thining method and device |
| TW105142541A TWI602233B (en) | 2016-08-05 | 2016-12-21 | Method for thinning a wafer and device thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610638222.5A CN107689326A (en) | 2016-08-05 | 2016-08-05 | A kind of wafer thining method and device |
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| Publication Number | Publication Date |
|---|---|
| CN107689326A true CN107689326A (en) | 2018-02-13 |
Family
ID=61011314
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610638222.5A Pending CN107689326A (en) | 2016-08-05 | 2016-08-05 | A kind of wafer thining method and device |
Country Status (2)
| Country | Link |
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| CN (1) | CN107689326A (en) |
| TW (1) | TWI602233B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109599330A (en) * | 2018-11-30 | 2019-04-09 | 中国振华集团永光电子有限公司（国营第八七三厂） | A kind of wafer back side processing technology |
| CN110211870A (en) * | 2019-06-18 | 2019-09-06 | 北京北方华创微电子装备有限公司 | Wafer thining method |
| CN111446163A (en) * | 2020-03-27 | 2020-07-24 | 绍兴同芯成集成电路有限公司 | Wafer with edge stepped/gentle slope type protection ring and manufacturing method thereof |
| CN112133666A (en) * | 2020-09-28 | 2020-12-25 | 北京国联万众半导体科技有限公司 | Millimeter wave chip manufacturing method |
| CN115642112A (en) * | 2022-11-24 | 2023-01-24 | 西安奕斯伟材料科技有限公司 | Back sealing device and method for silicon wafer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109712926B (en) * | 2017-10-25 | 2021-01-22 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109599330A (en) * | 2018-11-30 | 2019-04-09 | 中国振华集团永光电子有限公司（国营第八七三厂） | A kind of wafer back side processing technology |
| CN110211870A (en) * | 2019-06-18 | 2019-09-06 | 北京北方华创微电子装备有限公司 | Wafer thining method |
| CN110211870B (en) * | 2019-06-18 | 2021-08-13 | 北京北方华创微电子装备有限公司 | Wafer thinning method |
| CN111446163A (en) * | 2020-03-27 | 2020-07-24 | 绍兴同芯成集成电路有限公司 | Wafer with edge stepped/gentle slope type protection ring and manufacturing method thereof |
| CN112133666A (en) * | 2020-09-28 | 2020-12-25 | 北京国联万众半导体科技有限公司 | Millimeter wave chip manufacturing method |
| CN115642112A (en) * | 2022-11-24 | 2023-01-24 | 西安奕斯伟材料科技有限公司 | Back sealing device and method for silicon wafer |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI602233B (en) | 2017-10-11 |
| TW201810407A (en) | 2018-03-16 |
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