CN107544770B - Analog multiplier-adder circuit with digital-analog mixed input and charge domain - Google Patents
Analog multiplier-adder circuit with digital-analog mixed input and charge domain Download PDFInfo
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Abstract
The invention discloses a digital-analog mixed input and charge domain analog multiplier-adder circuit, which is characterized by comprising the following components: n same multiplication units, each multiplication unit independently completes multiplication operation, and the output ends of the multiplication units are connected together to realize addition operation. The method realizes the multiply-add part with the largest occupied area and the largest power consumption in the neural network by using an analog circuit based on a charge transfer principle, and no static current exists during operation, so that the power consumption is greatly reduced, the linearity is improved, and the expandability is realized.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuits, and more particularly, to a charge domain analog multiplier-adder circuit with digital-analog hybrid input.
Background
An artificial neural network is a great research hotspot in the field of artificial intelligence at present, and successfully solves the practical problems which are difficult to solve by many modern computers in the fields of pattern recognition, automatic control, prediction estimation and the like.
Along with the increase of complexity of the problem to be solved, the calculation amount of the neural network is increased sharply, so that the rapid and low-power calculation of big data becomes important. Taking the most common Convolutional Neural Network (CNN) as an example, a large number of multiply-add operations exist in one operation, the traditional digital method for realizing multiplication has the defects of large occupied area, large power consumption and the like along with the increase of bits of a multiplier, and the research of an analog multiply-add device aims at solving the problems.
The analog circuit is very simple to implement addition and only needs to connect the output current to one point. Therefore, the key to analog multipliers is the implementation of the multipliers, the most common practice being to use gilbert cells and their modifications (m.holler, s.tam, h.castro, and r.benson, "electric train switchable concrete networks (ETANN) with 10240floating gate responses," in proc.int. joint conf. neural networks, Washington, June 1989, pp.191-196.). The tail current tube of the device is a floating gate transistor and is used for storing weight, and the product of differential current output which is proportional to the differential input and the weight is obtained through the current-voltage characteristic of the MOS tube, so that multiplication is realized. However, the structure has a disadvantage that static current exists, the problem of power consumption is not fundamentally solved, and the linearity is not good enough.
Disclosure of Invention
The invention aims to provide a digital-analog mixed input charge domain analog multiplier-adder circuit, which realizes the multiplication-addition part with the largest occupied area and the largest power consumption in a neural network by using an analog circuit based on a charge shifting principle, and has no quiescent current during operation, thereby greatly reducing the power consumption, improving the linearity and having expandability.
The purpose of the invention is realized by the following technical scheme:
a digital-to-analog hybrid input, charge-domain analog multiplier-adder circuit, comprising: n same multiplication units, each multiplication unit independently completes multiplication operation, and the output ends of the multiplication units are connected together to realize addition operation.
Each multiplication unit is divided into four bits, the internal structure of each bit is the same, the difference is the size of the MOS capacitor and the parallel plate capacitor, and the high bit is a double copy of the next high bit, namely the capacitance value is enlarged by two times.
Each bit comprises four basic units with the same structure and different input signals; each basic unit consists of a switch circuit and a multiplication circuit; the switching circuit includes: a PMOS switch M1, an NMOS switch M2, an NMOS switch M3, a PMOS switch M4, and an NMOS switch M5; the multiplication circuit includes: MOS capacitor and parallel plate capacitor connected in series; the source and drain electrodes of the MOS capacitor short circuit are connected to VDD through a PMOS switch M1 and are connected to GND through an NMOS switch M2, and the gates of the PMOS switch M1 and the NMOS switch M2 are connected together and controlled by an externally input digital signal X; the junction of the gate of the MOS capacitor and the upper plate of the parallel plate capacitor is connected to an external analog input signal W through an NMOS switch M3 and is connected to VDD through a PMOS switch M4, and the gates of the NMOS switch M3 and the PMOS switch M4 are controlled by an output signal of an external sequential circuit; the lower plate of the parallel plate capacitor is connected to GND through an NMOS switch M5, and the gate of the NMOS switch M5 is also controlled by the output signal of an external sequential circuit.
In one bit, the lower plates of the parallel plate capacitors of the left basic unit and the right basic unit are connected together, the analog input signals W are differential signals, and the control signals of the PMOS switch M1 and the NMOS switch M2 are in opposite phases; the analog input signals W of the upper and lower basic cells are the same, and the control signals of the PMOS switch M1 and the NMOS switch M2 are inverted.
The lower plates of the parallel plate capacitors in the basic units in the upper half part and the lower half part of the multiplication unit are respectively connected together and are connected to GND through the same NMOS switch, namely a common NMOS switch M5.
The technical scheme provided by the invention shows that (1) the calculation framework based on charge shifting has no static current and low calculation power consumption; (2) the differential weight inputs and outputs the differential weight, and the linearity is high; (3) can be expanded into more multiplication units, and each multiplication unit can also be expanded into more bits.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
FIG. 1 is a diagram of a digital-analog hybrid input, charge-domain analog multiplier-adder circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a multiplication unit according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of a basic unit in a multiplication unit provided by an embodiment of the present invention;
FIG. 4 is a graph illustrating a relationship between MOS capacitance and voltage according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating a state change of a basic unit in a multiplication unit of a multiplier-adder circuit according to an embodiment of the present invention;
FIG. 6 is a detailed circuit diagram of a single bit in a multiplication unit of the multiplier-adder circuit according to the present invention;
fig. 7 is a diagram of input/output linear relationship of the multiplication unit according to the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic diagram of a digital-analog hybrid input charge domain analog multiplier-adder circuit according to an embodiment of the present invention. As shown in fig. 1, it mainly includes: n same multiplication units, each multiplication unit independently completes multiplication operation, and the output ends of the multiplication units are connected together to realize addition operation. In this embodiment, N may be set to 16, but the specific value may be adjusted according to the actual situation.
In the embodiment of the present invention, the digital signal input by each multiplication unit may be 4 bits, so that each multiplication unit may be divided into four bits, each bit has the same internal structure, and is different in the size of the MOS capacitor and the parallel plate capacitor, and the high bit is a double copy of the second high bit, that is, the capacitance value is doubled, as shown in fig. 2.
In the embodiment of the invention, each bit comprises four basic units with the same structure but different input signals; each basic unit consists of a switch circuit and a multiplication circuit; the switch circuit is composed of a plurality of MOS switches and realizes the control of analog weight input, the control of digital input and the reading of an operation result; the multiplication circuit is formed by connecting an MOS capacitor and a parallel plate capacitor (which can be realized by an MIM capacitor) with a small capacitance value in series, and the multiplication of a charge domain is realized.
As shown in fig. 3, each bit includes four basic units with the same structure and different input signals; each basic unit consists of a switch circuit and a multiplication circuit; the switching circuit includes: a PMOS switch M1, an NMOS switch M2, an NMOS switch M3, a PMOS switch M4, and an NMOS switch M5; the multiplication circuit includes: MOS capacitor and parallel plate capacitor connected in series; the source and drain electrodes of the MOS capacitor short circuit are connected to VDD through a PMOS switch M1 and are connected to GND through an NMOS switch M2, and the gates of the PMOS switch M1 and the NMOS switch M2 are connected together and controlled by an externally input digital signal X; the junction of the gate of the MOS capacitor and the upper plate of the parallel plate capacitor is connected to an external analog input signal W through an NMOS switch M3 and is connected to VDD through a PMOS switch M4, and the gates of the NMOS switch M3 switch and the PMOS switch M4 are controlled by an output signal of an external sequential circuit; the lower plate of the parallel plate capacitor is connected to GND through an NMOS switch M5, and the gate of the NMOS switch M5 is also controlled by the output signal of an external sequential circuit.
In the embodiment of the invention, in one bit, the lower polar plates of the parallel plate capacitors of the left basic unit and the right basic unit are connected together, the analog input signals W are differential signals, and the control signals of the PMOS switch M1 and the NMOS switch M2 are in opposite phases; the analog input signals W of the upper and lower basic cells are the same, and the control signals of the PMOS switch M1 and the NMOS switch M2 are inverted.
In the embodiment of the invention, the lower plates of the parallel plate capacitors in the basic units in the upper half part and the lower half part of the multiplication unit are respectively connected together and are connected to GND through the same NMOS switch, namely the common NMOS switch M5.
The present invention is based on a basic principle that a MOS capacitance value jumps around a threshold voltage, as shown in fig. 4. Let the smaller value of the capacitor be C1 and the larger value be C2.
Taking a simplified basic cell as an example, fig. 5 shows two state changes that the basic cell may undergo, which are state 1- > state 2 or state 1- > state 3. In the first case, the switch is closed first, the external analog input W (> Vth) charges the MOS capacitor and the parallel plate capacitor, and the charge on both capacitors after stabilization and the total charge at the junction can be expressed as:
in the above formula, W represents an external analog input signal, C2Representing the capacitance of the MOS capacitor in state 1, C0Capacitance value, Q, representing the parallel plate capacitance2Representing the amount of charge, Q, stored by the MOS capacitor in state 11Representing the amount of charge stored by the parallel plate capacitance in state 1, and Q representing the total charge at the junction of the MOS capacitance and the parallel plate capacitance.
Then the switch is turned off, and the voltage of the upper plate of the MOS capacitor keeps GND unchanged. Because there is no discharging loop between the lower plate of MOS capacitor and the upper plate of parallel plate capacitor, the charges on the two capacitors remain unchanged:
Q′1＝Q1＝C0W (2)
in the above formula, Q1' represents the amount of charge stored by the parallel plate capacitance in state 2.
In the second case, the state 1 is the same as the first case, but after the switch is turned off, the voltage of the upper plate of the MOS capacitor changes from GND to VDD, and the MOS capacitor changes from C2 to C1. However, no discharging loop is arranged between the lower plate of the MOS capacitor and the upper plate of the parallel plate capacitor, and the total charge is kept unchanged. From conservation of charge, the charge on the parallel plate capacitance can be expressed as:
in the above formula, VDD is power voltage, C1Representing the capacitance, Q, of the MOS capacitor in state 31'' represents the amount of charge stored by the parallel plate capacitance in state 3.
It can be seen from equations (2) and (3) that the charge on the parallel plate capacitance is always linear with W, regardless of the state change. For convenience of description, the charge on the parallel plate capacitance after change is written as:
in the above formula, k1, k2, b2 are amounts introduced for convenience of expression, and k1 represents C in formula (2)0K2 represents the coefficient of W in formula (3)
b2 represents formula (3)
A single-bit unit is composed of four basic units, as shown in fig. 6, where Vx is VDD or GND, and Vx _ is an inverse of Vx, that is, Vx is VDD and Vx _ GND; vx is GND and VDD. Taking the lowest bit as an example, when Vx is VDD, there are:
in the above formula, Q+Represents the total amount of output charge of the upper half of the single bit cell, Q-represents the total amount of output charge of the lower half of the single bit cell, Wcm represents the common mode amount of the external analog input signal, Wdm represents the differential mode amount of the external analog input signal, and Δ Q represents the differential charge amount of the output of the single bit cell.
When Vx is GND, there are:
from formulas (5) and (6), it can be obtained:
ΔQ＝(-1)1-X0(k2-k1)*2Wdm(7)
in the above equation, X0 is the lowest bit of the externally input digital control signal, which controls the conversion of Vx in fig. 6, and when X0 is 1, Vx is VDD; when X0 is equal to 0, Vx is equal to GND.
For the next low bit, the parallel plate capacitance C0 becomes 2C0, and each of the original MOS capacitances also becomes twice, i.e., C1 becomes 2C1, C2 becomes 2C2, then k1 and k2 become 2k1 and 2k2, resulting in:
ΔQ＝(-1)1-X1*2(k2-k1)*2Wdm
by analogy, the output charge difference of a multiplication unit containing four bits can be written as:
ΔQ4bit＝(-1)1-X0*(k2-k1)*2Wdm+(-1)1-X1*2(k2-k1)*2Wdm+(-1)1-X2*4(k2-k1)*2Wdm+(-1)1-X3*8(k2-k1)*2Wdm
＝2Wdm(k2-k1)[(-1)1-X0*20+(-1)1-X1*21+(-1)1-X2*22+(-1)1-X3*23]
let X be (-1)1-X0*20+(-1)1-X1*21+(-1)1-X2*22+(-1)1-X3*23
ΔQ4bit＝2(k2-k1)WdmX (8)
In the above formula,. DELTA.Q4bitX3, X2, X1, and X0 represent the highest bit, the second lowest bit, and the lowest bit of an externally input four-bit digital control signal, respectively.
The invention comprises 16 multiply-add units, and the output total charge difference can be written as:
ΔQgeneral assembly＝2(k2-k1)(Wdm*X1+Wdm*X2+…+Wdm*X16) (1)
In the above formula,. DELTA.QGeneral assemblyRepresenting the total differential output charge of the 16 multiply-add units, XiRepresenting the digital input of the ith multiplication unit.
The above equation is the multiplication and addition operation. It can be seen that the essence of the multiplication is the movement of charges, the operation in the charge domain, and no static current exists, thus fundamentally reducing the power consumption.
In the embodiment of the invention, a 180nm CMOS process can be adopted, and the simulation result is as follows: the present invention consumes 10.5696uW for one multiply-add operation under 25MHz bandwidth, and 0.6606uW for one multiply unit on average, whereas the multiply-add device using Gilbert unit mentioned in the background art consumes 0.15mW per synapse under 334kHz bandwidth (M.Ngwar, J.Wight, "A full Integrated Analog Neuron for Dynamic Multi-layer Perception networks," IEEE IJCNN, Jul.2015.). It can be seen that the present invention greatly reduces power consumption.
In addition, the multiplier of the present invention has a good linearity, and as shown in fig. 7, in the multiplying unit, the differential output and the differential input weight have a highly linear relationship in the case of different digital inputs.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (4)
1. A digital-to-analog hybrid input, charge-domain analog multiplier-adder circuit, comprising: n identical multiplication units, wherein each multiplication unit independently completes multiplication operation, and the output ends of the multiplication units are connected together to realize addition operation;
each bit in each multiplication unit has the same internal structure, and each bit comprises four basic units with the same structure and different input signals; each basic unit consists of a switch circuit and a multiplication circuit; the switching circuit includes: a PMOS switch M1, an NMOS switch M2, an NMOS switch M3, a PMOS switch M4, and an NMOS switch M5; the multiplication circuit includes: MOS capacitor and parallel plate capacitor connected in series; the source and drain electrodes of the MOS capacitor short circuit are connected to VDD through a PMOS switch M1 and are connected to GND through an NMOS switch M2, and the gates of the PMOS switch M1 and the NMOS switch M2 are connected together and controlled by an externally input digital signal X; the junction of the gate of the MOS capacitor and the upper plate of the parallel plate capacitor is connected to an external analog input signal W through an NMOS switch M3 and is connected to VDD through a PMOS switch M4, and the gates of the NMOS switch M3 and the PMOS switch M4 are controlled by an output signal of an external sequential circuit; the lower plate of the parallel plate capacitor is connected to GND through an NMOS switch M5, and the gate of the NMOS switch M5 is also controlled by the output signal of an external sequential circuit.
2. The digital-to-analog hybrid input, charge-domain analog multiplier-adder circuit of claim 1,
each multiplication unit is divided into four bits, the internal structure of each bit is the same, the difference is the size of the MOS capacitor and the parallel plate capacitor, and the high bit is a double copy of the next high bit, namely the capacitance value is enlarged by two times.
3. The digital-to-analog hybrid input, charge-domain analog multiplier-adder circuit of claim 1,
in one bit, the lower plates of the parallel plate capacitors of the left basic unit and the right basic unit are connected together, the analog input signals W are differential signals, and the control signals of the PMOS switch M1 and the NMOS switch M2 are in opposite phases; the analog input signals W of the upper and lower basic cells are the same, and the control signals of the PMOS switch M1 and the NMOS switch M2 are inverted.
4. The digital-to-analog hybrid input, charge-domain analog multiplier-adder circuit of claim 1,
the lower plates of the parallel plate capacitors in the basic units in the upper half part and the lower half part of the multiplication unit are respectively connected together and are connected to GND through the same NMOS switch, namely a common NMOS switch M5.
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