CN107544770A - A kind of numerical model analysis input, charge-domain simulation adder and multiplier circuit - Google Patents
A kind of numerical model analysis input, charge-domain simulation adder and multiplier circuit Download PDFInfo
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Abstract
The invention discloses a kind of input of numerical model analysis, charge-domain simulation adder and multiplier circuit, it is characterised in that including：N number of identical multiplication unit, each multiplication unit complete independently multiplying, the output end of each multiplication unit link together, and realize add operation.This method realizes the multiply-add part that area occupied in neutral net is maximum, power consumption is maximum with the analog circuit that principle is moved based on electric charge, and quiescent current is not present during computing, so as to greatly reduce power consumption, while improves the linearity, and have scalability.
Description
Technical field
The present invention relates to semiconductor integrated circuit field, more particularly to a kind of input of numerical model analysis, charge-domain simulation
Adder and multiplier circuit.
Background technology
Artificial neural network is a big study hotspot of current artificial intelligence field, its in pattern-recognition, automatically control, in advance
Survey the fields such as estimation and successfully solve the insoluble practical problem of many modern computers.
Solves the problems, such as the raising of complexity with required, neural computing amount also increases suddenly, so big data is carried out fast
Speed calculates with low power just becomes most important.By taking the most frequently used convolutional neural networks (CNN) as an example, in once-through operation there is
Substantial amounts of multiply-add operation, traditional digital method realize increase of the multiplication with multiplier bit, and there is area occupied is big, work(
The shortcomings of big is consumed, and the research for simulating adder and multiplier aims to solve the problem that these problems.
Analog circuit realizes that addition is very simple, only output current need to be connected into a bit.Therefore, adder and multiplier is simulated
The crucial realization in multiplier, way most commonly be using Gilbert cell and its improve circuit (M.Holler,
S.Tam,H.Castro,and R.Benson,“An electrically trainableartificial neural
network(ETANN)with 10240floating gate synapses,”in Proc.Int.Joint Conf.Neural
Networks,Washington,June 1989,pp.191–196.).Its tail current pipe is floating transistor, for storing
Weight, difference current output is obtained by the current-voltage characteristic of metal-oxide-semiconductor and is proportional to the product of Differential Input and weight, so as to real
Existing multiplication.But this structure is exactly quiescent current be present in the presence of a shortcoming, does not solve power problemses, and line fundamentally
Property degree is also not good enough.
The content of the invention
It is an object of the invention to provide a kind of input of numerical model analysis, charge-domain simulation adder and multiplier circuit, by nerve net
The multiply-add part that area occupied is maximum in network, power consumption is maximum realized with the analog circuit that principle is moved based on electric charge, during computing not
Quiescent current be present, so as to greatly reduce power consumption, while improve the linearity, and there is scalability.
The purpose of the present invention is achieved through the following technical solutions：
A kind of numerical model analysis input, charge-domain simulation adder and multiplier circuit, including：N number of identical multiplication unit, respectively multiplies
Method unit complete independently multiplying, the output end of each multiplication unit link together, and realize add operation.
Each multiplication unit is divided into four bits, and each bit internal structure is identical, unlike mos capacitance and
The size of parallel plate capacitor, higher bit are the double renditions of time higher bit, i.e. capacitance expands twice.
Each bit includes four elementary cells that structure is identical and input signal is different；Each elementary cell is by switching
Circuit and multiplying operational circuit composition；The on-off circuit includes：PMOS switch M1, nmos switch M2, nmos switch M3,
PMOS switch M4 and nmos switch M5；The multiplying operational circuit includes：Mos capacitance and the parallel-plate electricity being cascaded
Hold；Wherein, the source-drain electrode of the mos capacitance short circuit is connected to VDD by PMOS switch M1, is connected to by nmos switch M2 on GND,
The data signal X controls that PMOS switch M1 and nmos switch M2 grid connect together by outside input；The mos capacitance
The junction of grid and the top crown of the parallel plate capacitor, the analog input signal W of outside is connected to by nmos switch M3,
VDD, nmos switch M3 and PMOS switch M4 grid are connected to by the output signal of outside sequence circuit by PMOS switch M4
Control；The parallel plate capacitor bottom crown is connected to GND by nmos switch M5, and nmos switch M5 grid is also by outside sequential electricity
The output signal control on road.
In a bit, the bottom crown of the parallel plate capacitor of two elementary cells in left and right links together, and simulation is defeated
Enter signal W differential signals each other, and PMOS switch M1 and nmos switch M2 control signal are anti-phase；Upper and lower two elementary cells
Analog input signal W it is identical, and PMOS switch M1 and nmos switch M2 control signal are anti-phase.
The bottom crown of parallel plate capacitor in upper and lower two half part of multiplication unit in elementary cell is respectively coupled one
Rise, GND is connected to by same nmos switch, that is, share nmos switch M5.
As seen from the above technical solution provided by the invention, the computing architecture that (1) is moved based on electric charge, without static state
Electric current, calculate low in energy consumption；(2) difference weight input difference exports, and the linearity is high；(3) more multiplication units are extendable to, often
Individual multiplication unit is also extendable to more bits.
Brief description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Accompanying drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill in field, on the premise of not paying creative work, other can also be obtained according to these accompanying drawings
Accompanying drawing.
Fig. 1 is a kind of showing for numerical model analysis input, charge-domain simulation adder and multiplier circuit provided in an embodiment of the present invention
It is intended to；
Fig. 2 is the circuit diagram of multiplication unit provided in an embodiment of the present invention；
Fig. 3 is the circuit diagram of the elementary cell in multiplication unit provided in an embodiment of the present invention；
Fig. 4 is the graph of relation of mos capacitance value provided in an embodiment of the present invention and voltage；
Fig. 5 is the state change map of the elementary cell in multiplication unit in adder and multiplier circuit provided in an embodiment of the present invention；
Fig. 6 is the detailed circuit diagram of the single-bit in multiplication unit in adder and multiplier circuit provided in an embodiment of the present invention；
Fig. 7 is the input and output linear relationship figure of multiplication unit provided in an embodiment of the present invention.
Embodiment
With reference to the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Ground describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.Based on this
The embodiment of invention, the every other implementation that those of ordinary skill in the art are obtained under the premise of creative work is not made
Example, belongs to protection scope of the present invention.
Fig. 1 is a kind of showing for numerical model analysis input, charge-domain simulation adder and multiplier circuit provided in an embodiment of the present invention
It is intended to.As shown in figure 1, it mainly includes：N number of identical multiplication unit, each multiplication unit complete independently multiplying, each multiplication
The output end of unit links together, and realizes add operation.In the present embodiment, N=16 can be set, but specific value can root
Adjusted according to actual conditions.
In the embodiment of the present invention, the data signal of each multiplication unit input can be 4bit, therefore, can multiply each
Method unit is divided into four bits, and each bit internal structure is identical, unlike mos capacitance and parallel plate capacitor it is big
Small, higher bit is the double rendition of time higher bit, i.e. twice of capacitance expansion, as shown in Figure 2.
In the embodiment of the present invention, each bit includes four elementary cells that structure is identical but input signal is different；Often
One elementary cell is made up of on-off circuit and multiplying operational circuit；The on-off circuit is made up of multiple MOS switches, realizes mould
Intend control, the control of numeral input and the reading of operation result of weight input；The multiplying operational circuit is by a MOS electricity
Hold and a less parallel plate capacitor of capacitance (can be realized with MIM capacitor) is in series, realize the multiplication fortune of charge-domain
Calculate.
As shown in figure 3, each bit includes four elementary cells that structure is identical and input signal is different；It is each basic
Unit is made up of on-off circuit and multiplying operational circuit；The on-off circuit includes：PMOS switch M1, nmos switch M2,
Nmos switch M3, PMOS switch M4 and nmos switch M5；The multiplying operational circuit includes：The mos capacitance being cascaded
And parallel plate capacitor；Wherein, the source-drain electrode of the mos capacitance short circuit is connected to VDD by PMOS switch M1, passes through nmos switch M2
It is connected on GND, PMOS switch M1 and nmos switch M2 grid connect together to be controlled by the data signal X of outside input；Institute
The junction of the grid of mos capacitance and the top crown of the parallel plate capacitor is stated, the mould of outside is connected to by nmos switch M3
Intend input signal W, VDD is connected to by PMOS switch M4, when nmos switch M3 is switched with PMOS switch M4 grid by outside
The output signal control of sequence circuit；The parallel plate capacitor bottom crown is connected to GND, nmos switch M5 grid by nmos switch M5
Pole is also controlled by the output signal of outside sequence circuit.
In the embodiment of the present invention, in a bit, the bottom crown of the parallel plate capacitor of two elementary cells in left and right connects
It is connected together, analog input signal W differential signals, and PMOS switch M1 and nmos switch M2 control signal are anti-phase each other；
The analog input signal W of upper and lower two elementary cells is identical, and PMOS switch M1 and nmos switch M2 control signal are anti-phase.
In the embodiment of the present invention, the lower pole of the parallel plate capacitor in upper and lower two half part of multiplication unit in elementary cell
Plate is respectively coupled together, and GND is connected to by same nmos switch, that is, shares nmos switch M5.
The present invention is that near threshold voltage saltus step occurs for mos capacitance value based on a most basic principle, such as Fig. 4 institutes
Show.Remember that electric capacity smaller value is C1, higher value C2.
By taking simplified elementary cell as an example, Fig. 5 is the two states change that elementary cell may undergo, and is divided into state 1->
State 2 or state 1->State 3.In the first situation, switch first closes, outside simulation input W (>Vth mos capacitance) is given
Charged with parallel plate capacitor, the total electrical charge of electric charge and junction after stabilization on two electric capacity can be expressed as：
In above formula, W represents outside analog input signal, C2Represent capacitance of the mos capacitance in state 1, C0Represent flat
The capacitance of andante electric capacity, Q2Represent the quantity of electric charge that mos capacitance stores in state 1, Q1Parallel plate capacitor is represented in state 1
The quantity of electric charge of storage, Q represent the total charge dosage at mos capacitance and parallel-plate capacitance connection.
Then switch off, mos capacitance top crown voltage keeps GND constant.Due to mos capacitance bottom crown and parallel-plate electricity
Holding between top crown does not have a discharge loop, and electric charge is kept constant on two electric capacity：
Q′1=Q1=C0W (2)
In above formula, Q1' represent the quantity of electric charge that parallel plate capacitor stores in state 2.
It is identical with the first situation in state 1 in second of situation, but after switching off, the electricity of mos capacitance top crown
Pressure changes to VDD by GND, and now mos capacitance changes to C1 by C2.But mos capacitance bottom crown and parallel plate capacitor top crown it
Between there is no a discharge loop yet, total electrical charge keeps constant.According to charge conservation, the electric charge on parallel plate capacitor can be expressed as：
In above formula, VDD is supply voltage, C1Represent capacitance of the mos capacitance in state 3, Q1' ' represents parallel plate capacitor
The quantity of electric charge stored in state 3.
From formula (2) and formula (3) as can be seen that no matter which kind of state change, electric charge on parallel plate capacitor is always with W into line
Sexual intercourse.In order to state below conveniently, the electric charge on parallel plate capacitor after change is designated as：
In above formula, k1, k2, b2 are the amounts in order to express easily introduced, and k1 represents the C in formula (2)0, k2 represents formula
(3) W coefficient inB2 represents formula (3)
A single-bit cells are formed by four elementary cells, as shown in fig. 6, wherein Vx=VDD or GND, Vx_ are Vx
It is anti-phase, i.e. Vx=VDD, Vx_=GND；Vx=GND, Vx_=VDD.By taking lowest bit as an example, as Vx=VDD, have：
In above formula, Q+The output total charge dosage of single-bit cells top half is represented, Q- represents single-bit cells lower half
The output total charge dosage divided, Wcm represent the common mode amount of outside analog input signal, and Wdm represents outside analog input signal
Differential mode amount, Δ Q represent single-bit cells output differential charge amount.
As Vx=GND, have：
It can be obtained from formula (5) and formula (6)：
Δ Q=(- 1)1-X0(k2-k1)*2Wdm (7)
In above formula, X0 is the lowest bit position of the digital controlled signal of outside input, and Vx conversion, works as X0 in control figure 6
When=1, Vx=VDD；Work as X0=0, Vx=GND.
For secondary low bit, parallel plate capacitor C0 is changed into 2C0, and original each mos capacitance also becomes twice as, i.e.,
C1 is changed into 2C1, and C2 is changed into 2C2, then k1 and k2 are changed into 2k1 and 2k2, cause：
Δ Q=(- 1)1-X1*2(k2-k1)*2Wdm
By that analogy, the output charge difference of the multiplication unit comprising four bits can be written as：
ΔQ4bit=(- 1)1-X0*(k2-k1)*2Wdm+(-1)1-X1*2(k2-k1)*2Wdm+(-1)1-X2*4(k2-k1)*2Wdm+
(-1)1-X3*8(k2-k1)*2Wdm
=2Wdm(k2-k1)[(-1)1-X0*20+(-1)1-X1*21+(-1)1-X2*22+(-1)1-X3*23]
Make X=(- 1)1-X0*20+(-1)1-X1*21+(-1)1-X2*22+(-1)1-X3*23
ΔQ4bit=2 (k2-k1)WdmX (8)
In above formula, Δ Q4bitThe differential charge amount of the multiplication unit output of four bits is represented, X3, X2, X1, X0 are represented respectively
The highest bit of four digital bit control signals of outside input, secondary higher bit, secondary low bit, lowest bit.
The present invention includes 16 multiplicaton addition units, and output total electrical charge difference can be written as：
ΔQAlways=2 (k2-k1)(Wdm*X1+Wdm*X2+…+Wdm*X16) (1)
In above formula, Δ QAlwaysRepresent total difference output quantity of electric charge of 16 multiplicaton addition units, XiRepresent the number of i-th of multiplication unit
Word inputs.
Above formula is multiply-add operation.As can be seen that the essence of multiplying is moving for electric charge, it is the fortune in charge-domain
Calculate, in the absence of quiescent current, therefore fundamentally reduce power consumption.
In the embodiment of the present invention, 180nm CMOS technologies can be used, simulation result is：The present invention under 25MHz bandwidth,
Multiply-add operation consumption power 10.5696uW, an average multiplication unit consumption 0.6606uW are completed, and background technology is carried
The adder and multiplier using Gilbert cell arrived under 334kHz bandwidth each cynapse consumption power 0.15mW (M.Ngwar,
J.Wight,“A Fully Integrated Analog Neuron for Dynamic Multi-layer Perceptron
Networks,”IEEE IJCNN,Jul.2015.).It can be seen that the present invention greatly reduces power consumption.
In addition, the linearity of multiplier is preferable in the present invention, as shown in fig. 7, in multiplication unit, different digital defeated
In the case of entering, difference output and Differential Input weight have very high linear relationship.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art is in the technical scope of present disclosure, the change or replacement that can readily occur in,
It should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of claims
Enclose and be defined.
Claims (5)
- A kind of 1. numerical model analysis input, charge-domain simulation adder and multiplier circuit, it is characterised in that including：N number of identical multiplication Unit, each multiplication unit complete independently multiplying, the output end of each multiplication unit link together, and realize add operation.
- A kind of 2. numerical model analysis input, charge-domain simulation adder and multiplier circuit according to claim 1, it is characterised in thatEach multiplication unit is divided into four bits, and each bit internal structure is identical, unlike mos capacitance with it is parallel The size of plate electric capacity, higher bit are the double renditions of time higher bit, i.e. capacitance expands twice.
- A kind of 3. numerical model analysis input, charge-domain simulation adder and multiplier circuit according to claim 2, it is characterised in thatEach bit includes four elementary cells that structure is identical and input signal is different；Each elementary cell is by on-off circuit And multiplying operational circuit composition；The on-off circuit includes：PMOS switch M1, nmos switch M2, nmos switch M3, PMOS are opened Close M4 and nmos switch M5；The multiplying operational circuit includes：The mos capacitance and parallel plate capacitor being cascaded；Wherein, The source-drain electrode of the mos capacitance short circuit is connected to VDD by PMOS switch M1, is connected to by nmos switch M2 on GND, PMOS switch The data signal X controls that M1 and nmos switch M2 grid connect together by outside input；The grid of the mos capacitance and institute The junction of the top crown of parallel plate capacitor is stated, the analog input signal W of outside is connected to by nmos switch M3, passes through PMOS The grid that switch M4 is connected to VDD, nmos switch M3 and PMOS switch M4 is controlled by the output signal of outside sequence circuit；It is described Parallel plate capacitor bottom crown is connected to GND by nmos switch M5, and nmos switch M5 grid is also by the output of outside sequence circuit Signal controls.
- A kind of 4. numerical model analysis input, charge-domain simulation adder and multiplier circuit according to claim 3, it is characterised in thatIn a bit, the bottom crown of the parallel plate capacitor of two elementary cells in left and right links together, simulation input letter Number W differential signals, and PMOS switch M1 and nmos switch M2 control signal are anti-phase each other；The mould of upper and lower two elementary cells It is identical to intend input signal W, and PMOS switch M1 and nmos switch M2 control signal are anti-phase.
- A kind of 5. numerical model analysis input, charge-domain simulation adder and multiplier circuit according to claim 3, it is characterised in thatThe bottom crown of parallel plate capacitor in upper and lower two half part of multiplication unit in elementary cell is respectively coupled together, GND is connected to by same nmos switch, that is, shares nmos switch M5.
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| CN111639757A (en) * | 2020-04-11 | 2020-09-08 | 复旦大学 | Simulation convolution neural network based on flexible material |
| CN112424785A (en) * | 2018-07-17 | 2021-02-26 | 索尼公司 | Calculation device, product accumulation operation circuit, and product accumulation operation system |
| CN115136239A (en) * | 2020-04-13 | 2022-09-30 | 国际商业机器公司 | Three-capacitor differential mixed signal multiplier |
| CN115658012A (en) * | 2022-09-30 | 2023-01-31 | 杭州智芯科微电子科技有限公司 | Vector multiplier-adder SRAM analog memory computing device and electronic equipment |
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Effective date of registration: 20211224 Address after: 230000 China (Anhui) pilot Free Trade Zone, Hefei, Anhui Province a1205-a1208, future center, Institute of advanced technology, University of science and technology of China, No. 5089, Wangjiang West Road, high tech Zone, Hefei Patentee after: Hefei Zhongke microelectronics Innovation Center Co.,Ltd. Address before: 230026 Jinzhai Road, Baohe District, Hefei, Anhui Province, No. 96 Patentee before: University of Science and Technology of China |