CN107544019B - Chip testing device and chip testing method - Google Patents
Chip testing device and chip testing method Download PDFInfo
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- CN107544019B CN107544019B CN201710722024.1A CN201710722024A CN107544019B CN 107544019 B CN107544019 B CN 107544019B CN 201710722024 A CN201710722024 A CN 201710722024A CN 107544019 B CN107544019 B CN 107544019B
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Abstract
The application discloses a chip testing device and a chip testing method, and belongs to the technical field of electronics. The chip testing device comprises a chip fixing groove and a mainboard placing groove; a chip test interface is arranged in the chip fixing groove; the mainboard placing groove is internally provided with a test interface and a mainboard interface, one end of the test interface can be connected with the input and output interface of the mainboard placed in the mainboard placing groove, and the other end of the test interface is used for transmitting data with the input and output interface of the mainboard. This is disclosed through set up chip fixed slot, mainboard standing groove and with the test interface of the input/output interface connection on the mainboard in chip testing arrangement, when testing the chip through this chip testing arrangement, place the chip in the chip fixed slot to place the mainboard that the chip corresponds back in the mainboard standing groove, just can test whether the chip is good through test interface. The problem of the relatively low efficiency of chip testing among the correlation technique is solved. The effect of higher test efficiency of the chip is achieved.
Description
Technical Field
The present disclosure relates to the field of electronic technologies, and in particular, to a chip testing apparatus and a chip testing method.
Background
The chip of the mobile terminal usually includes components such as a Central Processing Unit (CPU) and a Graphics Processing Unit (GPU), and is used for implementing various functions of the mobile terminal.
At present, when a chip of a mobile terminal is tested, the chip is usually welded on a chip interface on a mainboard corresponding to the chip, then an input/output interface of the mainboard is connected with a test lead, test data is input into the test lead, and whether the chip is good or not can be known by receiving data fed back by the mainboard from the test lead.
In implementing the present disclosure, the inventors found that the related art has at least the following problems: according to the method, the chip and the mainboard need to be welded, and the input and output interface on the mainboard needs to be connected with the test lead, so that the test efficiency of the chip is low.
Disclosure of Invention
In order to solve the problem of low chip testing efficiency in the related art, the embodiment of the disclosure provides a chip testing device and a chip testing method. The technical scheme is as follows:
according to a first aspect of the present disclosure, there is provided a chip testing device, comprising a chip fixing groove and a motherboard placing groove;
a chip testing interface is arranged in the chip fixing groove, and one end of the chip testing interface can be connected with a chip placed in the chip fixing groove;
the test board comprises a main board placing groove and is characterized in that a test interface and a main board interface are arranged in the main board placing groove, one end of the test interface can be connected with an input/output interface of a main board placed in the main board placing groove, the other end of the test interface is used for transmitting data with the input/output interface of the main board, one end of the main board interface is connected with the other end of the chip test interface, and the other end of the main board interface can be connected with a chip interface of the main board.
Optionally, the input/output interface of the motherboard includes an external bus interface, the chip testing apparatus further includes a wireless communication module,
the test interface comprises a transmission interface, one end of the transmission interface is connected with the wireless communication module, and the other end of the transmission interface can be connected with an external bus interface of the mainboard;
the wireless communication module is used for establishing wireless communication connection with an external control device and transmitting data between the external control device and the mainboard.
Optionally, the input/output interface of the motherboard includes a functional interface,
the chip testing device also comprises a functional component which can realize various functions of the terminal corresponding to the mainboard;
the test interface further comprises a function test interface, one end of the function test interface is connected with the function component, and the other end of the function test interface can be connected with the function interface of the mainboard.
Optionally, the input/output interface of the main board further includes a key interface,
the chip testing device also comprises a functional key, and the testing interface also comprises a key testing interface;
one end of the key test interface can be connected with the key interface of the mainboard, the other end of the key test interface is connected with the function key, and the function key is used for controlling the function component.
Optionally, the motherboard placement groove is further provided with a power supply interface, and the power supply interface can be connected with the power supply interface on the motherboard.
Optionally, the chip testing apparatus further includes a display, and the display is configured to display the current and the voltage of the power supply interface.
Optionally, one end of the motherboard interface in the motherboard placing groove is detachably connected to the other end of the chip testing interface in the chip fixing groove.
Optionally, one end of the chip test interface may be detachably connected to the chip in the chip fixing slot.
According to a second aspect of the present disclosure, there is provided a chip testing method for testing a target chip by the chip testing apparatus of the first aspect, the chip testing apparatus including a chip fixing groove and a motherboard placing groove, the method comprising:
placing the mainboard corresponding to the target chip in the mainboard placing groove, wherein one end of a test interface in the mainboard placing groove is connected with an input/output interface of the mainboard, and a chip interface of the mainboard is connected with the other end of the mainboard interface of the mainboard placing groove;
fixing the target chip in the chip fixing groove, wherein the target chip is connected with one end of a chip testing interface in the chip fixing groove, and the other end of the chip testing interface is connected with one end of the mainboard interface;
and testing the target chip through the other end of the test interface.
Optionally, one end of the motherboard interface in the motherboard placement slot is detachably connected with the other end of the chip testing interface in the chip fixing slot,
before the fixing the target chip in the chip fixing groove, the method further includes:
obtaining the chip fixing groove, wherein the chip fixing groove is a chip fixing groove corresponding to the target chip;
and connecting the other end of the chip testing interface in the chip fixing groove with one end of the mainboard interface in the mainboard placing groove.
The technical scheme provided by the embodiment of the disclosure has the following beneficial effects:
through set up the chip fixed slot that is used for placing the chip in chip testing arrangement, the mainboard standing groove that is used for placing the mainboard and with the test interface of the input/output interface connection on the mainboard, when testing the chip through this chip testing arrangement, place the chip in the chip fixed slot to place the mainboard that the chip corresponds back in the mainboard standing groove, just can test whether the chip is good through test interface. The problem of need weld chip and mainboard among the correlation technique, and need be connected with the input/output interface and the test lead wire on the mainboard, lead to the test efficiency of chip lower is solved. The effect of higher test efficiency of the chip is achieved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
FIG. 1 is a schematic diagram of an implementation environment to which various embodiments of the present disclosure are directed;
FIG. 2 is a schematic diagram illustrating the structure of a chip testing apparatus according to an exemplary embodiment;
FIG. 3-1 is a schematic diagram illustrating another chip test apparatus according to an exemplary embodiment;
FIG. 3-2 is a schematic diagram of a physical device of the chip test apparatus shown in FIG. 3-1;
FIG. 4 is a flow diagram illustrating a method of chip testing in accordance with an exemplary embodiment;
FIG. 5 is a flow chart illustrating another method of chip testing according to an example embodiment.
With the foregoing drawings in mind, certain embodiments of the disclosure have been shown and described in more detail below. These drawings and written description are not intended to limit the scope of the disclosed concepts in any way, but rather to illustrate the concepts of the disclosure to those skilled in the art by reference to specific embodiments.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of an implementation environment according to various embodiments of the present disclosure, which may include a chip 10, a motherboard 20, and a chip testing device 30.
The chip 10 may be a chip for a terminal, and the terminal may be a mobile phone, a tablet computer, an intelligent wearable device, an intelligent home device, and the like. The main board 20 may be a main board corresponding to the chip 10.
The chip 10 and the main board 20 may be connected to a chip test apparatus 30.
In addition, the implementation environment may further include an external control device 40, and the external control device 40 may be a desktop computer, a portable computer, a mobile terminal, a tablet computer, and the like. The external control device 40 may establish a wired connection or a wireless connection with the chip testing device 30 and control the chip testing device 30 to test the chip 10 through the connection with the chip testing device 30.
Fig. 2 is a schematic structural diagram of a chip testing apparatus according to an exemplary embodiment, which is exemplified by the chip testing apparatus 30 in the implementation environment shown in fig. 1. The chip testing device 30 may include a chip fixing groove 31 and a main board placing groove 32.
A chip test interface 311 is disposed in the chip fixing groove 31, and one end 311a of the chip test interface 311 can be connected to the chip 10 placed in the chip fixing groove 31.
The motherboard placement slot 32 is provided with a test interface 321 and a motherboard interface 322, one end 321a of the test interface 321 can be connected to the input/output interface 21 of the motherboard 20 placed in the motherboard placement slot 32, the other end 321b of the test interface 321 is used for data transmission with the input/output interface 21 of the motherboard, one end 322a of the motherboard interface 322 is connected to the other end 311b of the chip test interface 311, and the other end 322b of the motherboard interface 322 can be connected to the chip interface 22 of the motherboard 20.
Neither the chip 10 nor the motherboard 20 in fig. 2 may be included in the chip testing apparatus 30 provided in the embodiment of the present disclosure.
When the chip testing device provided by the embodiment of the present disclosure is used for testing a chip, the main board 20 may be placed in the main board placing groove 32 first, so that the input/output interface 21 in the main board 20 is connected to one end 321a of the testing interface 321 of the main board placing groove 32, the chip interface 22 is connected to the other end 322b of the main board interface 322 of the main board placing groove 32, and the chip 10 is placed in the chip fixing groove 31, and then the chip 10 in the chip fixing groove 31 may be tested by transmitting data for chip testing through the other end 321b of the testing interface 321 of the main board placing groove 32 and the input/output interface 21 of the main board 20, and a large number of chips of the same type may be tested by replacing the chips in the chip fixing groove 31; by replacing the chip fixing grooves 31 and the main board 20, a large number of chips of different models can be tested, and compared with the method in the related art, the chip testing efficiency is higher.
To sum up, the chip testing device provided by the embodiment of the present disclosure, through setting up the chip fixing groove for placing the chip, the motherboard placing groove for placing the motherboard, and the testing interface connected to the input/output interface on the motherboard in the chip testing device, when testing the chip through the chip testing device, places the chip in the chip fixing groove, and places the motherboard corresponding to the chip in the motherboard placing groove, then it is able to test whether the chip is good through the testing interface. The problem of need weld chip and mainboard among the correlation technique, and need be connected with the input/output interface and the test lead wire on the mainboard, lead to the test efficiency of chip lower is solved. The effect of higher test efficiency of the chip is achieved.
Fig. 3-1 is a schematic structural diagram of another chip testing apparatus according to an exemplary embodiment, which is exemplified by the chip testing apparatus as the chip testing apparatus 30 in the implementation environment shown in fig. 1. The chip testing device 30 may include a chip fixing groove 31 and a main board placing groove 32.
Optionally, the input/output interface 21 of the motherboard 20 includes an external bus interface 211, and the chip testing device 30 further includes a wireless communication module 33. The external Bus interface 211 may comprise a Universal Serial Bus (USB) interface.
The test interface 321 includes a transmission interface 3211, one end c of the transmission interface 3211 is connected to the wireless communication module 33, and the other end d of the transmission interface 3211 can be connected to the external bus interface 211 of the motherboard 20.
The wireless communication module 33 is configured to establish a wireless communication connection with the external control device 40 and transmit data between the external control device 40 and the motherboard 20, where the data may be data for performing a chip test. The WIreless communication module 33 may establish a WIreless FIdelity (WIFI) connection or a Bluetooth connection with the external control device 40.
In addition, the external control device 40 may also be directly connected to the transmission interface 3211 by a wired connection, and the embodiment of the present invention is not limited thereto.
Optionally, the input/output interface 21 of the motherboard 20 includes a functional interface 212, the chip testing apparatus 30 further includes a functional component 34, and the functional component 34 can implement various functions of a terminal corresponding to the motherboard 20. The type and the quantity of functional components can be decided by the function that the chip can realize, in other words, according to the difference of the terminal that the chip corresponds, functional component 34 also can be different, exemplarily, if the terminal that the mainboard corresponds is the cell-phone, functional component can include touch-sensitive screen, display screen, speaker, microphone and camera etc. if the terminal that the mainboard corresponds is intelligent bracelet, then functional component can include touch-sensitive screen, display screen, speaker and microphone etc..
The test interface 321 further includes a functional test interface 3212, one end e of the functional test interface 3212 is connected to the functional component 34, and the other end f of the functional test interface 3212 is capable of being connected to the functional interface 212 of the motherboard 20.
Optionally, the input/output interface 21 of the main board 20 further includes a key interface 213, the chip testing device 30 further includes a function key 35, and the testing interface 321 further includes a key testing interface 3213.
One end h of the key test interface 3213 can be connected to the key interface 213 of the main board 20, the other end i of the key test interface 3213 is connected to the function key 35, and the function key 35 is used to control the function component 34. Illustratively, the function keys 35 may include a volume control key, a main board power key, a main menu key, and the like.
Optionally, the motherboard placement slot 32 is further provided with a power supply interface 323, and the power supply interface 323 can be connected with the power supply interface 23 on the motherboard 20. The power supply interface 323 may output a corresponding voltage according to an operating voltage of a terminal corresponding to the motherboard 20. For example, when the chip to be tested is a cell phone chip, the voltage supplied by the power supply interface 323 may be 3.9 volts.
Optionally, the chip testing device 30 further includes a display 36, and the display 36 is used for displaying the current and the voltage of the power supply interface 323. The display 36 may be a digital tube display.
Alternatively, the power supply interface 323 may be connected to a power supply 50 external to the chip testing apparatus, the power supply 50 being used for supplying power to the chip testing apparatus.
Optionally, one end 322a of the motherboard interface 322 in the motherboard placement slot 32 is detachably connected to the other end 311b of the chip testing interface 311 in the chip fixing slot 31, so that the chip fixing slot 31 can be conveniently replaced to test different chips.
Alternatively, one end 311a of the chip test interface 311 may be detachably connected to the chip 10 in the chip fixing groove 31. Therefore, the chip can be conveniently and quickly detached, the damage to the chip caused by welding in the related technology can be avoided, and the detection speed of the chip can be accelerated.
Alternatively, the chip test interface 311 may be a probe interface capable of being detachably connected to the chip 10 in the chip fixing groove 31.
D, f and h in FIG. 3-1 may constitute 321a in FIG. 2, and c, e and i in FIG. 3-1 may constitute 321b in FIG. 2.
Optionally, the chip testing device 30 may further include a Subscriber Identity Module (SIM) slot (not shown in fig. 3-1), where the SIM slot is capable of connecting the SIM card with a motherboard in the motherboard placement slot, so as to test the mobile communication function of the chip.
The chip 10, the main board 20, the external control device 40, and the power supply 50 in fig. 3-1 may not be included in the chip testing device 30 provided in the embodiment of the present disclosure.
As shown in fig. 3-2, which is a schematic structural diagram of a physical device of the chip testing device shown in fig. 3-1, an external interface 38 may be disposed in the chip testing device 30, and the external interface 38 may be capable of connecting with an external bus interface of a motherboard (not shown in fig. 3-2) in the motherboard placement slot 32. The wireless communication module 33 can also be connected to an external bus interface of the motherboard in the motherboard placement slot 32 via the external interface 38.
The chip testing device may further include a user identification card slot 39. The function keys 35 may include a volume control key, a main board power key, a chip tester power key, and the like. An external power supply may be connected to the power jack 37, and the power jack 37 may establish a connection with the power supply interface 323 in the motherboard placement slot 32 and supply power to the power supply interface 323.
A cover plate 312 may be further disposed in the chip fixing groove 31, and the cover plate 312 is used to fix a chip located in the chip fixing groove 31.
The connection condition of each interface in fig. 3-2 can refer to fig. 3-1, and is not described herein again.
To sum up, the chip testing device provided by the embodiment of the present disclosure, through setting up the chip fixing groove for placing the chip, the motherboard placing groove for placing the motherboard, and the testing interface connected to the input/output interface on the motherboard in the chip testing device, when testing the chip through the chip testing device, places the chip in the chip fixing groove, and places the motherboard corresponding to the chip in the motherboard placing groove, then it is able to test whether the chip is good through the testing interface. The problem of need weld chip and mainboard among the correlation technique, and need be connected with the input/output interface and the test lead wire on the mainboard, lead to the test efficiency of chip lower is solved. The effect of higher test efficiency of the chip is achieved.
Fig. 4 is a flowchart illustrating a chip testing method for testing whether a chip is good or not by the chip testing apparatus shown in fig. 2 or the chip testing apparatus shown in fig. 3-1 according to an exemplary embodiment. The chip testing method can comprise the following steps:
And 402, fixing a target chip in the chip fixing groove, wherein the target chip is connected with one end of a chip testing interface in the chip fixing groove, and the other end of the chip testing interface is connected with one end of a mainboard interface.
And 403, testing the target chip through the other end of the test interface.
To sum up, in the chip testing method provided by the embodiment of the present disclosure, after the chip is placed in the chip fixing groove and the main board corresponding to the chip is placed in the main board placing groove, whether the chip is good or not is tested through the testing interface. The problem of need weld chip and mainboard among the correlation technique, and need be connected with the input/output interface and the test lead wire on the mainboard, lead to the test efficiency of chip lower is solved. The effect of higher test efficiency of the chip is achieved.
FIG. 5 is a flow chart illustrating another chip testing method for testing whether a chip is good by the chip testing apparatus shown in FIG. 2 or the chip testing apparatus shown in FIG. 3-1 according to an example embodiment. The chip testing method can comprise the following steps:
After the mainboard corresponding to the target chip is placed in the mainboard placing groove, one end of the test interface in the mainboard placing groove is connected with the input/output interface of the mainboard, and the chip interface of the mainboard is connected with the other end of the mainboard interface of the mainboard placing groove. Optionally, a lead may be disposed in the motherboard placement slot, and one end of the test interface may be connected to the input/output interface of the motherboard through the lead, and the chip interface of the motherboard may be connected to the other end of the motherboard interface of the motherboard placement slot through the lead.
The target chip can be a chip to be tested, and chips of different models can correspond to different mainboards. For example, the mobile phone chip may correspond to a mobile phone motherboard, and the tablet computer chip may correspond to a tablet computer motherboard.
Different chips can correspond there is different chip fixed slots, fix the chip through different chip fixed slots and can avoid the correlation technique directly to weld the chip on the mainboard when testing the chip, pull down the damage that the mainboard caused the chip with the chip again after the test is accomplished. The chip testing interface in the chip fixing groove can be a probe interface, and the chip can be conveniently connected with or disconnected from the chip testing interface through the probe interface.
Optionally, one end of the main board interface in the main board placing groove is detachably connected with the other end of the chip testing interface in the chip fixing groove, so that the chip fixing groove in the chip testing device can be conveniently replaced.
As shown in fig. 3-1, after connecting the other end 311b of the chip test interface 311 with the one end 322a of the motherboard interface 322 in the motherboard placement slot 32, the chip test interface 311 in the chip fixation slot 31 establishes a connection with the motherboard 20 in the motherboard placement slot 32.
By the end of the step, the setting of the test environment of the chip is finished, and all functions of the target chip can be tested.
And step 504, fixing the target chip in the chip fixing groove.
As shown in fig. 3-1, after the chip 10 (i.e., the destination chip) is fixed in the chip fixing slot 31, the chip 10 is connected to one end 311a of the chip test interface 311 in the chip fixing slot 31, and the other end 311b of the chip test interface 311 is connected to one end 322a of the motherboard interface 322.
In addition, as shown in fig. 3-2, a cover plate 312 may be disposed in the chip fixing groove 31, and after a target chip is inserted into the chip fixing groove 31, the target chip may be fixed in the chip fixing groove 31 by the cover plate 312.
And 505, testing the target chip through the other end of the test interface.
According to different test modes, the step can comprise the following two modes:
in the first mode, the chip is tested by functional keys.
When the chip is tested in the mode, whether the chip is good or not can be judged by pressing various function keys and according to the reaction of the function assembly. Illustratively, as shown in fig. 3-1, the function key 35 includes a volume-up key, and the function component 34 includes a speaker, the volume-up key may be pressed, and the chip 10 may be determined to be good according to whether the volume of the speaker is increased.
In addition, when the functional component includes a touch screen, various operations may be performed through the touch screen to test the chip, which is not limited in the embodiments of the present invention.
In the second mode, the chip is tested by an external control device that establishes a wireless connection with the wireless communication module.
When the chip is tested in this way, the mainboard can be controlled by the chip test program in the external control device, and the chip in the mainboard can be tested. For example, as shown in fig. 3-1, the functional component 34 may include a display screen, and the chip testing program in the external control device 40 may input a screen-up control signal to the motherboard 20 through the wireless communication module 33, so that whether the chip 10 is good or not may be determined by whether the screen is lit up or not.
In addition, the external control device can also establish wired connection with the mainboard through an external bus interface in the chip testing device, and detect the chip through the wired connection.
In the embodiment of the present disclosure, various chips can be detected in the manner from step 501 to step 505, and the applicability of the chip testing method is strong, and the chip is not damaged. When a plurality of chips of the same type as the target chip are tested, the plurality of chips can be respectively fixed in the chip fixing grooves in the steps 504 and 505, and the chips in the chip fixing grooves are detected, so that the detection process is convenient and quick, and the chips cannot be damaged.
To sum up, in the chip testing method provided by the embodiment of the present disclosure, after the chip is placed in the chip fixing groove and the main board corresponding to the chip is placed in the main board placing groove, whether the chip is good or not is tested through the testing interface. The problem of need weld chip and mainboard among the correlation technique, and need be connected with the input/output interface and the test lead wire on the mainboard, lead to the test efficiency of chip lower is solved. The effect of higher test efficiency of the chip is achieved.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules is merely a logical division, and in actual implementation, there may be other divisions, for example, multiple modules or components may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules, and may be in an electrical, mechanical or other form.
The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The above description is only exemplary of the present disclosure and is not intended to limit the present disclosure, so that any modification, equivalent replacement, or improvement made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (2)
1. A chip testing device is characterized by comprising a chip fixing groove, a wireless communication module, a subscriber identity module SIM (subscriber identity module) groove, a functional component, a functional key, a display and a mainboard placing groove, wherein different chips correspond to different chip fixing grooves or the same chip fixing groove, different chips correspond to different mainboards or the same mainboard, the functional component comprises at least one of a touch screen, a loudspeaker, a microphone and a camera, the functional key at least comprises a volume control key, a mainboard control key and a main menu key, the display is a digital display, and the display is used for displaying the current and the voltage of a power supply interface;
a chip testing interface and a cover plate are arranged in the chip fixing groove, the cover plate is used for fixing a chip in the chip fixing groove, the chip testing interface is a probe interface, and one end of the chip testing interface can be detachably connected with the chip placed in the chip fixing groove; the mainboard placing groove is internally provided with a test interface, the power supply interface, a lead and a mainboard interface, one end of the test interface is connected with the input and output interface of the mainboard placed in the mainboard placing groove by using the lead, the other end of the test interface is used for carrying out data transmission with the input and output interface of the mainboard, the power supply interface can be connected with the power supply interface on the mainboard, the power supply interface provides corresponding voltage and current for different mainboards, one end of the mainboard interface is detachably connected with the other end of the chip test interface, the other end of the mainboard interface is connected with the chip interface of the mainboard by using the lead, the test interface comprises a transmission interface, one end of the transmission interface is connected with the wireless communication module, wherein the wireless communication module is used for establishing wireless fidelity WIFI connection or Bluetooth connection with an external control device, the SIM slot of the user identity recognition card can connect the user identity recognition card with the mainboard in the mainboard placing slot, and the SIM slot of the user identity recognition card is used for testing the mobile communication function of the chip;
the input and output interface of the mainboard comprises an external bus interface, the other end of the transmission interface can be connected with the external bus interface of the mainboard, the wireless communication module is connected with the external bus interface, the input and output interface of the mainboard comprises a functional interface and a key interface, the functional components can realize various functions of the terminal corresponding to the mainboard, different functional components are arranged on chips corresponding to different terminals, and the chips correspond to one or more functional components; the test interface also comprises a function test interface, one end of the function test interface is connected with the function component, and the other end of the function test interface can be connected with the function interface of the mainboard;
the test interface also comprises a key test interface; one end of the key test interface can be connected with the key interface of the mainboard, the other end of the key test interface is connected with the function key, and the function key is used for controlling the function component.
2. A chip testing method, wherein the method is used to test a target chip by the chip testing device of claim 1, the chip testing device comprises a chip fixing slot, a wireless communication module, a SIM slot, a functional assembly, a functional key, a display and a motherboard placement slot, different chips correspond to different chip fixing slots or the same chip fixing slot, different chips correspond to different motherboards or the same motherboard, the functional assembly comprises at least one of a touch screen, a speaker, a microphone and a camera, the functional key comprises at least a volume control key, a motherboard control key and a main menu key, the display is a digital tube display, the display is used to display the current and voltage of a power supply interface, the power supply interface is disposed in the motherboard placement slot, the power supply interface is connected with a power supply interface on the motherboard, the power supply interface provides corresponding voltage and current for different main boards, and the method comprises the following steps:
placing the main board corresponding to the target chip in the main board placing groove, connecting one end of a test interface in the main board placing groove with an input/output interface of the main board by using a lead wire arranged in the main board placing groove, connecting a chip interface of the main board with the other end of the main board interface of the main board placing groove by using the lead wire, the test interface comprises a transmission interface, one end of the transmission interface is connected with the wireless communication module, wherein the wireless communication module is used for establishing wireless fidelity (WIFI) connection or Bluetooth connection with an external control device, and transmits data between the external control device and the main board, the SIM slot can connect the SIM card with the main board in the main board placing slot, the SIM slot of the user identity identification card is used for testing the mobile communication function of the target chip;
the input and output interface of the mainboard comprises an external bus interface, the other end of the transmission interface can be connected with the external bus interface of the mainboard, the wireless communication module is connected with the external bus interface, the input and output interface of the mainboard comprises a functional interface and a key interface, the functional components can realize various functions of the terminal corresponding to the mainboard, different functional components are arranged on chips corresponding to different terminals, and the target chip corresponds to one or more functional components; the test interface also comprises a function test interface, one end of the function test interface is connected with the function component, and the other end of the function test interface can be connected with the function interface of the mainboard;
the test interface also comprises a key test interface; one end of the key test interface can be connected with the key interface of the mainboard, the other end of the key test interface is connected with the function key, and the function key is used for controlling the function component;
fixing the target chip in the chip fixing groove through a cover plate in the chip fixing groove, wherein the target chip is detachably connected with one end of a chip testing interface in the chip fixing groove, the other end of the chip testing interface is detachably connected with one end of the mainboard interface, and the chip testing interface is a probe interface;
and testing the target chip through the other end of the test interface.
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| CN201710722024.1A CN107544019B (en) | 2017-08-22 | 2017-08-22 | Chip testing device and chip testing method |
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| CN201710722024.1A CN107544019B (en) | 2017-08-22 | 2017-08-22 | Chip testing device and chip testing method |
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| CN107544019B true CN107544019B (en) | 2021-08-10 |
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| CN110824330A (en) * | 2018-08-08 | 2020-02-21 | 致茂电子(苏州)有限公司 | Semiconductor integrated circuit test system and semiconductor integrated circuit test device thereof |
| CN111913471A (en) * | 2020-07-21 | 2020-11-10 | 北京京瀚禹电子工程技术有限公司 | Testing device |
| TWI799025B (en) * | 2021-12-22 | 2023-04-11 | 技嘉科技股份有限公司 | Processing system, device and method for automatic testing interface card |
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| CN201773169U (en) * | 2010-06-23 | 2011-03-23 | 天津渤海易安泰电子半导体测试有限公司 | Testing system for integrated circuit chip |
| CN202994975U (en) * | 2012-12-17 | 2013-06-12 | 山东华芯半导体有限公司 | QFP128 packaged chip test board |
| CN205539072U (en) * | 2016-04-06 | 2016-08-31 | 深圳市芯天下技术有限公司 | High performance chip test fixture |
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