CN107508460B - A kind of boost capacitor charging circuit with under-voltage protection - Google Patents
A kind of boost capacitor charging circuit with under-voltage protection Download PDFInfo
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- CN107508460B CN107508460B CN201710783955.2A CN201710783955A CN107508460B CN 107508460 B CN107508460 B CN 107508460B CN 201710783955 A CN201710783955 A CN 201710783955A CN 107508460 B CN107508460 B CN 107508460B
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- tube
- boost capacitor
- pmos tube
- boot
- nmos tube
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- 239000003990 capacitor Substances 0.000 title claims abstract description 61
- 238000001514 detection method Methods 0.000 claims abstract description 14
- 238000005516 engineering process Methods 0.000 abstract description 2
- 230000005611 electricity Effects 0.000 description 6
- 101150110971 CIN7 gene Proteins 0.000 description 4
- 101100286980 Daucus carota INV2 gene Proteins 0.000 description 4
- 101150110298 INV1 gene Proteins 0.000 description 4
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 4
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 description 4
- 230000006837 decompression Effects 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/34—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering
- H02J7/345—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering using capacitors as storage or buffering devices
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
A kind of boost capacitor charging circuit with under-voltage protection, belongs to electronic circuit technology field.Detection charge loop is for detecting boost capacitor CbootBoth ends pressure difference simultaneously gives boost capacitor CbootCharging, it eliminates traditional mode and needs the problem of designing loop compensation to boost capacitor charging using low pressure difference linear voltage regulator LDO, do not need plug-in bulky capacitor, save chip cost and area, it also avoids for a long time after light-load mode, boost capacitor C when exitingbootThe inadequate problem of upper voltage；Current comparator gives boost capacitor C using low pressure difference linear voltage regulator LDO for realizing under-voltage protection function, compared to traditionbootThe mode of charging, charging modes of the invention are simpler, enormously simplify the design difficulty of circuit.
Description
Technical field
The invention belongs to electronic circuit technology fields, and in particular to a kind of band under-voltage protection for not needing plug-in bulky capacitor
The boost capacitor charging circuit of function is the Buck converter of NMOS tube suitable for power tube.
Background technique
As soon as Buck converter seems outstanding as seed type most-often used in DC-DC converter, the driving of power tube
It is important.As shown in Figure 1, using the Buck converter of NMOS for power tube, including power tube MN, drive module, boosting electricity
Hold Cboot, diode D, inductance, capacitor Co and resistance RL, power tube MN driving when require safe opening, it is necessary to by power tube
A gate source voltage V is lifted on the basis of voltage of the MN grid driving voltage at switching node SWGS, the realization of this lifting voltage
Usually provided by boosting (boot) capacitor.When power tube MN shutdown, switching node SW ground connection, low pressure difference linearity pressure stabilizing
Device LDO gives boost capacitor CbootCharging guarantees boost capacitor CbootOn the enough power tube MN of pressure difference can fully open next time；
When power tube MN is opened, switching node SW meets output, (i.e. boost voltage C at node BSTbootTop crown) voltage is elevated
It arrives: VBST=VSW+Vboot, Schottky diode turns off at this time, and low pressure difference linear voltage regulator LDO no longer gives boost capacitor CbootIt fills
Electricity.
But boost capacitor C is given for traditional this use low pressure difference linear voltage regulator LDObootThe mode of charging, is deposited
In following drawback:
1, the design of low pressure difference linear voltage regulator LDO is complicated, due to boost capacitor CbootThe conduct in power tube MN shutdown
The output capacitance of low pressure difference linear voltage regulator LDO and disconnected with the output of low pressure difference linear voltage regulator LDO when opening, make low voltage difference
The pole variation of linear voltage regulator LDO output very greatly, needs plug-in bulky capacitor Ce to guarantee loop stability, increase chip at
This.
2, when Buck circuit enters light-load mode, power tube MN is turned off and the turn-off time is very long, at this time at switching node SW
Voltage be Vout, boost capacitor CbootUpper voltage may drop to VLDO-VD-Vout(VDFor the pressure drop of diode D), if
Vout voltage is excessively high, can be due to boost capacitor C when system, which exits underloading, needs to be again turned on power tube MNbootUpper pressure difference is not
Enough cause power tube MN that can not fully open, loses the efficiency of system (when i.e. output voltage is very high, because exiting underloading
When boost capacitor on pressure drop it is inadequate, will lead to power tube MN can not fully open at this time).Boost capacitor C in order to preventbootOn
Since electric leakage causes pressure difference is too small power tube MN can not be made to fully open, need to design under-voltage protecting circuit and logic, and it is traditional
The logical design using low pressure difference linear voltage regulator LDO charge mode can be more complicated.
3, under frequency applications, as shown in Figure 1, Schottky diode D1 both ends pressure drop VD1By low pressure difference linear voltage regulator LDO
Output voltage (generally 5V) limitation, both ends electric currentIt can be restricted, so that boost capacitor CbootBoth ends pressure drop
Ideal value can not be charged to, can not be fully on so as to cause upper tube and reduce efficiency.
Summary of the invention
In view of the above shortcomings, the present invention proposes a kind of boost capacitor charging circuit with under-voltage protection, is suitable for function
Rate pipe is the decompression Buck comparator of NMOS tube.
The technical solution of the present invention is as follows:
A kind of boost capacitor charging circuit with under-voltage protection, including current comparator and detection charge loop,
The detection charge loop includes operational amplifier, power diode D2, first resistor R1, second resistance R2,
Three resistance R3, the first NMOS tube MN1, the first PMOS tube MP1 and the 4th PMOS tube MP4,
The inverting input terminal of operational amplifier connects the first reference voltage Vref, and output end connects the 4th PMOS tube MP4
Grid, the source electrode of the 4th PMOS tube MP4 connects input voltage vin；
The anode of power diode D2 connects the drain electrode of the 4th PMOS tube MP4, and cathode connects the boost capacitor Cboot
Top crown and the source electrode by connecting the first PMOS tube MP1 after first resistor R1；
The grid of first PMOS tube MP1 connects the boost capacitor CbootBottom crown, drain electrode connection 3rd resistor R3
One end and the first NMOS tube MN1 drain electrode；
One end of second resistance R2 connects the source electrode and operation amplifier of the other end of 3rd resistor R3, the first NMOS tube MN1
The non-inverting input terminal of device, other end ground connection；
The current comparator includes the second NMOS tube MN2, third NMOS tube MN3, the second PMOS tube MP2, the 3rd PMOS
Pipe MP3, the first phase inverter INV1, the second phase inverter INV2, the 4th resistance Rf and first capacitor Cf,
One end of 4th resistance Rf connects the drain electrode of the first NMOS tube MN1 in the detection charge loop, other end connection
The grid of third NMOS tube MN3 and by being grounded after first capacitor Cf；
The grid leak of second PMOS tube MP2 is shorted and connects the leakage of the grid and the second NMOS tube MN2 of third PMOS tube MP3
Pole, source electrode connect the source electrode of third PMOS tube MP3；
The grid of second NMOS tube MN2 connects the second reference voltage Vref1, source electrode ground connection；
The drain electrode of the drain electrode connection third PMOS tube MP3 of third NMOS tube MN3 simultaneously passes through the first phase inverter INV1 and second
The grid of the first NMOS tube MN1 in the detection charge loop, source electrode ground connection are connected after the cascaded structure of phase inverter INV2.
The invention has the benefit that passing through detection boost capacitor CbootPressure difference to give boost capacitor CbootCharging, removes from
Traditional mode needs the problem of designing loop compensation to boost capacitor charging using low pressure difference linear voltage regulator LDO, does not need
Plug-in bulky capacitor saves chip cost and area, also avoids for a long time after light-load mode, boost capacitor when exiting
CbootThe inadequate problem of upper voltage；There is under-voltage monitoring function simultaneously, given and risen using low pressure difference linear voltage regulator LDO compared to tradition
Voltage capacitance CbootThe mode of charging, charging modes of the invention are simpler, enormously simplify the design difficulty of circuit.
Detailed description of the invention
Fig. 1 gives boost capacitor C using low pressure difference linear voltage regulator LDO for traditionalbootThe topological diagram of charging.
Fig. 2 is the physical circuit figure of the boost capacitor charging circuit provided by the invention with under-voltage protection.
Specific embodiment
The present invention is described in detail with reference to the accompanying drawing.
Circuit of the invention is as shown in Fig. 2, charging circuit provided by the invention, for being the decompression of NMOS tube to power tube
Boost capacitor C in Buck converterbootCharging, detection charge loop is for detecting boost capacitor CbootBoth ends pressure difference simultaneously gives liter
Voltage capacitance CbootCharging, including operational amplifier, power diode D2, first resistor R1, second resistance R2,3rd resistor R3,
The inverting input terminal of first NMOS tube MN1, the first PMOS tube MP1 and the 4th PMOS tube MP4, operational amplifier connect the first benchmark
Voltage Vref, output end connect the grid of the 4th PMOS tube MP4, and the source electrode of the 4th PMOS tube MP4 connects the defeated of Buck converter
Enter voltage Vin；The anode of power diode D2 connects the drain electrode of the 4th PMOS tube MP4, and cathode connects boost capacitor Cboot's
Top crown and the source electrode by connecting the first PMOS tube MP1 after first resistor R1；The grid connection boosting electricity of first PMOS tube MP1
Hold CbootBottom crown, drain electrode connection 3rd resistor R3 one end and the first NMOS tube MN1 drain electrode；The one of second resistance R2
The other end, the source electrode of the first NMOS tube MN1 and the non-inverting input terminal of operational amplifier of end connection 3rd resistor R3, the other end
Ground connection.
Current comparator is for realizing under-voltage protection function, including the second NMOS tube MN2, third NMOS tube MN3, second
PMOS tube MP2, third PMOS tube MP3, the first phase inverter INV1, the second phase inverter INV2, the 4th resistance Rf and first capacitor Cf,
The drain electrode of first NMOS tube MN1 in one end connecting detection charge loop of 4th resistance Rf, the other end connect third NMOS tube MN3
Grid and by being grounded after first capacitor Cf；The grid leak of second PMOS tube MP2 is shorted and connects the grid of third PMOS tube MP3
With the drain electrode of the second NMOS tube MN2, source electrode connects the source electrode of third PMOS tube MP3；The grid connection the of second NMOS tube MN2
Two reference voltage Vref1, source electrode ground connection；The drain electrode of the drain electrode connection third PMOS tube MP3 of third NMOS tube MN3 simultaneously passes through the
After the cascaded structure of one phase inverter INV1 and the second phase inverter INV2 in connecting detection charge loop the first NMOS tube MN1 grid
Pole, source electrode ground connection.
As shown in Fig. 2, working as boost capacitor CbootWhen upper pressure difference is enough, the voltage VFB of the non-inverting input terminal of operational amplifier
First reference voltage Vref, the A point i.e. drain terminal voltage VA of the first NMOS tube MN1 is clamped to higher than the second reference voltage by negative-feedback
The grid voltage VB of i.e. the first NMOS tube MN1 of Vref1, B point is pulled low, and VB exports low level, the first NMOS tube MN1 shutdown.This
When, flow through the electric current I of the first PMOS tube MP11Are as follows:
Wherein upFor the mobility in hole, Cox is PMOS tube gate capacitance per unit area, and Vthp is the threshold value electricity of PMOS tube
Pressure,For the breadth length ratio of the first PMOS tube MP1.By being derived above it is found that boost capacitor CbootBoth ends pressure difference Vboot can lead to
The first reference voltage Vref of setting, first resistor R1 and second resistance R2 are crossed to be arranged, but is in the first reference voltage Vref
Non-linear relation.If necessary to approximate existing relationship, the Vboot voltage that can according to need increases first resistor R1, second
Resistance R2 and the first PMOS tube MP1 breadth length ratioMake the first PMOS tube MP1 work in subthreshold region, there is following relationship at this time:
At this point, boost capacitor CbootBoth ends pressure difference Vboot and the first reference voltage Vref is approximately linear relationship.
As shown in Fig. 2, power tube MN is closed for a long time at this time, if gone out at this time when system is in light-load mode for a long time
Existing boost capacitor CbootThe too small situation of upper pressure difference needs to start under-voltage protection at this moment in order to guarantee that the efficiency of system is not lost
Function allows system in this case without opening the movement of power tube MN.A point voltage VA is by the electricity of the 4th resistance Rf and first
Hold the grid end that the filter network that Cf is constituted is coupled to third NMOS tube MN3, as boost capacitor CbootUpper voltage is reduced to under-voltage guarantor
When shield value, for A point voltage VA less than the second reference voltage Vref1, the electric current for flowing through third NMOS tube MN3, which is less than, flows through the 3rd PMOS
The electric current of pipe MP3, B point voltage VB turns over height, and after two-stage phase inverter, B point voltage VB is also that high level makes the first NMOS tube
MN1 is opened, and A point voltage VA continues to reduce, and accelerates the overturning of B point, plays a hysteresis effect.
When triggering under-voltage protection function:
Vref1=VA=I1(R2+R3) (5)
So boost capacitor C at this timebootUpper pressure difference are as follows:
As boost capacitor CbootIt powers on after pressure begins to ramp up, needs to exit under-voltage protection at this time:
Amount of hysteresis are as follows:
As known from the above, required minimum Vboot voltage can be fully opened according to power tube MN to select relevant ginseng
Number and setting amount of hysteresis.
The present invention devises a detection boost capacitor CbootPressure difference gives boost capacitor CbootCharging, while having under-voltage
The circuit of monitoring function.Power diode D2 both ends pressure drop in the present invention does not have the both ends Schottky diode D1 in traditional form
Limited by low pressure difference linear voltage regulator LDO output voltage, thus its electric current can achieve it is very big, can also be in frequency applications
By boost capacitor CbootOn voltage be charged to ideal value.
Advantages of the present invention, which first consists in, to be eliminated traditional mode and is filled using low pressure difference linear voltage regulator LDO to boost capacitor
Electricity needs the problem of designing loop compensation, while also there is no need to plug-in bulky capacitors, save chip cost and area, next is avoided
For a long time after light-load mode, the inadequate problem of voltage in boost capacitor when exiting.Under-voltage protecting circuit is set simultaneously
Meter and logic are also simpler to boost capacitor charging modes using low pressure difference linear voltage regulator LDO than tradition, enormously simplify circuit
Design difficulty.
Those of ordinary skill in the art will understand that the embodiments described herein, which is to help reader, understands this hair
Bright principle, it should be understood that protection scope of the present invention is not limited to such specific embodiments and embodiments.This field
Those of ordinary skill disclosed the technical disclosures can make according to the present invention and various not depart from the other each of essence of the invention
The specific variations and combinations of kind, these variations and combinations are still within the scope of the present invention.
Claims (1)
1. a kind of boost capacitor charging circuit with under-voltage protection, which is characterized in that including current comparator and detection charging ring
Road,
The detection charge loop include operational amplifier, power diode (D2), first resistor (R1), second resistance (R2),
3rd resistor (R3), the first NMOS tube (MN1), the first PMOS tube (MP1) and the 4th PMOS tube (MP4),
The inverting input terminal of operational amplifier connects the first reference voltage (Vref), and output end connects the 4th PMOS tube (MP4)
Grid, the source electrode of the 4th PMOS tube (MP4) meets input voltage (Vin)；
The anode of power diode (D2) connects the drain electrode of the 4th PMOS tube (MP4), and cathode connects the boost capacitor (Cboot)
Top crown and the source electrode of the first PMOS tube (MP1) is connected by first resistor (R1) afterwards；
The grid of first PMOS tube (MP1) connects the boost capacitor (Cboot) bottom crown, drain electrode connection 3rd resistor (R3)
One end and the first NMOS tube (MN1) drain electrode；
The other end of one end connection 3rd resistor (R3), the source electrode of the first NMOS tube (MN1) and the operation of second resistance (R2) are put
The non-inverting input terminal of big device, other end ground connection；
The current comparator includes the second NMOS tube (MN2), third NMOS tube (MN3), the second PMOS tube (MP2), third
PMOS tube (MP3), the first phase inverter (INV1), the second phase inverter (INV2), the 4th resistance (Rf) and first capacitor (Cf),
The drain electrode of first NMOS tube (MN1), other end connection in one end connection detection charge loop of 4th resistance (Rf)
The grid of third NMOS tube (MN3) is simultaneously grounded by first capacitor (Cf) afterwards；
The grid leak of second PMOS tube (MP2) is shorted and connects the grid of third PMOS tube (MP3) and the leakage of the second NMOS tube (MN2)
Pole, source electrode connect the source electrode of third PMOS tube (MP3)；
The grid of second NMOS tube (MN2) connects the second reference voltage (Vref1), source electrode ground connection；
The drain electrode of drain electrode connection third PMOS tube (MP3) of third NMOS tube (MN3) simultaneously passes through the first phase inverter (INV1) and the
The grid of the first NMOS tube (MN1) in the detection charge loop, source electrode are connected after the cascaded structure of two phase inverters (INV2)
Ground connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710783955.2A CN107508460B (en) | 2017-09-04 | 2017-09-04 | A kind of boost capacitor charging circuit with under-voltage protection |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710783955.2A CN107508460B (en) | 2017-09-04 | 2017-09-04 | A kind of boost capacitor charging circuit with under-voltage protection |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107508460A CN107508460A (en) | 2017-12-22 |
| CN107508460B true CN107508460B (en) | 2019-06-04 |
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| CN201710783955.2A Expired - Fee Related CN107508460B (en) | 2017-09-04 | 2017-09-04 | A kind of boost capacitor charging circuit with under-voltage protection |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113849029B (en) * | 2021-09-26 | 2022-08-26 | 电子科技大学 | Under-voltage detection circuit of self-biased reference source |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105450019A (en) * | 2016-01-20 | 2016-03-30 | 电子科技大学 | A drive circuit used for a DC-DC converter |
| CN105915042A (en) * | 2016-05-27 | 2016-08-31 | 电子科技大学 | Soft start and soft shutoff circuit for Buck converters |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104218803B (en) * | 2014-08-27 | 2017-04-12 | 成都芯源***有限公司 | Bootstrap voltage charging circuit and voltage conversion circuit |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105450019A (en) * | 2016-01-20 | 2016-03-30 | 电子科技大学 | A drive circuit used for a DC-DC converter |
| CN105915042A (en) * | 2016-05-27 | 2016-08-31 | 电子科技大学 | Soft start and soft shutoff circuit for Buck converters |
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| CN107508460A (en) | 2017-12-22 |
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Granted publication date: 20190604 |