CN107490913B

CN107490913B - Array substrate, display panel and display device

Info

Publication number: CN107490913B
Application number: CN201710804398.8A
Authority: CN
Inventors: 王超
Original assignee: Tianma Microelectronics Co Ltd; Shanghai Tianma Microelectronics Co Ltd
Current assignee: Tianma Microelectronics Co Ltd; Shanghai Tianma Microelectronics Co Ltd
Priority date: 2015-04-01
Filing date: 2015-04-01
Publication date: 2020-11-13
Anticipated expiration: 2035-04-01
Also published as: CN107340623A; CN107490913A; CN107340623B; CN104865756B; CN104865756A

Abstract

The invention discloses an array substrate, a display panel and a display device, comprising a display area and a non-display area surrounding the display area, wherein the non-display area comprises a plurality of first electrode leads and a plurality of second electrode leads, and the non-display area of the array substrate comprises: a substrate; the first conducting layer is arranged on the surface of the substrate; the gate dielectric layer is arranged on one side, away from the substrate, of the first conducting layer; the second conducting layer is arranged on one side, away from the substrate, of the gate dielectric layer; the isolation layer is arranged on one side, away from the substrate, of the second conducting layer, the thickness of the isolation layer is larger than that of the gate dielectric layer, and/or the dielectric constant of the isolation layer is smaller than that of the gate dielectric layer; the third conducting layer is arranged on one side, away from the substrate, of the isolating layer; the first electrode lead is arranged on the first conducting layer or the second conducting layer, the second electrode lead is arranged on the third conducting layer, and the wiring layout of the array substrate is greatly saved through reasonable wiring.

Description

Array substrate, display panel and display device

The application has an application date of 2015, 4 months and 1 days, an application number of 201510152790, and the invention names: divisional applications of an array substrate, a display panel and a display device are provided.

Technical Field

The invention relates to the field of touch display technology, in particular to an array substrate, a display panel comprising the array substrate and a display device comprising the array substrate.

Background

With the development of display technology, liquid crystal display panels are continuously improved, so that the liquid crystal display panels have the advantages of thin bodies, power saving, no radiation and the like, and the liquid crystal display panels are more and more widely applied. The array substrate is one of important components in a liquid crystal display panel, has the characteristics of high integration level, complex routing and the like, and various devices need to be integrated in a limited wiring layout, so that the array substrate capable of saving the wiring layout is one of main research projects of researchers at present.

Disclosure of Invention

In view of this, embodiments of the present invention provide an array substrate, a display panel, and a display device, in which two electrode leads, to which signals are applied and which are overlapped, are disposed on different conductive layers, so that a wiring layout of the array substrate is saved, and a utilization rate of the array substrate is improved.

In order to achieve the above purpose, the technical solutions provided by the embodiments of the present invention are as follows:

an array substrate comprises a display area and a non-display area surrounding the display area, wherein the non-display area comprises a plurality of first electrode leads and a plurality of second electrode leads, and the non-display area of the array substrate comprises:

a substrate;

the first conducting layer is arranged on the surface of the substrate;

the gate dielectric layer is arranged on one side, away from the substrate, of the first conducting layer;

the second conducting layer is arranged on one side, away from the substrate, of the gate dielectric layer;

the isolation layer is arranged on one side, away from the substrate, of the second conducting layer, the thickness of the isolation layer is larger than that of the gate dielectric layer, and/or the dielectric constant of the isolation layer is smaller than that of the gate dielectric layer;

the third conducting layer is arranged on one side, away from the substrate, of the isolation layer;

wherein the first electrode lead is disposed on the first conductive layer or the second conductive layer, and the second electrode lead is disposed on the third conductive layer.

In addition, the embodiment of the invention also provides a display panel which comprises the array substrate.

Finally, the embodiment of the invention also provides a display device which comprises the display panel.

Compared with the prior art, the technical scheme provided by the embodiment of the invention has at least the following advantages:

the embodiment of the invention provides an array substrate, a display panel and a display device, which comprise a display area and a non-display area surrounding the display area, wherein the non-display area comprises a plurality of first electrode leads and a plurality of second electrode leads, and the non-display area of the array substrate comprises: a substrate; the first conducting layer is arranged on the surface of the substrate; the gate dielectric layer is arranged on one side, away from the substrate, of the first conducting layer; the second conducting layer is arranged on one side, away from the substrate, of the gate dielectric layer; the isolation layer is arranged on one side, away from the substrate, of the second conducting layer, the thickness of the isolation layer is larger than that of the gate dielectric layer, and/or the dielectric constant of the isolation layer is smaller than that of the gate dielectric layer; the third conducting layer is arranged on one side, away from the substrate, of the isolation layer; wherein the first electrode lead is disposed on the first conductive layer or the second conductive layer, and the second electrode lead is disposed on the third conductive layer.

As can be seen from the above, in the technical scheme provided by the embodiment of the present invention, since the thickness of the isolation layer is greater than that of the gate dielectric layer, and/or the dielectric constant of the isolation layer is less than that of the gate dielectric layer, when signals are simultaneously applied to the first electrode lead and the second electrode lead, the interference phenomenon between the first electrode lead and the second electrode lead located on different conductive layers is improved, and then through reasonable wiring, the wiring layout of the array substrate can be greatly saved, thereby improving the utilization rate of the array substrate.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a conventional array substrate;

fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;

FIG. 3a is a cut-away view taken along aa' of FIG. 2;

FIG. 3b is another cut-away view taken along aa' of FIG. 2;

fig. 4a is a wiring diagram of a first electrode lead and a second electrode lead provided in an embodiment of the present application;

fig. 4b is a wiring diagram of a first electrode lead and a second electrode lead according to another embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;

fig. 11 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;

fig. 12 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;

fig. 13 is a schematic view of a touch structure of an array substrate according to an embodiment of the present disclosure;

FIG. 14a is a cut away view along bb' of FIG. 13;

fig. 14b is another cut view along the direction bb' in fig. 13.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As described in the background art, the array substrate has the characteristics of high integration level, complex routing and the like, and various devices need to be integrated in a limited wiring layout, so that an array substrate which saves the wiring layout is one of the main research projects of researchers at present.

Specifically, referring to fig. 1, a schematic structural diagram of a conventional array substrate is shown, where the array substrate includes a display area 101 and a non-display area 102 surrounding the display area, and the display area 101 includes a plurality of gate lines 101a and a plurality of data lines 101 b; the non-display region 102 includes a gate driving circuit region 102a and a step region 102 b; the gate line 101a is led out through a gate line lead 101a ' located in the gate driving circuit region 102a, and the data line 101b is led out through a data line lead 101b ' located in the step region 102b, and since signals need to be applied to the adjacent data line leads 101b ' at the same time, in order to avoid mutual interference of the signals between the adjacent data line leads 101b ', the distance between the adjacent data line leads 101b ' is increased, and further, the wiring layout of the array substrate is increased.

Based on this, the embodiment of the application provides an array substrate, through will be exerted two electrode lead that signal period has the overlap and set up in different conducting layers to through reasonable wiring, with the wiring domain of saving array substrate, improve array substrate's utilization ratio. Specifically, referring to fig. 2 to 14b, the array substrate provided in the embodiments of the present application will be described in detail.

Referring to fig. 2, fig. 3a and fig. 3b, fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure, fig. 3a is a sectional view along aa 'of fig. 2, and fig. 3b is another sectional view along aa' of fig. 2, wherein the array substrate includes:

a display area 10;

and a non-display region 20 surrounding the display region 10, the non-display region 20 including a plurality of first electrode leads 20a and a plurality of second electrode leads 20b, and a period of time during which the first electrode leads 20a and the second electrode leads 20b are applied with signals is overlapped, the non-display region of the array substrate including:

a substrate 100;

a first conductive layer 200 disposed on the surface of the substrate 100;

the gate dielectric layer 300 is arranged on one side, away from the substrate 100, of the first conducting layer 200;

the second conductive layer 400 is arranged on one side of the gate dielectric layer 300, which is far away from the substrate 100;

the isolation layer 500 is arranged on one side, away from the substrate 100, of the second conductive layer 400, and the thickness of the isolation layer is larger than that of the gate dielectric layer, and/or the dielectric constant of the isolation layer is smaller than that of the gate dielectric layer;

the third conductive layer 600 is disposed on a side of the isolation layer 500 away from the substrate 100;

the first electrode lead 20a is disposed on the first conductive layer 200 or the second conductive layer 400, and the second electrode lead 20b is disposed on the third conductive layer 600.

That is, referring to fig. 3a, the first electrode lead 20a is disposed on the first conductive layer 200, and the second electrode lead 20b is disposed on the third conductive layer 600;

and, referring to fig. 3b, the first electrode lead 20a is disposed on the second conductive layer 400, and the second electrode lead 20b is disposed on the third conductive layer 600.

It should be noted that, the thickness of the isolation layer is greater than the thickness of the gate dielectric layer, and/or the dielectric constant of the isolation layer is less than the dielectric constant of the gate dielectric layer includes three conditions, that is, the first condition is that the thickness of the isolation layer is greater than the thickness of the gate dielectric layer, and the dielectric constant of the isolation layer is less than the dielectric constant of the gate dielectric layer; the second is that when the thickness of the gate dielectric layer is the same as that of the isolation layer, the dielectric constant of the isolation layer is smaller than that of the gate dielectric layer; and the third is that when the dielectric constant of the isolation layer is the same as that of the gate dielectric layer, the thickness of the isolation layer is larger than that of the gate dielectric layer. The thickness of the isolation layer is preferably not less than 1.8 micrometers in the embodiments of the present application.

The first electrode lead and the second electrode lead provided by the embodiments of the present application may be arbitrarily disposed, and most preferably, the first electrode lead and the second electrode lead have an overlapping region therebetween along a light transmission direction of the array substrate. Specifically, referring to fig. 4a, a wiring pattern of a first electrode lead and a second electrode lead is provided for an embodiment of the present application, wherein an overlapping region is formed between the first electrode lead 20a and the second electrode lead 20b, and the extending directions of the first electrode lead 20a and the second electrode lead 20b are the same. That is, along the extending direction of any one of the electrode leads, one electrode lead can cover a part of the other electrode lead; or, along the extending direction of any one electrode lead, one electrode lead can completely cover the other electrode lead;

in addition, referring to fig. 4b, another wiring diagram of the first electrode lead and the second electrode lead is provided for the embodiment of the present application, wherein an overlapping region is formed between the first electrode lead 20a and the second electrode lead 20b, and an included angle is formed between the extending directions of the first electrode lead 20a and the second electrode lead 20b, wherein the included angle may be any number of degrees, such as 45 degrees, 60 degrees, and the like, which is not limited thereto.

It should be noted that, in the embodiment of the present application, the wiring structure between the first electrode lead and the second electrode lead is not specifically limited, and the wiring structure needs to be designed according to actual applications, so as to reduce the wiring layout of the array substrate through reasonable wiring. In addition, in order to keep the consistency of the signals transmitted by the first electrode lead and the second electrode lead, the resistances of the first electrode lead and the second electrode lead provided by the embodiment of the application are the same.

Further, referring to fig. 5, a schematic structural diagram of another array substrate provided in the present embodiment is shown, wherein the non-display area 20 includes a gate driving circuit area 21 and a step area 22, wherein,

the gate driving circuit region 21 includes a plurality of gate line leads 21a, each gate line 21a lead being connected to a gate line 10a of the array substrate;

the step area 22 includes a plurality of data line leads 22a, and each data line lead 22a is connected to a data line 10b of the array substrate;

the first electrode lead 20a and the second electrode lead 20b are both gate line leads or data line leads.

For the array substrate provided in the embodiment of the present application, the type of the array substrate is not particularly limited in the present application, wherein the transistor of the array substrate may be a bottom gate transistor or a top gate transistor, specifically, the array substrate provided in the embodiment of the present application is described in detail with reference to fig. 6 and 7, and it should be noted that fig. 6 and 7 both use the array substrate provided in fig. 3a or fig. 3b as an example.

As shown in fig. 6, the transistor of the array substrate may be a bottom-gate transistor, and is a schematic structural diagram of another array substrate provided in the embodiment of the present application, where the first conductive layer 200 of the array substrate includes a gate G, the second conductive layer 400 includes a source and a drain (including a source S and a drain D), and the array substrate includes:

and a semiconductor layer 700 disposed between the gate dielectric layer 300 and the second conductive layer 400, the semiconductor layer 700 including an active region a, wherein the gate electrode G, the source and drain electrodes (source S and drain D), and the active region a form a thin film transistor.

Alternatively, the transistor of the array substrate may be a top-gate transistor, and as shown in fig. 7, the structural schematic diagram of another array substrate provided in the embodiment of the present application is shown, where the first conductive layer 200 of the array substrate includes a gate G, the second conductive layer 400 includes a source and a drain (including a source S and a drain D), and the array substrate includes:

a semiconductor layer 700 disposed between the substrate 100 and the first conductive layer 200, the semiconductor layer 700 including an active region a; and a gate insulating layer 301 disposed between the semiconductor layer 700 and the first conductive layer 200, wherein the gate electrode G, the source and drain electrodes (including the source electrode S and the drain electrode D), and the active region a form a thin film transistor.

In addition, the present application also does not specifically limit the positions of the common electrode and the pixel electrode of the array substrate, and the array substrate provided in the embodiments of the present application is specifically described with reference to fig. 8 to 12.

Fig. 8 is a schematic structural diagram of another array substrate according to an embodiment of the present application, wherein,

the array substrate includes: the substrate 100, the first conductive layer 200, the gate dielectric layer 300 and the second conductive layer 400;

the first insulating layer 801 is arranged on one side, away from the substrate 100, of the second conductive layer 400;

a first electrode 802 disposed on a side of the first insulating layer 801 facing away from the substrate 100;

a second insulating layer 803 disposed on a side of the first electrode 802 away from the substrate 100;

a second electrode 804 disposed on a side of the second insulating layer 803 facing away from the substrate 100;

a third insulating layer 805 disposed on a side of the second electrode 804 facing away from the substrate 100;

the third conductive layer 600 is disposed on a side of the third insulating layer 805 away from the substrate 100;

the isolation layer comprises a first insulation layer, a second insulation layer and a third insulation layer.

Alternatively, referring to fig. 9, a schematic structural diagram of another array substrate provided in the embodiment of the present application is shown, where the array substrate includes: the substrate 100, the first conductive layer 200, the gate dielectric layer 300 and the second conductive layer 400;

a third conductive layer 600 disposed on a side of the second insulating layer 803 facing away from the substrate 100;

a third insulating layer 805 disposed on a side of the third conductive layer 600 away from the substrate 100;

and a second electrode 804 disposed on a side of the third insulating layer 805 facing away from the substrate 100;

wherein the isolation layer includes a first insulating layer and a second insulating layer.

Alternatively, referring to fig. 10, a schematic structural diagram of another array substrate provided in the embodiment of the present application is shown, where the array substrate includes: the substrate 100, the first conductive layer 200, the gate dielectric layer 300 and the second conductive layer 400;

the third conductive layer 600 is arranged on one side of the first insulating layer 801, which is far away from the substrate 100;

a second insulating layer 803 disposed on a side of the third conductive layer 600 away from the substrate 100;

a first electrode 802 disposed on a side of the second insulating layer 803 facing away from the substrate 100;

a third insulating layer 805 disposed on a side of the first electrode 802 away from the substrate 100;

wherein the isolation layer comprises a first insulating layer.

Alternatively, referring to fig. 11, a schematic structural diagram of another array substrate provided in the embodiment of the present application is shown, where the array substrate includes: the substrate 100, the first conductive layer 200, the gate dielectric layer 300 and the second conductive layer 400;

the driving electrodes 806 are disposed on a side of the first insulating layer 801 facing away from the substrate 100, and the driving electrodes 806 include first electrodes and second electrodes;

a second insulating layer 803 disposed on a side of the driving electrode 802 away from the substrate 100;

and a third conductive layer 600 disposed on a side of the driving electrode 803 facing away from the substrate 100;

Alternatively, referring to fig. 12, a schematic structural diagram of another array substrate provided in the embodiment of the present application is shown, where the array substrate includes: the substrate 100, the first conductive layer 200, the gate dielectric layer 300 and the second conductive layer 400;

and a driving electrode 806 disposed on a side of the second insulating layer 803 facing away from the substrate 100, the driving electrode 806 including a first electrode and a second electrode;

wherein the isolation layer comprises a first insulating layer.

In the foregoing, the embodiments of the present application may provide that the first electrode is a common electrode, and the second electrode is a pixel electrode; or, the first electrode is a pixel electrode and the second electrode is a common electrode.

Further, the array substrate provided in the embodiment of the present application may be a self-capacitance touch array substrate, and refer to fig. 13, which is a schematic view of a touch structure of the array substrate provided in the embodiment of the present application, wherein a common electrode of the array substrate is divided into a plurality of mutually independent touch electrodes 201;

a plurality of touch lines 202 disposed in the display area 10, each touch line 202 being electrically connected to a touch electrode 201;

wherein, the touch electrode 201 is applied with a common voltage in the display stage, and the touch electrode is applied with a touch detection signal in the touch stage;

the touch line 202 is disposed on the third conductive layer.

Optionally, the non-display area 20 includes: a plurality of touch line leads 203, each touch line lead 203 being connected to a touch line 202;

fig. 14a is a cross-sectional view taken along the direction bb' in fig. 13, wherein, referring to fig. 14a, when the first electrode lead 20a is disposed on the first conductive layer 200, the touch line lead 203 is disposed on the second conductive layer 400, and the touch line lead and the touch line are electrically connected by a via hole;

alternatively, referring to fig. 14b, which is another sectional view along the bb' direction in fig. 13, wherein, referring to fig. 14b, when the first electrode lead 20a is disposed on the second conductive layer 400, the touch line lead 203 is disposed on the first conductive layer 200, and the touch line lead 203 and the touch line are electrically connected by a via. The first electrode lead, the second electrode lead and the touch electrode lead can be overlapped, so that the occupied area of the leads is saved, and the utilization rate of the array substrate is improved.

In addition, an embodiment of the present application further provides a display panel including the array substrate provided in any one of the above embodiments.

Finally, an embodiment of the present application further provides a display device, including the display panel provided in the foregoing embodiment.

The embodiment of the application provides an array substrate, display panel and display device, include the display area and encircle the non-display area of display area, the non-display area includes many first electrode leads and many second electrode leads, and there is the overlap in the time interval that first electrode lead and second electrode lead are exerted the signal, the non-display area of array substrate includes: a substrate; the first conducting layer is arranged on the surface of the substrate; the gate dielectric layer is arranged on one side, away from the substrate, of the first conducting layer; the second conducting layer is arranged on one side, away from the substrate, of the gate dielectric layer; the isolation layer is arranged on one side, away from the substrate, of the second conducting layer, the thickness of the isolation layer is larger than that of the gate dielectric layer, and/or the dielectric constant of the isolation layer is smaller than that of the gate dielectric layer; the third conducting layer is arranged on one side, away from the substrate, of the isolation layer; wherein the first electrode lead is disposed on the first conductive layer or the second conductive layer, and the second electrode lead is disposed on the third conductive layer.

According to the technical scheme, the thickness of the isolation layer is larger than that of the gate dielectric layer, and/or the dielectric constant of the isolation layer is smaller than that of the gate dielectric layer, so that when the first electrode lead and the second electrode lead are simultaneously applied with signals, the interference phenomenon between the first electrode lead and the second electrode lead which are located on different conducting layers is improved, then through reasonable wiring, the wiring layout of the array substrate can be greatly saved, and the utilization rate of the array substrate is further improved.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An array substrate comprises a display area and a non-display area surrounding the display area, wherein the non-display area comprises a plurality of first electrode leads and a plurality of second electrode leads, and the array substrate is characterized by further comprising:

a substrate;

the first conducting layer is arranged on the surface of the substrate and comprises a grid electrode;

a semiconductor layer disposed between the substrate and the first conductive layer, the semiconductor layer including an active region, a gate insulating layer disposed between the semiconductor layer and the first conductive layer;

the second conducting layer is arranged on one side, away from the substrate, of the gate dielectric layer and comprises a source drain electrode, wherein the gate electrode, the source drain electrode and the active region form a thin film transistor;

the isolation layer is arranged on one side, away from the substrate, of the second conducting layer, the thickness of the isolation layer is larger than that of the gate dielectric layer, the thickness of the isolation layer is not smaller than 1.8 microns, and/or the dielectric constant of the isolation layer is smaller than that of the gate dielectric layer;

2. The array substrate of claim 1, wherein the first electrode lead and the second electrode lead have an overlapping region therebetween along a light transmission direction of the array substrate.

3. The array substrate of claim 2, wherein the first electrode lead and the second electrode lead extend in the same direction.

4. The array substrate of claim 2, wherein the first electrode lead and the second electrode lead extend at an angle therebetween.

5. The array substrate of claim 1, wherein the first and second electrode leads have the same resistance.

6. The array substrate of claim 1, wherein the non-display region comprises a gate driving circuit region and a step region, wherein,

the grid driving circuit area comprises a plurality of grid line leads, and each grid line lead is connected with one grid line of the array substrate;

the step area comprises a plurality of data line leads, and each data line lead is connected with a data line of the array substrate;

the first electrode lead and the second electrode lead are both gate line leads or data line leads.

7. The array substrate of claim 1, wherein the array substrate comprises: the substrate, the first conducting layer, the gate dielectric layer and the second conducting layer;

the first insulating layer is arranged on one side, away from the substrate, of the second conducting layer;

the first electrode is arranged on one side, away from the substrate, of the first insulating layer;

the second insulating layer is arranged on one side, away from the substrate, of the first electrode;

the second electrode is arranged on one side, away from the substrate, of the second insulating layer;

the third insulating layer is arranged on one side, away from the substrate, of the second electrode;

the third conducting layer is arranged on one side, away from the substrate, of the third insulating layer;

wherein the isolation layer includes the first, second, and third insulating layers.

8. The array substrate of claim 1, wherein the array substrate comprises: the substrate, the first conducting layer, the gate dielectric layer and the second conducting layer;

the third conducting layer is arranged on one side, away from the substrate, of the second insulating layer;

the third insulating layer is arranged on one side, away from the substrate, of the third conducting layer;

the second electrode is arranged on one side, away from the substrate, of the third insulating layer;

wherein the isolation layer includes the first and second insulating layers.

9. The array substrate of claim 1, wherein the array substrate comprises: the substrate, the first conducting layer, the gate dielectric layer and the second conducting layer;

the third conducting layer is arranged on one side, away from the substrate, of the first insulating layer;

the second insulating layer is arranged on one side, away from the substrate, of the third conducting layer;

the first electrode is arranged on one side, away from the substrate, of the second insulating layer;

the third insulating layer is arranged on one side, away from the substrate, of the first electrode;

wherein the isolation layer comprises the first insulating layer.

10. The array substrate of claim 1, wherein the array substrate comprises: the substrate, the first conducting layer, the gate dielectric layer and the second conducting layer;

the driving electrode is arranged on one side, away from the substrate, of the first insulating layer and comprises a first electrode and a second electrode;

the second insulating layer is arranged on one side, away from the substrate, of the driving electrode;

the third conducting layer is arranged on one side, away from the substrate, of the driving electrode;

wherein the isolation layer includes the first and second insulating layers.

11. The array substrate of claim 1, wherein the array substrate comprises: the substrate, the first conducting layer, the gate dielectric layer and the second conducting layer;

the driving electrode is arranged on one side, away from the substrate, of the second insulating layer and comprises a first electrode and a second electrode;

wherein the isolation layer comprises the first insulating layer.

12. The array substrate of any one of claims 7 to 11, wherein the first electrode is a common electrode and the second electrode is a pixel electrode;

or, the first electrode is a pixel electrode, and the second electrode is a common electrode.

13. The array substrate of claim 12, wherein the common electrode is divided into a plurality of independent touch electrodes;

the touch control lines are arranged in the display area, and each touch control line is electrically connected with one touch control electrode;

the touch electrode is applied with a common voltage in a display stage, and the touch electrode is applied with a touch detection signal in a touch stage;

wherein the touch line is disposed on the third conductive layer.

14. The array substrate of claim 13, wherein the non-display area comprises: the touch control line leads are connected with one touch control line respectively;

when the first electrode lead is arranged on the first conductive layer, the touch control line lead is arranged on the second conductive layer, and the touch control line lead is electrically connected with the touch control line in a via hole mode;

or when the first electrode lead is arranged on the second conductive layer, the touch line lead is arranged on the first conductive layer, and the touch line lead is electrically connected with the touch line in a via hole mode.

15. A display panel comprising the array substrate according to any one of claims 1 to 14.

16. A display device characterized by comprising the display panel according to claim 15.