CN104733478A - Array substrate, manufacturing method thereof and display device - Google Patents
Array substrate, manufacturing method thereof and display device Download PDFInfo
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- CN104733478A CN104733478A CN201510162220.9A CN201510162220A CN104733478A CN 104733478 A CN104733478 A CN 104733478A CN 201510162220 A CN201510162220 A CN 201510162220A CN 104733478 A CN104733478 A CN 104733478A
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Abstract
The invention discloses an array substrate, a manufacturing method thereof and a display device, and relates to the technical field of display. The narrow border design of the display device is facilitated. A grid drive circuit is arranged in the peripheral region of the array substrate and comprises at least one capacitor, each capacitor comprises a first electrode and a second electrode which are oppositely arranged, and a dielectric layer located between the first electrode and the second electrode, wherein the first electrode and the second electrode are transparent conducting layers, and the dielectric layer is a transparent insulating layer. The array substrate is used for achieving the narrow border design of the display device.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of array base palte and preparation method thereof, display unit.
Background technology
At present, usually the gate driver circuit in display unit is integrated on the neighboring area of array base palte, to reduce the production cost of display unit, production capacity and power consumption, and is conducive to improving product yield and realizing narrow frame.In prior art, the elements such as the holding wire in gate driver circuit, electric capacity and thin-film transistor are all use lighttight rete on array base palte to make.
But present inventor finds, after the follow-up sealed plastic box applied on gate driver circuit region, need to carry out ultraviolet lighting to sealed plastic box, to make sealed plastic box solidify, therefore, require that gate driver circuit region has higher light transmission rate.But each element from the foregoing in gate driver circuit is all light tight, make to only have when the area of gate driver circuit region is larger, and the aperture opening ratio of gate driver circuit region is larger, gate driver circuit region can be made to have higher light transmission rate, but the area of the neighboring area of array base palte can be caused comparatively large, be unfavorable for the narrow frame design of display unit.
Summary of the invention
The object of the present invention is to provide a kind of array base palte and preparation method thereof, display unit, be conducive to the narrow frame design realizing display unit.
For achieving the above object, the invention provides a kind of array base palte, adopting following technical scheme:
The neighboring area of described array base palte is provided with gate driver circuit, described gate driver circuit comprises at least one electric capacity, each described electric capacity includes the first electrode, the second electrode that are oppositely arranged, and the dielectric layer between described first electrode and described second electrode, described first electrode and described second electrode are transparency conducting layer, and described dielectric layer is transparent insulating barrier.
Alternatively, described first Electrode connection at least two signal input parts; Described second Electrode connection at least two signal input parts.
Further, the relative both sides of described first electrode connect a signal input part separately; The relative both sides of described second electrode connect a signal input part separately.
Alternatively, described gate driver circuit also comprises at least one thin-film transistor, and electric capacity described at least one is positioned at above described thin-film transistor.
Further, described thin-film transistor comprise be cascading grid, gate insulator, active layer, with layer arrange source electrode and drain electrode, described source electrode and described drain electrode place layer are provided with resin insulating barrier, and described electric capacity is positioned on described resin insulating barrier.
Further, described array base palte also comprises at described source electrode and the inorganic insulation layer between described drain electrode place layer and described resin insulating barrier, and the material of described inorganic insulation layer is the oxide of silicon and/or the nitride of silicon.
Alternatively, pixel electrode and public electrode is provided with in the viewing area of described array base palte, described first electrode and described public electrode arrange with layer and material is identical, described second electrode and described pixel electrode arrange with layer and material is identical, described pixel electrode place layer and described public electrode are provided with passivation layer between layers, are positioned at the passivation layer of the neighboring area of array base palte as described dielectric layer.
Embodiments provide a kind of array base palte, the neighboring area of this array base palte is provided with gate driver circuit, gate driver circuit comprises at least one electric capacity, each electric capacity includes the first electrode be oppositely arranged, second electrode, and the dielectric layer between the first electrode and the second electrode, because the first electrode and the second electrode are transparency conducting layer, and dielectric layer is transparent insulating barrier, thus make electric capacity region printing opacity, thus improve the light transmission rate of gate driver circuit region, thus the sealed plastic box of subsequent coated when making the area of gate driver circuit region less, can be made to solidify, and then be conducive to the area of the neighboring area reducing array base palte, be conducive to the narrow frame design realizing display unit.
In addition, present invention also offers a kind of display unit, this display unit comprises the array base palte described in above any one.
In order to achieve the above object further, the invention provides a kind of manufacture method of array base palte, adopt following technical scheme:
A kind of manufacture method of array base palte comprises:
Form the first transparency conducting layer, through patterning processes, the neighboring area of array base palte forms the figure comprising the first electrode;
The neighboring area of array base palte forms transparent insulating barrier, using as dielectric layer;
Form the second transparency conducting layer, through patterning processes, the neighboring area of array base palte forms the figure comprising the second electrode;
Described first electrode and described second electrode are oppositely arranged, described dielectric layer is between described first electrode and described second electrode, and described first electrode, described dielectric layer and described second electrode form the electric capacity of the gate driver circuit be arranged on the neighboring area of array base palte.
Further, form the first transparency conducting layer, through patterning processes, the neighboring area of array base palte is formed the step comprising the figure of the first electrode be specially: on array base palte, form described first transparency conducting layer, through patterning processes, the neighboring area of array base palte is formed the figure comprising described first electrode, meanwhile, the viewing area of array base palte forms the figure comprising public electrode;
The neighboring area of array base palte forms transparent insulating barrier, is specially using the step as dielectric layer: on array base palte, form passivation layer, be positioned at passivation layer on the neighboring area of array base palte as described dielectric layer;
Form the second transparency conducting layer, through patterning processes, the neighboring area of array base palte is formed the step comprising the figure of the second electrode be specially: on array base palte, form described second transparency conducting layer, through patterning processes, the neighboring area of array base palte is formed the figure comprising described second electrode, meanwhile, the viewing area of array base palte is formed the figure comprising pixel electrode.
Embodiments provide a kind of manufacture method of array base palte as above, the first electrode made owing to adopting this manufacture method and the second electrode are oppositely arranged, dielectric layer is between the first electrode and the second electrode, first electrode, dielectric layer and the second electrode form the electric capacity of the gate driver circuit be arranged on the neighboring area of array base palte, because the first electrode and the second electrode are transparency conducting layer, and dielectric layer is transparent insulating barrier, thus make electric capacity region printing opacity, thus improve the light transmission rate of gate driver circuit region, thus the sealed plastic box of subsequent coated when making the area of gate driver circuit region less, can be made to solidify, and then be conducive to the area of the neighboring area reducing array base palte, be conducive to the narrow frame design realizing display unit.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the floor map of the neighboring area of array base palte in the embodiment of the present invention;
Fig. 2 be in the embodiment of the present invention Fig. 1 along the schematic cross-section one in A-A ' direction;
Fig. 3 be in the embodiment of the present invention Fig. 1 along the schematic cross-section two in A-A ' direction;
Fig. 4 be in the embodiment of the present invention Fig. 1 along the schematic cross-section three in A-A ' direction;
Fig. 5 is the manufacture method flow chart of the array base palte in the embodiment of the present invention.
Description of reference numerals:
1-electric capacity; 11-the first electrode; 12-the second electrode;
13-dielectric layer; 2-signal input part; 3-thin-film transistor;
31-grid; 32-gate insulator; 33-active layer;
34-source electrode; 35-drain electrode; 4-resin insulating barrier;
5-inorganic insulation layer; 6-passivation layer.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiment one
Embodiments provide a kind of array base palte, particularly, as depicted in figs. 1 and 2, the neighboring area of this array base palte is provided with gate driver circuit, and gate driver circuit comprises at least one electric capacity 1, and each electric capacity 1 includes the first electrode 11, second electrode 12 be oppositely arranged, and the dielectric layer 13 between the first electrode 11 and the second electrode 12, wherein, the first electrode 11 and the second electrode 12 are transparency conducting layer, and dielectric layer 13 is transparent insulating barrier.
Exemplarily, the material of the first electrode 11 and the second electrode 13 is tin indium oxide (ITO) or indium zinc oxide (IZO).
Embodiments provide a kind of array base palte, the neighboring area of this array base palte is provided with gate driver circuit, gate driver circuit comprises at least one electric capacity, each electric capacity includes the first electrode be oppositely arranged, second electrode, and the dielectric layer between the first electrode and the second electrode, because the first electrode and the second electrode are transparency conducting layer, and dielectric layer is transparent insulating barrier, thus make electric capacity region printing opacity, thus improve the light transmission rate of gate driver circuit region, thus the sealed plastic box of subsequent coated when making the area of gate driver circuit region less, can be made to solidify, and then be conducive to the area of the neighboring area reducing array base palte, be conducive to the narrow frame design realizing display unit.
Usually, in prior art, the side of each electrode of the electric capacity in gate driver circuit connects a signal input part, the voltage transmission of signal input part input there will be distortion to during opposite side, cause the lack of homogeneity of the voltage on electrode, therefore, in order to improve the uniformity of the voltage on the first electrode 11 and the second electrode 12, in the embodiment of the present invention preferably, as shown in Figure 1, first electrode 11 connects at least two signal input parts 2, second electrode 12 connects at least two signal input parts 2 (signal input part 2 that the second electrode 12 is connected with it is in FIG covered by the signal input part 2 that the first electrode 11 is connected with it completely), thus the transmission range of the voltage making each signal input part input is short, be not easy to produce distortion, or the distortion produced is very little, and then the uniformity of the voltage on the first electrode 11 and the second electrode 12 can be promoted.
Further, after considering the complexity of the uniformity of voltage on the first electrode 11 and the second electrode 12 and the manufacture method of array base palte, in the embodiment of the present invention preferably, as shown in Figure 1, the relative both sides of the first electrode 11 connect a signal input part 2 separately; The relative both sides of the second electrode 12 connect a signal input part 2 separately.
Alternatively, as shown in Figure 3, gate driver circuit also comprises at least one thin-film transistor 3, in the embodiment of the present invention preferably, at least one electric capacity 1 is positioned at above thin-film transistor 3, thus the area of gate driver circuit region can be reduced, be conducive to the narrow frame design realizing display unit further.
Exemplarily, as shown in Figure 3, thin-film transistor 3 comprise be cascading grid 31, gate insulator 32, active layer 33, the source electrode 34 arranged with layer and drain electrode 35, source electrode 34 and drain electrode 35 place layers are provided with resin insulating barrier 4, and electric capacity 1 is positioned on resin insulating barrier 4.Because the thickness of resin insulating barrier 4 is larger, thus the parasitic capacitance between the first electrode 11 of the grid 31 that can effectively reduce in thin-film transistor 3 and electric capacity 1 and/or the second electrode 12, and/or, reduce the parasitic capacitance between the first electrode 11 of source electrode 34 in thin-film transistor 3 and electric capacity 1 and/or the second electrode 12, and/or, reduce the parasitic capacitance between the first electrode 11 of drain electrode 35 in thin-film transistor 3 and electric capacity 1 and/or the second electrode 12, contribute to the performance promoting array base palte, improve the display effect of display unit.
Further, because the material of usual source electrode 34 and drain electrode 35 place layers is metal or alloy, source electrode 34 and drain electrode 35 place layers and resin insulating barrier 4 between contact performance poor, cause the structural instability of array base palte, therefore, in the embodiment of the present invention preferably, as shown in Figure 4, array base palte also comprises at source electrode 34 and the inorganic insulation layer 5 between drain electrode 35 place layers and resin insulating barrier 4, the material of inorganic insulation layer 5 is the oxide of silicon and/or the nitride of silicon, to make source electrode 34 and between drain electrode 35 place layers and inorganic insulation layer 5, to there is good contact performance, between inorganic insulation layer 5 and resin insulating barrier 4, also there is good contact performance, thus make the structure of array base palte more stable.
In addition, gate driver circuit also comprises many signal line and many connecting lines, and wherein, holding wire is used for each input input signal in gate driver circuit, and connecting line is for realizing the connection between the element such as electric capacity 1, thin-film transistor 3.The embodiment of the present invention is not to the number of holding wire and connecting line, and concrete connected mode limits, and those skilled in the art can reasonably connect up to holding wire and connecting line according to actual needs.
Exemplarily, the array base palte in the embodiment of the present invention can for being applied to the array base palte in twisted nematic display unit, also can for being applied to the array base palte in the transition effects type display unit of senior super dimension field.
When array base palte is when being applied to the array base palte in twisted nematic display unit, pixel electrode is provided with in the viewing area of array base palte, in the embodiment of the present invention preferably, an electrode in electric capacity 1 and pixel electrode arrange with layer and material is identical, to simplify the manufacture method of array base palte, and reduce the cost of array base palte.In addition, also need to make separately layer of transparent conductive layer in the neighboring area of array base palte, for another electrode making electric capacity 1.
When array base palte is when being applied to the array base palte in the transition effects type display unit of senior super dimension field, pixel electrode and public electrode is provided with in the viewing area of array base palte, in the embodiment of the present invention, preferably the first electrode 11 and public electrode are arranged with layer and material is identical, second electrode 12 and pixel electrode arrange with layer and material is identical, pixel electrode place layer and public electrode are provided with passivation layer 6 between layers, be positioned at the passivation layer 6 of the neighboring area of array base palte as dielectric layer 13, to simplify the manufacture method of array base palte, and reduce the cost of array base palte.
Exemplarily, the material of the first electrode 11, second electrode 12, public electrode and pixel electrode is tin indium oxide (ITO).
Further, because the computing formula of electric capacity is: C=ε * S/4 π kd, wherein, ε/4 π k is the relative dielectric constant of dielectric layer 13, S is that the right opposite of the first electrode 11 and the second electrode 12 amasss, and d is the vertical range between the first electrode 11 and the second electrode 12, therefore, the embodiment of the present invention can carry out the capacitance of control capacittance 1 by the thickness that can adjust passivation layer 6, have suitable capacitance to make electric capacity 1.
In addition, present invention also offers a kind of display unit, this display unit comprises the array base palte described in above any one.This display unit can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
Because this display unit comprises the array base palte described in above any one, thus be conducive to the narrow frame design realizing display unit.
Embodiment two
Embodiments provide a kind of manufacture method for making a kind of described array base palte of embodiment, particularly, as shown in Figure 5, this manufacture method comprises:
Step S501, form the first transparency conducting layer, through patterning processes, the neighboring area of array base palte forms the figure comprising the first electrode.
Exemplarily, above-mentioned steps is specially: on array base palte, form the first transparency conducting layer, through patterning processes, the neighboring area of array base palte forms the figure comprising the first electrode, meanwhile, the viewing area of array base palte is formed the figure comprising public electrode.
Step S502, on the neighboring area of array base palte, form transparent insulating barrier, using as dielectric layer.
Exemplarily, above-mentioned steps is specially: on array base palte, form passivation layer, is positioned at passivation layer on the neighboring area of array base palte as dielectric layer.
Step S503, form the second transparency conducting layer, through patterning processes, the neighboring area of array base palte forms the figure comprising the second electrode.
Exemplarily, above-mentioned steps is specially: on array base palte, form the second transparency conducting layer, through patterning processes, the neighboring area of array base palte forms the figure comprising the second electrode, meanwhile, the viewing area of array base palte is formed the figure comprising pixel electrode.
Wherein, the first electrode and the second electrode are oppositely arranged, and dielectric layer is between the first electrode and the second electrode, and the first electrode, dielectric layer and the second electrode form the electric capacity of the gate driver circuit be arranged on the neighboring area of array base palte.
Embodiments provide a kind of manufacture method of array base palte as above, the first electrode made owing to adopting this manufacture method and the second electrode are oppositely arranged, dielectric layer is between the first electrode and the second electrode, first electrode, dielectric layer and the second electrode form the electric capacity of the gate driver circuit be arranged on the neighboring area of array base palte, because the first electrode and the second electrode are transparency conducting layer, and dielectric layer is transparent insulating barrier, thus make electric capacity region printing opacity, thus improve the light transmission rate of gate driver circuit region, thus the sealed plastic box of subsequent coated when making the area of gate driver circuit region less, can be made to solidify, and then be conducive to the area of the neighboring area reducing array base palte, be conducive to the narrow frame design realizing display unit.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (10)
1. an array base palte, the neighboring area of described array base palte is provided with gate driver circuit, described gate driver circuit comprises at least one electric capacity, it is characterized in that, each described electric capacity includes the first electrode, the second electrode that are oppositely arranged, and the dielectric layer between described first electrode and described second electrode, described first electrode and described second electrode are transparent conductive layer, and described dielectric layer is transparent insulating barrier.
2. array base palte according to claim 1, is characterized in that, described first Electrode connection at least two signal input parts; Described second Electrode connection at least two signal input parts.
3. array base palte according to claim 2, is characterized in that, the relative both sides of described first electrode connect a signal input part separately; The relative both sides of described second electrode connect a signal input part separately.
4. the array base palte according to any one of claim 1-3, is characterized in that, described gate driver circuit also comprises at least one thin-film transistor, and electric capacity described at least one is positioned at above described thin-film transistor.
5. array base palte according to claim 4, it is characterized in that, described thin-film transistor comprise be cascading grid, gate insulator, active layer, with layer arrange source electrode and drain electrode, described source electrode and described drain electrode place layer are provided with resin insulating barrier, and described electric capacity is positioned on described resin insulating barrier.
6. array base palte according to claim 5, is characterized in that, also comprises at described source electrode and the inorganic insulation layer between described drain electrode place layer and described resin insulating barrier, and the material of described inorganic insulation layer is the oxide of silicon and/or the nitride of silicon.
7. array base palte according to claim 1, it is characterized in that, pixel electrode and public electrode is provided with in the viewing area of described array base palte, described first electrode and described public electrode arrange with layer and material is identical, described second electrode and described pixel electrode arrange with layer and material is identical, described pixel electrode place layer and described public electrode are provided with passivation layer between layers, are positioned at the passivation layer of the neighboring area of array base palte as described dielectric layer.
8. a display unit, is characterized in that, comprises the array base palte as described in any one of claim 1-7.
9. a manufacture method for array base palte, is characterized in that, comprising:
Form the first transparency conducting layer, through patterning processes, the neighboring area of array base palte forms the figure comprising the first electrode;
The neighboring area of array base palte forms transparent insulating barrier, using as dielectric layer;
Form the second transparency conducting layer, through patterning processes, the neighboring area of array base palte forms the figure comprising the second electrode;
Described first electrode and described second electrode are oppositely arranged, described dielectric layer is between described first electrode and described second electrode, and described first electrode, described dielectric layer and described second electrode form the electric capacity of the gate driver circuit be arranged on the neighboring area of array base palte.
10. the manufacture method of array base palte according to claim 9, is characterized in that,
Form the first transparency conducting layer, through patterning processes, the neighboring area of array base palte is formed the step comprising the figure of the first electrode be specially: on array base palte, form described first transparency conducting layer, through patterning processes, the neighboring area of array base palte is formed the figure comprising described first electrode, meanwhile, the viewing area of array base palte is formed the figure comprising public electrode;
The neighboring area of array base palte forms transparent insulating barrier, is specially using the step as dielectric layer: on array base palte, form passivation layer, be positioned at passivation layer on the neighboring area of array base palte as described dielectric layer;
Form the second transparency conducting layer, through patterning processes, the neighboring area of array base palte is formed the step comprising the figure of the second electrode be specially: on array base palte, form described second transparency conducting layer, through patterning processes, the neighboring area of array base palte is formed the figure comprising described second electrode, meanwhile, the viewing area of array base palte is formed the figure comprising pixel electrode.
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| CN201510162220.9A CN104733478A (en) | 2015-04-07 | 2015-04-07 | Array substrate, manufacturing method thereof and display device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018139450A1 (en) * | 2017-01-27 | 2018-08-02 | シャープ株式会社 | Active matrix substrate and display device using same |
| CN108598095A (en) * | 2018-05-23 | 2018-09-28 | 京东方科技集团股份有限公司 | Display base plate and preparation method thereof, detection method |
| CN109060160A (en) * | 2018-06-25 | 2018-12-21 | 泗阳君子兰激光科技发展有限公司 | High voltage bearing temperature sensor |
| CN110071119A (en) * | 2019-04-09 | 2019-07-30 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101673013A (en) * | 2008-09-12 | 2010-03-17 | 乐金显示有限公司 | Liquid crystal display device including touch panel |
| US20100066702A1 (en) * | 2008-09-12 | 2010-03-18 | Deuk Su Lee | Liquid crystal display device and method of manufacturing thereof |
| CN103676362A (en) * | 2013-12-18 | 2014-03-26 | 京东方科技集团股份有限公司 | Liquid crystal optical grating substrate, liquid crystal optical grating and display device |
| CN103677412A (en) * | 2013-12-09 | 2014-03-26 | 合肥京东方光电科技有限公司 | Embedded touch screen and driving method thereof |
| CN103760702A (en) * | 2013-11-20 | 2014-04-30 | 友达光电股份有限公司 | Display panel |
-
2015
- 2015-04-07 CN CN201510162220.9A patent/CN104733478A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101673013A (en) * | 2008-09-12 | 2010-03-17 | 乐金显示有限公司 | Liquid crystal display device including touch panel |
| US20100066702A1 (en) * | 2008-09-12 | 2010-03-18 | Deuk Su Lee | Liquid crystal display device and method of manufacturing thereof |
| CN103760702A (en) * | 2013-11-20 | 2014-04-30 | 友达光电股份有限公司 | Display panel |
| CN103677412A (en) * | 2013-12-09 | 2014-03-26 | 合肥京东方光电科技有限公司 | Embedded touch screen and driving method thereof |
| CN103676362A (en) * | 2013-12-18 | 2014-03-26 | 京东方科技集团股份有限公司 | Liquid crystal optical grating substrate, liquid crystal optical grating and display device |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018139450A1 (en) * | 2017-01-27 | 2018-08-02 | シャープ株式会社 | Active matrix substrate and display device using same |
| CN110226193A (en) * | 2017-01-27 | 2019-09-10 | 夏普株式会社 | Active-matrix substrate and the display device for using it |
| JPWO2018139450A1 (en) * | 2017-01-27 | 2019-11-14 | シャープ株式会社 | Active matrix substrate and display device using the same |
| US10725352B2 (en) | 2017-01-27 | 2020-07-28 | Sharp Kabushiki Kaisha | Active matrix substrate and display device using same |
| CN108598095A (en) * | 2018-05-23 | 2018-09-28 | 京东方科技集团股份有限公司 | Display base plate and preparation method thereof, detection method |
| US10896859B2 (en) | 2018-05-23 | 2021-01-19 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate, method for forming display substrate and method for detecting the same |
| CN109060160A (en) * | 2018-06-25 | 2018-12-21 | 泗阳君子兰激光科技发展有限公司 | High voltage bearing temperature sensor |
| CN110071119A (en) * | 2019-04-09 | 2019-07-30 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN110071119B (en) * | 2019-04-09 | 2021-07-06 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
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Application publication date: 20150624 |