CN107482020A - 一种阵列基板及其制造方法 - Google Patents

一种阵列基板及其制造方法 Download PDF

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CN107482020A
CN107482020A CN201710718137.4A CN201710718137A CN107482020A CN 107482020 A CN107482020 A CN 107482020A CN 201710718137 A CN201710718137 A CN 201710718137A CN 107482020 A CN107482020 A CN 107482020A
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pixel electrode
substrate
array base
base palte
hole
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王跃林
赵艳艳
徐敬义
李磊
方业周
刘铁男
任艳伟
付弋珊
秦伟达
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to CN201710718137.4A priority Critical patent/CN107482020A/zh
Publication of CN107482020A publication Critical patent/CN107482020A/zh
Priority to US16/106,105 priority patent/US10504938B2/en
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Abstract

本发明公开了一种阵列基板及其制造方法。阵列基板包括：第一基板，所述第一基板具有从其一侧露出的漏极；形成在所述第一基板露出漏极一侧的平坦层，所述平坦层开有位于所述漏极之上的台阶孔，且所述台阶孔的孔径自所述平坦层远离所述第一基板的一侧向靠近所述第一基板的方向变小；像素电极，所述像素电极形成在所述台阶孔处且与所述漏极连接；覆盖所述平坦层和所述像素电极的钝化层；形成在所述钝化层之上的公共电极。本发明的阵列基板及其制造方法，与现有技术相比，解决了现有的阵列基板钝化层在像素电极和平坦层相交的位置存在一个像素电极厚度高的段差导致的钝化层容易卷曲脱落的技术问题。

Description

一种阵列基板及其制造方法
技术领域
本发明涉及液晶显示领域，特别涉及一种阵列基板及其制造方法。
背景技术
现有的阵列基板，如图1所示，包括玻璃基板10，缓冲层20，有源层30，栅极绝缘层41，栅极42，源极51，漏极52，层间绝缘层53，平坦层60，像素电极70，钝化层80和公共电极90。平坦层60开有位于漏极52之上过孔，像素电极70覆盖过孔与漏极52连接；钝化层80覆盖平坦层60和像素电极70，公共电极90形成在钝化层80之上。图1所示的阵列基板，像素电极70和公共电极90两层电极形成的电场分布较为均匀，无电场的死角少，使用该阵列基板的显示面板的透过率较高。但是，由于像素电极70是形成在平坦层60表面的，造成像素电极70凸出于平坦层60，且凸出于平坦层的高度是像素电极70的厚度，即像素电极凸出平坦层一个像素电极的厚度。这样，钝化层在像素电极和平坦层相交的位置必然会存在一个像素电极厚度的段差，此段差的高度是直接由像素电极决定的，是不可变的。由于钝化层在像素电极和平坦层相交的位置存在一个像素电极厚度高的段差，导致钝化层在像素电极和平坦层相交的位置容易发生卷曲脱落，进而导致阵列基板的不良率较高，使用该阵列基板的液晶面板存在黑点的不良。
发明内容
本发明提供了一种阵列基板及其制造方法，与现有技术相比，解决了现有的阵列基板钝化层在像素电极和平坦层相交的位置存在一个像素电极厚度高的段差导致的钝化层容易卷曲脱落的技术问题。
为达到上述目的，本发明提供以下技术方案：
一种阵列基板，包括：
第一基板，所述第一基板具有从其一侧露出的漏极；
形成在所述第一基板露出漏极一侧的平坦层，所述平坦层开有位于所述漏极之上的台阶孔，且所述台阶孔的孔径自所述平坦层远离所述第一基板的一侧向靠近所述第一基板的方向变小；
像素电极，所述像素电极形成在所述台阶孔处且与所述漏极连接；
覆盖所述平坦层和所述像素电极的钝化层；
形成在所述钝化层之上的公共电极。
作为一种可选的方式，所述平坦层的上表面与所述像素电极的上表面之间的高度差的绝对值小于所述像素电极的高度；
其中，所述平坦层的上表面是指所述平坦层台阶孔以外部分远离所述第一基板的一侧的表面，所述像素电极的上表面是所述像素电极位于所述台阶孔中距离所述第一基板最远的台阶之上部分的远离所述第一基板的一侧的表面。
作为一种可选的方式，所述像素电极的上表面与所述平坦层的上表面相平；
或者所述像素电极的上表面凸出于平坦层的上表面且凸出的高度小于像素电极的厚度；
或者所述像素电极的上表面凹于所述平坦层的上表面且下凹的深度小于像素电极的厚度。
作为一种可选的方式，所述台阶孔中距离所述第一基板最远的孔的孔径的形状和尺寸与所述阵列基板的像素电极的形状和尺寸相一致。
作为一种可选的方式，所述阵列基板是底栅型阵列基板或顶栅型阵列基板。
本发明还提供以下技术方案：
一种阵列基板的制造方法，包括如下步骤：
形成第一基板，所述第一基板具有从其一侧露出的漏极；
形成覆盖所述第一基板露出所述漏极一侧的平坦层；
在所述平坦层位于所述漏极之上的位置开设台阶孔，且所述台阶孔的孔径自所述平坦层远离所述第一基板的一侧向靠近所述第一基板的方向变小；
形成像素电极，所述像素电极形成在所述台阶孔处且与所述漏极连接；
形成覆盖所述平坦层和所述像素电极的钝化层；
在所述钝化层之上形成公共电极。
作为一种可选的方式，在所述平坦层位于所述漏极之上的位置开设台阶孔的步骤具体包括如下步骤：
通过一个掩膜版的曝光和刻蚀在所述平坦层位于所述漏极之上的位置开设所述台阶孔，所述掩膜版包括全透过通孔和位于所述全透过通孔周围且与之连接的部分透过区域；
其中，所述全透过通孔用于形成所述台阶孔中距离所述第一基板最近的孔，所述部分透过区域用于形成所述台阶孔中距离所述第一基板最近的孔以外的孔。
作为一种可选的方式，所述部分透过区域形成的所述台阶孔中距离所述第一基板最远的孔的深度与所述阵列基板的像素电极的厚度差值的绝对值小于像素电极的厚度值。
作为一种可选的方式，所述部分透过区域形成的所述台阶孔中距离所述第一基板最远的孔的深度等于所述阵列基板所需的像素电极的厚度；
或者所述部分透过区域形成的所述台阶孔中距离所述第一基板最远的孔的深度小于所述阵列基板所需的像素电极的厚度；
或者所述部分透过区域形成的所述台阶孔中距离所述第一基板最远的孔的深度大于所述阵列基板所需的像素电极的厚度且小于像素电极的厚度的两倍。
作为一种可选的方式，所述部分透过区域和全透过区域作为一个整体的形状与尺寸与所述阵列基板的像素电极的形状和尺寸相配合，使得所述台阶孔中距离所述第一基板最远的孔的形状与尺寸与所述阵列基板的像素电极的形状和尺寸相一致。
本发明提供的阵列基板，包括第一基板，平坦层，像素电极，钝化层和公共电极，其中，第一基板具有从其一侧露出的漏极，平坦层形成在第一基板露出漏极一侧，平坦层开有位于漏极之上的台阶孔，且台阶孔的孔径自平坦层远离第一基板的一侧向靠近第一基板的方向变小；像素电极形成在台阶孔处且与漏极连接；钝化层覆盖平坦层和像素电极；公共电极形成在钝化层之上。这样，由于平坦层在漏极之上的位置开有台阶孔，且台阶孔的孔径自平坦层远离第一基板的一侧向靠近第一基板的方向变小，像素电极形成的台阶孔处，即像素电极是形成在向第一基板方向凹陷的方向的台阶孔处，像素电极与平坦层台阶孔以外部分远离第一基板的一侧的表面相比，像素电极凸出的高度一定会低于像素电极的厚度，或者像素电极是低于平坦层台阶孔以外部分远离第一基板的一侧的表面的。这样，在像素电极的厚度为定值时，可以通过控制台阶孔距离第一基板最远的孔的高度控制像素电极与平坦层台阶孔以外部分远离第一基板的一侧的表面之间的段差，实现了钝化层在像素电极和平坦层相交的位置的段差是可控的。通过控制钝化层在像素电极和平坦层相交的位置的段差小于像素电极的厚度，可以实现降低钝化层因在像素电极和平坦层相交的位置发生卷曲脱落的几率，进而提高了阵列基板的良率，使用该基板的液晶面板存在黑点的不良的几率也就随之降低。
附图说明
图1为现有的阵列基板的示意图；
图2为本发明的一个实施例的阵列基板的示意图；
图3为图2所示的阵列基板的平坦层上台阶孔的示意图；
图4为本发明的阵列基板的制造方法的流程图；
图5为图4所述的阵列基板的制造方法中在平坦层开设台阶孔所采用的掩膜版的局部示意图。
主要元件附图标记说明：
现有技术中：
10玻璃基板，20缓冲层，30有源层，41栅极绝缘层，42栅极，51源极，
52漏极，53层间绝缘层，60平坦层，70像素电极，80钝化层，
90公共电极。
本发明中：
100漏极，
200平坦层，210台阶孔，
211台阶孔中距离第一基板最近的孔，212台阶孔中距离第一基板最远的孔，
300像素电极，400钝化层，500公共电极，
600第一基板，610玻璃基板，620缓冲层，630有源层，641栅极绝缘层，
642栅极，651源极，652层间绝缘层。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例一
本发明的实施例一的阵列基板，如图2和图3所示，包括：
第一基板600，第一基板具有从其一侧露出的漏极100；
形成在第一基板露出漏极一侧的平坦层200，平坦层200开有位于漏极100之上的台阶孔210，且台阶孔210的孔径自平坦层200远离第一基板的一侧向靠近第一基板的方向变小，台阶孔中距离第一基板最近的孔用211表示，台阶孔中距离第一基板最远的孔用212；
像素电极300，像素电极300形成在台阶孔210处且与漏极100连接；
覆盖平坦层200和像素电极300的钝化层400；
形成在钝化层400之上的公共电极500。
本实施例的阵列基板，包括第一基板，平坦层，像素电极，钝化层和公共电极，其中，第一基板具有从其一侧露出的漏极，平坦层形成在第一基板露出漏极一侧，平坦层开有位于漏极之上的台阶孔，且台阶孔的孔径自平坦层远离第一基板的一侧向靠近第一基板的方向变小；像素电极形成在台阶孔处且与漏极连接；钝化层覆盖平坦层和像素电极；公共电极形成在钝化层之上。这样，由于平坦层在漏极之上的位置开有台阶孔，且台阶孔的孔径自平坦层远离第一基板的一侧向靠近第一基板的方向变小，像素电极形成的台阶孔处，即像素电极是形成在向第一基板方向凹陷的方向的台阶孔处，像素电极与平坦层台阶孔以外部分远离第一基板的一侧的表面相比，像素电极凸出的高度一定会低于像素电极的厚度，或者像素电极是低于平坦层台阶孔以外部分远离第一基板的一侧的表面的。这样，在像素电极的厚度为定值时，可以通过控制台阶孔中距离第一基板最远的孔的高度控制像素电极与平坦层台阶孔以外部分远离第一基板的一侧的表面之间的段差，实现了钝化层在像素电极和平坦层相交的位置的段差是可控的。通过控制钝化层在像素电极和平坦层相交的位置的段差小于像素电极的厚度，可以实现降低钝化层因在像素电极和平坦层相交的位置发生卷曲脱落的几率，进而提高了阵列基板的良率，使用该基板的液晶面板存在黑点的不良的几率也就随之降低。
钝化层在像素电极和平坦层相交的位置的段差是可控的，我们控制是有针对性的，控制的针对性具体为：平坦层的上表面与像素电极的上表面之间的高度差的绝对值小于像素电极的高度；
其中，平坦层的上表面是指平坦层台阶孔以外部分远离第一基板的一侧的表面，像素电极的上表面是像素电极位于台阶孔中距离第一基板最远的台阶之上部分的远离第一基板的一侧的表面。
这样，钝化层在像素电极和平坦层相交的位置的段差小于像素电极的厚度，可以实现降低钝化层因在像素电极和平坦层相交的位置发生卷曲脱落的几率，进而提高了阵列基板的良率，使用该基板的液晶面板存在黑点的不良的几率也就随之降低了。
平坦层的上表面与像素电极的上表面之间的高度差的绝对值小于像素电极的高度，包括以下三种可实施的方式：
第一种可实施的方式：如图2所示的，平坦层200的上表面与像素电极300的上表面相平。即钝化层在像素电极和平坦层相交的位置没有高度差，是最理想的实施方式。这样，钝化层在像素电极和平坦层相交的位置没有段差，是一个平面，最大程度降低钝化层因在像素电极和平坦层相交的位置发生卷曲脱落的几率，进而提高了阵列基板的良率。
第二种可实施的方式：台阶孔中距离第一基板最远的孔的深度小于像素电极的厚度，即像素电极的上表面凸出于平坦层的上表面且凸出的高度小于像素电极的厚度。
第二种可实施的方式：台阶孔距离第一基板最远的孔的深度大于像素电极的厚度且小于像素电极的厚度的两倍，即像素电极的上表面凹于平坦层的上表面且下凹的深度小于像素电极的厚度。
这三种可实施的方式，都能实现降低钝化层因在像素电极和平坦层相交的位置发生卷曲脱落的几率，进而提高了阵列基板的良率，使用该基板的液晶面板存在黑点的不良的几率也就随之降低。
像素电极的形状和尺寸是和阵列基板及与之配合使用的彩膜基板相关的，因此，像素电极的形状和尺寸是根据阵列基板及与之配合使用的彩膜基板决定的，台阶孔中距离第一基板最远的孔212的形状和尺寸是需要与阵列基板的像素电极的形状和尺寸相一致。
这样，台阶孔中距离第一基板最远的孔212与像素电极相一致，使得台阶孔能与阵列基板的其他结构相适应，减少对阵列基板的结构的改变。
本发明的阵列基板是针对像素电极和公共电极都设置在阵列基板上且两者之间绝缘，像素电极位于下方靠近第一基板一侧，公共电极位于上方远离第一基板的一侧中像素电极形成位置的改进，不限于图示中的阵列基板的类型。本发明的阵列基板可以是底栅型的阵列基板，可以是顶栅型的阵列基板，同样，可以是多晶硅阵列基板，还可以是非多晶硅阵列基板。
本发明阵列基板中的第一基板，根据阵列基板的类型不同，第一基板包括的结构可能也有所差别，如图2和图3所示的阵列基板，第一基板600包括玻璃基板610，缓冲层620，有源层630，栅极绝缘层641，栅极642，源极651，层间绝缘层652等等结构，其中，层间绝缘层652为源极和漏极提供绝缘；如果阵列基板是多晶硅的阵列基板，有源层采用多晶硅材料形成有源层，并在玻璃基板和缓冲层之间形成用于遮挡多晶硅有源层的挡光层。
实施例二
如图4所示，本发明的实施例二的阵列基板包括如下步骤：
形成第一基板，第一基板具有从其一侧露出的漏极；
形成覆盖第一基板露出漏极一侧的平坦层；
在平坦层位于漏极之上的位置开设台阶孔，且台阶孔的孔径自平坦层远离所述第一基板的一侧向靠近第一基板的方向变小；
形成像素电极，像素电极形成在台阶孔处且与漏极连接；
形成覆盖平坦层和像素电极的钝化层；
在钝化层之上形成公共电极。
现有技术中的阵列基板的制造方法中具有在平坦层位于漏极之上的位置开设过孔的步骤。本发明的实施例二的阵列基板的制造方法，没有增加额外的制造工艺，只是将现有技术中在平坦层位于漏极之上的位置开设过孔的步骤，替换成了在平坦层位于漏极之上的位置开设台阶孔，且台阶孔的孔径自平坦层远离第一基板的一侧向靠近第一基板的方向变小的步骤，而制造出的阵列基板钝化层在像素电极和平坦层相交的位置的段差是可控的，通过控制钝化层在像素电极和平坦层相交的位置的段差小于像素电极的厚度，可以实现降低钝化层因在像素电极和平坦层相交的位置发生卷曲脱落的几率，进而提高了阵列基板的良率，使用该基板的液晶面板存在黑点的不良的几率也就随之降低了。
在平坦层位于漏极之上的位置开设台阶孔的步骤具体包括如下步骤：
通过一个掩膜版的曝光和刻蚀在平坦层位于漏极之上的位置开设台阶孔，如图5所示，掩膜版包括全透过通孔710和位于全透过通孔周围且与之连接的部分透过区域720；
其中，全透过通孔用于形成台阶孔中距离第一基板最近的孔211，部分透过区域用于形成台阶孔中距离第一基板最近的孔以外的孔。
这样，通过采用具有全透过通孔和部分透过区域的掩膜版，仅需要一个掩膜版，经过一次曝光和刻蚀，即可得到台阶孔。
掩膜版的部分透过区域形成的台阶孔中距离第一基板最远的孔的深度是与掩膜版的部分透过区域的透过率相关的，通过控制掩膜版的部分透过区域的透过率达到部分透过区域形成的台阶孔中距离第一基板最远的孔的深度与阵列基板的像素电极的厚度差值的绝对值小于像素电极的厚度值。
部分透过区域形成的台阶孔中距离第一基板最远的孔的深度与阵列基板的像素电极的厚度差值的绝对值小于像素电极的厚度值包括三种可实施的方式：
第一种可实施的方式是：部分透过区域形成的台阶孔中距离第一基板最远的孔的深度等于阵列基板所需的像素电极的厚度；
第二种可实施的方式是：部分透过区域形成的台阶孔中距离第一基板最远的孔的深度小于阵列基板所需的像素电极的厚度；
第三种可实施的方式是：部分透过区域形成的台阶孔中距离第一基板最远的孔的深度大于阵列基板所需的像素电极的厚度且小于像素电极的厚度的两倍。
这三种可实施的方式制造出的阵列基板，都能实现降低钝化层因在像素电极和平坦层相交的位置发生卷曲脱落的几率，进而提高了阵列基板的良率，使用该基板的液晶面板存在黑点的不良的几率也就随之降低。
像素电极的形状和尺寸是和阵列基板及与之配合使用的彩膜基板相关的，因此，像素电极的形状和尺寸是根据阵列基板及与之配合使用的彩膜基板决定的，台阶孔中距离第一基板最远的孔的形状和尺寸是需要与阵列基板的像素电极的形状和尺寸相一致。为了达到这个效果，在阵列基板的制造方法中，需要部分透过区域和全透过区域作为一个整体的形状与尺寸与阵列基板的像素电极的形状和尺寸相配合，使得台阶孔中距离第一基板最远的孔的形状与尺寸与阵列基板的像素电极的形状和尺寸相一致。
阵列基板的类型不同，所需要的制造方法也不同，阵列基板所需要的其他步骤采用相应的步骤完成即可。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (10)

1.一种阵列基板，其特征在于，包括：
第一基板，所述第一基板具有从其一侧露出的漏极；
形成在所述第一基板露出漏极一侧的平坦层，所述平坦层开有位于所述漏极之上的台阶孔，且所述台阶孔的孔径自所述平坦层远离所述第一基板的一侧向靠近所述第一基板的方向变小；
像素电极，所述像素电极形成在所述台阶孔处且与所述漏极连接；
覆盖所述平坦层和所述像素电极的钝化层；
形成在所述钝化层之上的公共电极。
2.根据权利要求1所述的阵列基板，其特征在于，所述平坦层的上表面与所述像素电极的上表面之间的高度差的绝对值小于所述像素电极的高度；
其中，所述平坦层的上表面是指所述平坦层台阶孔以外部分远离所述第一基板的一侧的表面，所述像素电极的上表面是所述像素电极位于所述台阶孔中距离所述第一基板最远的台阶之上部分的远离所述第一基板的一侧的表面。
3.根据权利要求2所述的阵列基板，其特征在于，所述像素电极的上表面与所述平坦层的上表面相平；
或者所述像素电极的上表面凸出于平坦层的上表面且凸出的高度小于像素电极的厚度；
或者所述像素电极的上表面凹于所述平坦层的上表面且下凹的深度小于像素电极的厚度。
4.根据权利要求1所述的阵列基板，其特征在于，所述台阶孔中距离所述第一基板最远的孔的孔径的形状和尺寸与所述阵列基板的像素电极的形状和尺寸相一致。
5.根据权利要求1所述的阵列基板，其特征在于，所述阵列基板是底栅型阵列基板或顶栅型阵列基板。
6.一种阵列基板的制造方法，其特征在于，包括如下步骤：
形成第一基板，所述第一基板具有从其一侧露出的漏极；
形成覆盖所述第一基板露出所述漏极一侧的平坦层；
在所述平坦层位于所述漏极之上的位置开设台阶孔，且所述台阶孔的孔径自所述平坦层远离所述第一基板的一侧向靠近所述第一基板的方向变小；
形成像素电极，所述像素电极形成在所述台阶孔处且与所述漏极连接；
形成覆盖所述平坦层和所述像素电极的钝化层；
在所述钝化层之上形成公共电极。
7.根据权利要求6所述的阵列基板的制造方法，其特征在于，在所述平坦层位于所述漏极之上的位置开设台阶孔的步骤具体包括如下步骤：
通过一个掩膜版的曝光和刻蚀在所述平坦层位于所述漏极之上的位置开设所述台阶孔，所述掩膜版包括全透过通孔和位于所述全透过通孔周围且与之连接的部分透过区域；
其中，所述全透过通孔用于形成所述台阶孔中距离所述第一基板最近的孔，所述部分透过区域用于形成所述台阶孔中距离所述第一基板最近的孔以外的孔。
8.根据权利要求7所述的阵列基板的制造方法，其特征在于，所述部分透过区域形成的所述台阶孔中距离所述第一基板最远的孔的深度与所述阵列基板的像素电极的厚度差值的绝对值小于像素电极的厚度值。
9.根据权利要求8所述的阵列基板的制造方法，其特征在于，所述部分透过区域形成的所述台阶孔中距离所述第一基板最远的孔的深度等于所述阵列基板所需的像素电极的厚度；
或者所述部分透过区域形成的所述台阶孔中距离所述第一基板最远的孔的深度小于所述阵列基板所需的像素电极的厚度；
或者所述部分透过区域形成的所述台阶孔中距离所述第一基板最远的孔的深度大于所述阵列基板所需的像素电极的厚度且小于像素电极的厚度的两倍。
10.根据权利要求7所述的阵列基板的制造方法，其特征在于，所述部分透过区域和全透过区域作为一个整体的形状与尺寸与所述阵列基板的像素电极的形状和尺寸相配合，使得所述台阶孔中距离所述第一基板最远的孔的形状与尺寸与所述阵列基板的像素电极的形状和尺寸相一致。
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