CN107464746A - 用于半导体装置的阈值电压及井植入方法 - Google Patents

用于半导体装置的阈值电压及井植入方法 Download PDF

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CN107464746A
CN107464746A CN201710418214.4A CN201710418214A CN107464746A CN 107464746 A CN107464746 A CN 107464746A CN 201710418214 A CN201710418214 A CN 201710418214A CN 107464746 A CN107464746 A CN 107464746A
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area
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fin
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CN107464746B (zh
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戴鑫托
布莱恩·葛伦
马翰德·库玛
丹尼尔·J·德契恩
丹尼尔·杰格
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GlobalFoundries US Inc
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  • Thin Film Transistor (AREA)

Abstract

本发明涉及用于半导体装置的阈值电压及井植入方法，其用于图案化及植入的方法提供多个具体实施例，包括下列步骤：形成多个鳍片；形成一SiN于该多个鳍片上方；形成一a‑Si层于该SiN上方；形成及图案化一第一图案化层于该a‑Si层上方；使用该第一图案化层作为一掩模，蚀刻穿过该a‑Si层；移除该第一图案化层；植入离子于暴露的鳍片群组中；形成及图案化一第二图案化层以暴露一第一鳍片群组以及该a‑Si层在该第一鳍片群组的两对边上的一部分；植入离子于该第一鳍片群组的一第一区域中；形成一第三图案化层于该第一鳍片群组的该第一区域上方以及暴露该第一鳍片群组的一第二区域；以及植入离子于该第一鳍片群组的该第二区域中。

Description

用于半导体装置的阈值电压及井植入方法
技术领域
本揭示内容有关于半导体装置的光刻及离子植入。特别是，本揭示内容有关用于属10纳米(nm)以下技术节点、具有鳍片的半导体装置的图案化及离子植入技术。
背景技术
随着半导体加工进步到10纳米技术节点，众多技术挑战强迫使用成本更贵的浸镀层(immersion layer)。有些技术挑战包括关键栅极间距(3CPP)的最小面积要求，在10纳米技术节点会更窄小的N-P接面(junction)崩溃制程裕度，以及在10纳米技术节点更加关键的角落圆角化要求(corner rounding requirement；CRR)。由于这些技术挑战，用于多层的浸镀制程变成有必要。在10纳米技术节点的现有加工下，存在制程裕度的显著减少是由于边缘设置的影响，CRR与必要制程偏差(required process bias)的复合。
用其他现有制程，即使致能基于井(well)的阈值电压(Vt)调整，Vt调整位准仍为最小面积限制禁止3CPP单元调换的牺牲者。在其他现有制程中，10纳米单元(cell)的N-P接面间距减少已使相对崩溃裕度减少33％。由于重叠、鳍片设置及关键尺寸(critical dimension；CD)公差，为了恢复减少33％的裕度，转移到浸镀加工变成有必要。当前静态随机存取存储器(SRAM)单元的另一挑战是N-P空间几乎有10％的额外减少。形貌的影响，布林比较(boolean comps)及蚀刻偏差(etch bias)对于有窄小N-P接面间距的图案化裕度可能有进一步的负面影响。
因此，亟须方法供致能可改善N-P接面间距及CRR而不依赖昂贵浸镀制程的图案化及植入。
发明内容
本揭示内容的一方面为一种独特的图案化及植入方案，它可改善N-P接面间距及CRR而不使用昂贵的浸镀制程。
本揭示内容的其他方面及特征会在以下说明中提出以及部分在本领域技术人员审查以下内容或学习本揭示内容的实施后会明白。按照随附权利要求书所特别提示，可实现及得到本揭示内容的优点。
根据本揭示内容，有些技术效果部分可用一种方法达成，其包括：在一基板上方的多个区域中形成多个鳍片群组；形成一氮化硅(SiN)于该多个鳍片群组上方；形成一非晶硅(a-Si)层于该SiN上方；形成及图案化一第一图案化层于该a-Si层上方；使用该第一图案化层作为一掩模，蚀刻穿过该a-Si层向下到该SiN；移除该第一图案化层；在蚀刻该a-Si层后，植入离子于暴露的鳍片群组中；形成及图案化一第二图案化层以暴露一第一鳍片群组以及该a-Si层在该第一鳍片群组的两对边上的一部分；植入离子于该第一鳍片群组的一第一区域中；形成一第三图案化层于该第一鳍片群组的该第一区域上方以及暴露该第一鳍片群组的一第二区域；以及植入离子于该第一鳍片群组的该第二区域中。
数个方面包括：形成一氧化物层于个别鳍片之间以及于该多个鳍片群组之间且形成该SiN于该氧化物层上方。其他方面包括：形成一第四图案化层至少于该第一鳍片群组的该第二区域上方。其他方面也包括：移除该第四图案化层以暴露该第一鳍片群组的一第三区域。其他方面更包括：植入离子于该第一鳍片群组的该第三区域中。其他方面包括：沉积一第二氧化物层于该SiN及一a-Si层上方。数个方面包括：平坦化该第二氧化物层向下到该a-Si层的一上表面。其他方面也包括：在平坦化该第二氧化物层后，移除该a-Si层。其他方面更包括：在移除该a-Si层后，植入离子于暴露的第二鳍片群组中。其他方面又包括：形成及图案化一第五图案化层以暴露该第二鳍片群组以及该第二氧化物层在该第二鳍片群组的两对边上的一部分。其他方面包括：植入离子于该第二鳍片群组的一第一区域中。其他方面也包括：形成一第六图案化层于该第二鳍片群组的该第一区域上方以及暴露该第二鳍片群组的一第二区域。其他方面又包括：植入离子于该第二鳍片群组的该第二区域中。其他方面也包括：形成一第七图案化层于该第二鳍片群组的该第二区域上方以及暴露该第二鳍片群组的一第三区域。其他方面更包括：移除该第七图案化层；移除该第二氧化物层；以及移除该SiN。
又在本申请案的另一方面中，提供，一种方法，其包括：在一基板上方的多个区域中形成多个鳍片群组；形成SiN于该多个鳍片群组上方；形成一a-Si于该SiN上方；形成及图案化一第一图案化层于该a-Si层上方；使用该第一图案化层作为一掩模，蚀刻穿过该a-Si层向下到该SiN；移除该第一图案化层；在蚀刻该a-Si层后，植入离子于暴露的鳍片群组中；形成及图案化一第二图案化层以暴露在一NFET区域中的一第一鳍片群组以及该a-Si层形成于在一PFET区域中的一第二鳍片群组上方的一部分；植入离子于该第一鳍片群组的一第一区域中；形成一第三图案化层至少于该第一鳍片群组的该第一区域上方以及暴露该第一鳍片群组的一第二区域；以及植入离子于该第一鳍片群组的该第二区域中。
数个方面包括：形成一第四图案化层至少于该第一鳍片群组的该第二区域上方以及暴露该第一鳍片群组的一第三区域；以及植入离子于该第一鳍片群组的该第三区域中。某些方面包括：沉积一氧化物层于该SiN及一a-Si层上方；平坦化该氧化物层向下到该a-Si层的一上表面；移除该a-Si层；以及在移除该a-Si层后，植入离子于暴露的鳍片群组中。其他方面包括：形成及图案化一第五图案化层以暴露在该PFET区域中的该第二鳍片群组以及该氧化物层在一第二NFET区域中的一部分；植入离子于该第二鳍片群组的一第一区域中；形成一第六图案化层至少于该第二鳍片群组的该第一区域上方以及暴露该第二鳍片群组的一第二区域；植入离子于该第二鳍片群组的该第二区域中；形成一第七图案化层至少于该第二鳍片群组的该第二区域上方以及暴露该第二鳍片群组的一第三区域；移除该第七图案化层；移除该第二氧化物层；以及移除该SiN。
又在本申请案的另一方面，提供一种方法，其包括：在一基板上方的多个区域中形成多个鳍片群组，其中形成一氧化物层于个别鳍片之间以及于该多个鳍片群组之间；形成SiN于该氧化物层上方；形成一a-Si层于该SiN上方；形成及图案化一第一图案化层于该a-Si层上方；使用该第一图案化层作为一掩模，蚀刻穿过该a-Si层向下到该SiN；移除该第一图案化层；在蚀刻该a-Si层后，植入离子于暴露的鳍片群组中；形成及图案化一第二图案化层以暴露在一NFET区域中的一第一鳍片群组以及该a-Si层形成于在一PFET区域中的一第二鳍片群组上方的一部分；植入离子于该第一鳍片群组的一第一区域中；形成一第三图案化层至少于该第一鳍片群组的该第一区域上方以及暴露该第一鳍片群组的一第二区域；植入离子于该鳍片群组的该第二区域中；形成一第四图案化层至少于该第一鳍片群组的该第二区域上方；移除该第四图案化层以暴露该第一鳍片群组的一第三区域；以及植入离子于该第三鳍片群组的该第三区域中。
本领域技术人员由以下详细说明可明白本揭示内容的其他方面及技术效果，其中系仅以预期可实现本揭示内容的最佳模式举例描述本揭示内容的具体实施例。应了解，本揭示内容能够做出其他及不同的具体实施例，以及在各种明显的方面，能够修改数个细节而不脱离本揭示内容。因此，附图及说明内容本质上应被视为图解说明用而不是用来限定。
符号说明：
101 鳍片
101a-101d 鳍片群组
103 基板
105 氧化物层
107 SiN
109 a-Si层
111 第一图案化层
113 离子
115 第二图案化层
117 离子
119 有向箭头
121 第一区域
123 第二区域
125 第三区域
127 第三图案化层
129 第四图案化层
131 第二氧化物层
133 离子
135 第五图案化层
137 有向箭头
139 第一区域
141 第二区域
143 第三区域
145 第六图案化层
147 第七图案化层
201 掩模
203 鳍片
205 区域
207 NFET区域
209 PFET区域
211 角落
301 掩模
303 鳍片
305 椭圆形区域
307 NFET区域
309 PFET区域
311 角落
313 虚线长方形。
附图说明
在此用附图举例说明而不是限定本揭示内容，图中类似的元件用相同的元件符号表示。
图1A至图1X根据一示范具体实施例示意图示图案化及植入加工流程；
图2图示用现有加工制成NFET区域有植入区的CRR的装置；以及
图3图示用示范具体实施例制成消除植入区的CRR的装置。
具体实施方式
为了解释，在以下的说明中，提出许多特定细节供澈底了解示范具体实施例。不过，显然没有该等特定细节或用等价配置仍可实施示范具体实施例。在其他情况下，众所周知的结构及装置用方块图图示以免不必要地混淆示范具体实施例。此外，除非呈现，在本专利说明书及权利要求书中表示成分、反应状态等等的数量、比例及数值性质的所有数字应被理解为在所有情况下可用措辞“约”来修饰。
本揭示内容针对及解决需要昂贵浸镀层的当前问题，其伴随关键栅极间距的最小面积要求、窄小N-P接面崩溃制程裕度、以及普遍出现于10纳米以下技术节点的半导体加工的关键CRR而来。根据本揭示内容的具体实施例的方法包括：在一基板的多个区域中形成多个鳍片群组；形成一氮化硅(SiN)于该多个鳍片群组上；形成一非晶硅(a-Si)层于该SiN上；形成及图案化一第一图案化层于该a-Si层上；使用该第一图案化层作为一掩模，蚀刻穿过该a-Si层向下到该SiN；移除该第一图案化层；在蚀刻该a-Si层后，植入离子于暴露的鳍片群组中；形成及图案化一第二图案化层以暴露一第一鳍片群组以及该a-Si层在该第一鳍片群组的两对边上的一部分；植入离子于该第一鳍片群组的一第一区域中；形成一第三图案化层于该第一鳍片群组的该第一区域上以及暴露该第一鳍片群组的一第二区域；以及植入离子于该第一鳍片群组的该第二区域中。
此外，本领域技术人员由以下详细说明可明白本揭示内容的其他方面、特征及技术效果，其中系仅以预期可实现本揭示内容的最佳模式举例描述本揭示内容的具体实施例。应了解，本揭示内容能够做出其他及不同的具体实施例，以及在各种明显的方面，能够修改数个细节而不脱离本揭示内容。因此，附图及说明内容本质上应被视为图解说明用而不是用来限定。
参考图1A，多个鳍片101形成于基板103上。已完成用于形成浅沟槽隔离(shallowtrench isolation；STI)区域的步骤，化学机械研磨(chemical mechanical polishing；CMP)、除渣(deglaze)及SiN移除。鳍片101及基板两者可由硅(Si)形成。在个别鳍片101之间形成氧化物层105。如图1A所示，鳍片101分开成多个鳍片群组101a、101b、101c及101d。在图1B中，SiN 107形成于鳍片群组101a、101b、101c及101d和氧化物层105上。SiN 107经形成有5至15纳米的厚度。参考图1C，沉积a-Si层109于SiN 107上且予以平坦化成有100至200纳米的厚度。
参考图1D，在a-Si层109上沉积及图案化第一图案化层111。第一图案化层111为包含SiOC的硅基层。在图1E中，使用第一图案化层111作为掩模，进行蚀刻步骤藉此蚀刻a-Si层109向下到SiN 107。移除第一图案化层111。如图1E所示，形成部分的a-Si层109于鳍片群组101a及101c上。参考图1F，在蚀刻a-Si层109后，植入离子113于暴露的鳍片群组101b及101d中。该离子植入包括：以E12至E13的浓度植入磷(P)或硼(B)离子于鳍片101的源极/漏极区域(为求便于图解说明而不图示)。
参考图1G，形成及图案化第二图案化层115以暴露鳍片群组101b以及a-Si层109在鳍片群组101b的两对边上的一部分。如图1H所示，植入离子117于鳍片群组101b的第一区域121中。如图1I所示，在植入离子117后，移除第二图案化层115。然后，对于鳍片群组101b的第二区域及第三区域，重复图1G、图1H及图1I的制程，如有向箭头119所示。鳍片群组101b的第一区域121、第二区域123及第三区域125各自图示于图1J、图1K及图1L，彼等为鳍片群组101a、101b、101c及101d的上视图。在图1K中，形成第三图案化层127于鳍片群组101b的第一区域121上，以及在移除第二区域123的第三a-Si层后，暴露第一鳍片群组101b的第二区域123。在暴露第二区域123后，第三图案化层127覆盖所有的鳍片群组101a、101b、101c及101d，除第二区域123以外。第二区域123随后经受离子植入以及移除第三图案化层127。第二区域123暴露鳍片群组101b以及a-Si层109在鳍片群组101b的两对边上的一部分。在图1L中，形成第四图案化层129，以及移除它的一部分以暴露第三区域125。第三区域125暴露鳍片群组101b以及a-Si层109在鳍片群组101b的两对边上的一部分。第三区域125随后经受离子植入，以及接着移除第四图案化层129。
参考图1M，毯覆式沉积(blanket deposit)第二氧化物层131于SiN 107层及a-Si层109上。在图1N中，用CMP研磨及平坦化第二氧化物层131。第二氧化物层131向下研磨到a-Si层109的上表面。在图1O中，a-Si层109在研磨第二氧化物层131后移除。在图1P中，植入离子133于鳍片群组101a及101c中。该离子植入包括以E12至E15的浓度植入例如B、砷(As)、锗(Ge)、P等等的离子133于鳍片101的源极/漏极区域(为求便于图解说明而不图示)中。
参考图1Q，形成及图案化第五图案化层135以暴露鳍片群组101c以及第二氧化物层131在鳍片群组101c的两对边上的一部分。在图1R中，植入离子于鳍片群组101c的第一区域139中。在图1S中，在植入离子133后，移除第五图案化层135。
然后对于鳍片群组101c的第二区域及第三区域，重复图1Q、图1R及图1S的制程，如有向箭头137所示。鳍片群组101c的第一区域139、第二区域141及第三区域143各自图示于图1T、图1U及图1V，彼等为鳍片群组101a、101b、101c及101d的上视图。在图1U中，形成第六图案化层145于鳍片群组101c的第一区域139上，以及在移除第二区域141的第六a-Si层后，暴露鳍片群组101c的第二区域141。在暴露第二区域141后，第六图案化层145覆盖所有的鳍片群组101a、101b、101c及101d，除第二区域141以外。第二区域141随后经受离子植入，以及第六图案化层145在离子植入后移除。第二区域141暴露鳍片群组101c以及第二氧化物层131在鳍片群组101c的两对边上的一部分。在图1V中，形成第七图案化层147，以及移除它的一部分以暴露第三区域143。第三区域143暴露鳍片群组101c以及第二氧化物层131在鳍片群组101c的两对边上的一部分。第三区域143随后经受离子植入，以及接着在离子植入后移除第七图案化层147。
参考图1W，第二氧化物层131被移除使得SiN层107留下。然后，移除图1X的SiN107。
图2图示用现有制程制成的装置。掩模201形成于在底下(underlying)鳍片203上。图案化掩模201以暴露在区域205中的底下鳍片203。图案化在NFET区域207中的区域205以及用现有加工无法延伸到在NFET区域207两侧上的PFET区域209。因此，p向CD(用双向箭头表示)受限于NFET p宽度。此外，在现有加工下，各角落211都存在CRR。
图3图示根据示范具体实施例制成的装置。掩模301形成于在底下鳍片303上。图案化掩模301以暴露在椭圆形(oval-shaped)区域305中的底下鳍片303。图案化在NFET区域307中的椭圆形区域305以及根据本揭示内容可延伸到在NFET区域307两侧的PFET区域309。因此，p向CD(用双向箭头表示)不受限于NFET p宽度，反而使p向CD大小倍增甚至合并。此外，根据本揭示内容，可消除在虚线长方形313的四个角落311的CRR。所使用的光刻设备可包括准分子激光***，例如ArFi准分子激光***、氟化氩(ArF)及氟化氪(KrF)。这些准分子激光***的成本低于浸镀层加工设备。
本揭示内容的具体实施例可实现数种技术效果，包括最小面积恢复与CRR恢复。本揭示内容的具体实施例可实现降低成本，其通过减少用来加工半导体装置的掩模数，以及用比较便宜的光刻制程取代较贵的多层浸镀制程。本揭示内容在产业上可用于各种工业应用，例如，微处理器、智能手机、移动电话、手机、机顶盒、DVD烧录机及播放机、汽车导航、打印机及周边设备，网络及电信设备，游戏***及数字相机。本揭示内容因此在产业上可用于各种高度整合半导体装置，特别是应用于10纳米以下技术节点。
在以上说明中，特别用多个示范具体实施例描述本揭示内容。不过，显然仍可做出各种修改及改变而不脱离本揭示内容更宽广的精神及范畴，如权利要求书所述。因此，本专利说明书及附图应被视为图解说明用而非限定。应了解，本揭示内容能够使用各种其他组合及具体实施例以及在如本文所述的本发明概念范畴内能够做出任何改变或修改。

Claims (20)

1.一种方法，其包含：
在一基板上方的多个区域中形成多个鳍片群组；
形成一氮化硅(SiN)于该多个鳍片群组上方；
形成一非晶硅(a-Si)层于该SiN上方；
形成及图案化一第一图案化层于该a-Si层上方；
使用该第一图案化层作为一掩模，蚀刻穿过该a-Si层向下到该SiN；
移除该第一图案化层；
在蚀刻该a-Si层后，植入离子于暴露的鳍片群组中；
形成及图案化一第二图案化层以暴露一第一鳍片群组以及该a-Si层在该第一鳍片群组的两对边上的一部分；
植入离子于该第一鳍片群组的一第一区域中；
形成一第三图案化层于该第一鳍片群组的该第一区域上方以及暴露该第一鳍片群组的一第二区域；以及
植入离子于该第一鳍片群组的该第二区域中。
2.如权利要求1所述的方法，更包含：
形成一氧化物层于个别鳍片之间以及于该多个鳍片群组之间且形成该SiN于该氧化物层上方。
3.如权利要求2所述的方法，更包含：
形成一第四图案化层至少于该第一鳍片群组的该第二区域上方。
4.如权利要求3所述的方法，更包含：
移除该第四图案化层以暴露该第一鳍片群组的一第三区域。
5.如权利要求4所述的方法，更包含：
植入离子于该第一鳍片群组的该第三区域中。
6.如权利要求5所述的方法，更包含：
沉积一第二氧化物层于该SiN及一a-Si层上方。
7.如权利要求6所述的方法，更包含：
平坦化该第二氧化物层向下到该a-Si层的一上表面。
8.如权利要求7所述的方法，更包含：
在平坦化该第二氧化物层后，移除该a-Si层。
9.如权利要求8所述的方法，更包含：
在移除该a-Si层后，植入离子于暴露的第二鳍片群组中。
10.如权利要求8所述的方法，更包含：
形成及图案化一第五图案化层以暴露该第二鳍片群组以及该第二氧化物层在该第二鳍片群组的两对边上的一部分。
11.如权利要求10所述的方法，更包含：
植入离子于该第二鳍片群组的一第一区域中。
12.如权利要求11所述的方法，更包含：
形成一第六图案化层于该第二鳍片群组的该第一区域上方以及暴露该第二鳍片群组的一第二区域。
13.如权利要求12所述的方法，更包含：
植入离子于该第二鳍片群组的该第二区域中。
14.如权利要求13所述的方法，更包含：
形成一第七图案化层于该第二鳍片群组的该第二区域上方以及暴露该第二鳍片群组的一第三区域。
15.如权利要求14所述的方法，更包含：
移除该第七图案化层；
移除该第二氧化物层；以及
移除该SiN。
16.一种方法，其包含：
在一基板上方的多个区域中形成多个鳍片群组；
形成一氮化硅(SiN)于该多个鳍片群组上方；
形成一非晶硅(a-Si)于该SiN上方；
形成及图案化一第一图案化层于该a-Si层上方；
使用该第一图案化层作为一掩模，蚀刻穿过该a-Si层向下到该SiN；
移除该第一图案化层；
在蚀刻该a-Si层后，植入离子于暴露的鳍片群组中；
形成及图案化一第二图案化层以暴露在一NFET区域中的一第一鳍片群组以及该a-Si层形成于在一PFET区域中的一第二鳍片群组上方的一部分；
植入离子于该第一鳍片群组的一第一区域中；
形成一第三图案化层至少于该第一鳍片群组的该第一区域上方以及暴露该第一鳍片群组的一第二区域；以及
植入离子于该第一鳍片群组的该第二区域中。
17.如权利要求16所述的方法，更包含：
形成一第四图案化层至少于该第一鳍片群组的该第二区域上方以及暴露该第一鳍片群组的一第三区域；以及
植入离子于该第一鳍片群组的该第三区域中。
18.如权利要求17所述的方法，更包含：
沉积一氧化物层于该SiN及一a-Si层上方；
平坦化该氧化物层向下到该a-Si层的一上表面；
移除该a-Si层；以及
在移除该a-Si层后，植入离子于暴露的鳍片群组中。
19.如权利要求18所述的方法，更包含：
形成及图案化一第五图案化层以暴露在该PFET区域中的该第二鳍片群组以及该氧化物层在一第二NFET区域中的一部分；
植入离子于该第二鳍片群组的一第一区域中；
形成一第六图案化层至少于该第二鳍片群组的该第一区域上方以及暴露该第二鳍片群组的一第二区域；
植入离子于该第二鳍片群组的该第二区域中；
形成一第七图案化层至少于该第二鳍片群组的该第二区域上方以及暴露该第二鳍片群组的一第三区域；
移除该第七a-Si层；
移除该氧化物层；以及
移除该SiN。
20.一种方法，其包含：
在一基板上方的多个区域中形成多个鳍片群组，其中，形成一氧化物层于个别鳍片之间以及于该多个鳍片群组之间；
形成一氮化硅(SiN)于该氧化物层上方；
形成一非晶硅(a-Si)层于该SiN上方；
形成及图案化一第一图案化层于该a-Si层上方；
使用该第一图案化层作为一掩模，蚀刻穿过该a-Si层向下到该SiN；
移除该第一图案化层；
在蚀刻该a-Si层后，植入离子于暴露的鳍片群组中；
形成及图案化一第二图案化层以暴露在一NFET区域中的一第一鳍片群组以及该a-Si层形成于在一PFET区域中的一第二鳍片群组上方的一部分；
植入离子于该第一鳍片群组的一第一区域中；
形成一第三图案化层至少于该第一鳍片群组的该第一区域上方以及暴露该第一鳍片群组的一第二区域；
植入离子于该鳍片群组的该第二区域中；
形成一第四图案化层至少于该第一鳍片群组的该第二区域上方；
移除该第四图案化层以暴露该第一鳍片群组的一第三区域；以及
植入离子于该第三鳍片群组的该第三区域中。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110556426A (zh) * 2018-05-30 2019-12-10 格芯公司 改良的鳍式场效晶体管(FinFET)及其制造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102017127276A1 (de) * 2017-08-30 2019-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Standardzellen und abwandlungen davon innerhalb einer standardzellenbibliothek

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63308385A (ja) * 1987-06-10 1988-12-15 Fuji Electric Co Ltd 埋込みゲ−ト型電界効果トランジスタの製造方法
JPH1117024A (ja) * 1997-06-25 1999-01-22 Sony Corp 半導体装置の製造方法
CN101866923A (zh) * 2010-05-18 2010-10-20 苏州硅能半导体科技股份有限公司 三层光罩沟槽mos器件及制造方法
CN102130008A (zh) * 2010-01-19 2011-07-20 台湾积体电路制造股份有限公司 半导体元件的制造方法
CN102487011A (zh) * 2010-12-03 2012-06-06 上海华虹Nec电子有限公司 横向扩散金-氧-半场效应器件的低压倒置阱注入方法
US20140113420A1 (en) * 2012-10-24 2014-04-24 Globalfoundries Inc. Methods of avoiding shadowing when forming source/drain implant regions on 3d semiconductor devices
US20140138773A1 (en) * 2012-11-20 2014-05-22 International Business Machines Corporation Dense finfet sram
CN104752205A (zh) * 2013-12-27 2015-07-01 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
CN105161458A (zh) * 2015-08-17 2015-12-16 武汉华星光电技术有限公司 Tft基板的制作方法
US20150371904A1 (en) * 2014-05-20 2015-12-24 International Business Machines Corporation Patterning process for fin implantation

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9312191B2 (en) * 2014-08-14 2016-04-12 Globalfoundries Inc. Block patterning process for post fin
US9673083B2 (en) * 2015-01-29 2017-06-06 Globalfoundries Inc. Methods of forming fin isolation regions on FinFET semiconductor devices by implantation of an oxidation-retarding material

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63308385A (ja) * 1987-06-10 1988-12-15 Fuji Electric Co Ltd 埋込みゲ−ト型電界効果トランジスタの製造方法
JPH1117024A (ja) * 1997-06-25 1999-01-22 Sony Corp 半導体装置の製造方法
CN102130008A (zh) * 2010-01-19 2011-07-20 台湾积体电路制造股份有限公司 半导体元件的制造方法
CN101866923A (zh) * 2010-05-18 2010-10-20 苏州硅能半导体科技股份有限公司 三层光罩沟槽mos器件及制造方法
CN102487011A (zh) * 2010-12-03 2012-06-06 上海华虹Nec电子有限公司 横向扩散金-氧-半场效应器件的低压倒置阱注入方法
US20140113420A1 (en) * 2012-10-24 2014-04-24 Globalfoundries Inc. Methods of avoiding shadowing when forming source/drain implant regions on 3d semiconductor devices
US20140138773A1 (en) * 2012-11-20 2014-05-22 International Business Machines Corporation Dense finfet sram
US20150200107A1 (en) * 2012-11-20 2015-07-16 International Business Machines Corporation Dense finfet sram
CN104752205A (zh) * 2013-12-27 2015-07-01 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US20150371904A1 (en) * 2014-05-20 2015-12-24 International Business Machines Corporation Patterning process for fin implantation
CN105161458A (zh) * 2015-08-17 2015-12-16 武汉华星光电技术有限公司 Tft基板的制作方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110556426A (zh) * 2018-05-30 2019-12-10 格芯公司 改良的鳍式场效晶体管(FinFET)及其制造方法
CN110556426B (zh) * 2018-05-30 2023-08-29 格芯(美国)集成电路科技有限公司 改良的鳍式场效晶体管(FinFET)及其制造方法

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