CN107452676A - A kind of embolism forming method and the semiconductor devices with the embolism - Google Patents
A kind of embolism forming method and the semiconductor devices with the embolism Download PDFInfo
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- CN107452676A CN107452676A CN201710640184.1A CN201710640184A CN107452676A CN 107452676 A CN107452676 A CN 107452676A CN 201710640184 A CN201710640184 A CN 201710640184A CN 107452676 A CN107452676 A CN 107452676A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
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Abstract
The present invention relates to a kind of embolism forming method and with the embolism semiconductor devices.Wherein, embolism forming method, including：Substrate is provided, dielectric layer is formed in substrate surface, hole is formed on dielectric layer；Bore at the openend of expanded hole hole；The first conductive layer is formed on dielectric layer surface, it includes being locally filled with the embolism portion in hole；Space, certain media layer and the conductive layer of part first are removed, exposes the conductive plug of flush.Semiconductor devices, dielectric layer is set in substrate surface, dielectric layer has hole；Electric embolism is filled in hole, the flush of conductive plug and is exposed to dielectric layer, and conductive plug is solid surfaces.The conductive plug that the inventive method is formed has that tight, resistance be low, high reliability.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of embolism forming method and the semiconductor with the embolism
Device.
Background technology
At present, in semiconductor storage device assembly, generally use forms the mode of embolism structure between the two metal layers
Realize the electrical connection between two metal levels.Because tungsten has good stepcoverage and gap filling performance, therefore often adopt
Embolism is formed with the mode of chemical vapor deposition tungsten.
The formation quality of embolism is very big to the performance impact of device, if embolism formed it is second-rate, can cause interconnection electricity
Resistance increase, influence the performance of device.However, with the continuous diminution of process node, the depth of the hole opening for forming embolism
Width improves than also corresponding, therefore easily causes to be difficult to, even into hole bottom, easily exist by the tungsten of chemical vapor deposition
The sidewall surfaces of hole opening form accumulation, cause to deposit to the tungsten in hole when not being filled up completely with full hole just in opening
Closure too early, and then the embolism to be formed is internally formed space, so as to cause formed embolism performance bad.Further,
When removing unnecessary tungsten metal subsequently through cmp or etching technics, the cavity or gap in embolism can be caused
Exposed to outer, there are void defects in the embolism resulted in, influence the reliability that device subsequently connects.In the prior art,
Frequently with chemical vapor deposition processes reduce temperature, regulation the parameter such as pressure and air-flow come reduce cavity or gap production
It is raw, but the tungsten plug too high in resistance of generation, the conducting being unfavorable between metal level are deposited under such circumstances.
Disclosed above- mentioned information is only used for strengthening the understanding of the background to the present invention in the introduction, therefore it may be wrapped
Containing the information for not being formed as the prior art that those of ordinary skill in the art are known.
The content of the invention
In view of this, the embodiment of the present application desirable to provide a kind of embolism forming method and with the embolism semiconductor device
Part, at least to solve problems of the prior art.
The technical scheme of the embodiment of the present application is achieved in that one embodiment according to the application, there is provided Yi Zhongshuan
Forming method is filled in, including：
Semiconductor substrate is provided, dielectric layer is formed in the substrate surface, is formed on the dielectric layer described in being communicated to
The hole of substrate surface, the dielectric layer include a retaining layer portion and a sacrifice layer portion；
Expand the bore at the openend of described hole, to reduce depth-to-width ratio of the described hole at the openend, institute
State and reaming inclined-plane is formed at the openend of hole, the depth on the reaming inclined-plane is less than the thickness in the sacrifice layer portion；
Form the first conductive layer includes embolism portion in the upper surface , And of the dielectric layer and first conductive layer, filling
In described hole, there is space in the embolism portion, the space extends along described hole length direction, under the space
End is no more than the thickness definition scope in the sacrifice layer portion, and the upper end in the space is no more than the shape of first conductive layer
Into surface；
The sacrifice layer portion is removed, to remove the space and part first conductive layer simultaneously, until exposing table
Thickness definition scope of the concordant conductive plug in face in the retaining layer portion.
In certain embodiments, the technique for expanding the bore at the openend is using sputtering technology or grey chemical industry in situ
Skill, the reaming inclined-plane is formed the first chamfering relative to the upper surface of the dielectric layer, and then expand the mouth of the openend
Footpath.
In certain embodiments, in addition to：Before first conductive layer is formed, deposition barrier layer is in the dielectric layer
Upper surface and described hole bottom and side wall, so that first conductive layer and the embolism portion are on the barrier layer
Deposition is formed.
In certain embodiments, the material on the barrier layer is selected from one of tungsten nitride, titanium and titanium nitride.
In certain embodiments, in addition to：Before the barrier layer is formed, by deposition and annealing process in the hole
The substrate surface that hole bottom-exposed goes out forms the second conductive layer, so that the barrier layer is formed；Second conductive layer
Material is selected from one of titanium silicide, zirconium silicide, tantalum silicide, cobalt silicide and nickle silicide.
In certain embodiments, in addition to：Wet clean process is carried out after second conductive layer is formed, is removed attached
In second conductive layer, described hole madial wall and the surface impurity of the openend.
In certain embodiments, first conductive layer is formed in the dielectric layer surface by chemical vapor deposition method
Be filled in described hole.
In certain embodiments, the material of the dielectric layer is selected from oxide；The material of first conductive layer is selected from
In one of tungsten, copper, aluminium or polysilicon.
In certain embodiments, first conduction on the dielectric layer surface is removed using chemical mechanical milling tech
Layer and the sacrifice layer portion.
A kind of semiconductor devices with embolism, including：
Semi-conductive substrate；
One dielectric layer, is formed at the surface of the substrate, and the dielectric layer has the hole for being communicated to the substrate surface
And first tabular surface, the opening of described hole are exposed to first tabular surface；And conductive plug, it is filled in described hole
In, the conductive plug is the homogeneous solid being made up of the first conductive layer, and the conductive plug has the second tabular surface, described
Second tabular surface is that second tabular surface is with first tabular surface same without being recessed and filling up the opening of described hole
One plane.
In certain embodiments, it is provided with barrier layer between described hole surface and the conductive plug.
In certain embodiments, it is provided between the barrier layer of described hole bottom and described hole lower surface
Second conductive layer.
In certain embodiments, the material of first conductive layer is tungsten.
In certain embodiments, the barrier layer has rim, is revealed in the opening of described hole and described
Between first tabular surface and second tabular surface, second tabular surface is formed via the rim and first tabular surface
In a continuous surface.
For the present invention due to using above technical scheme, it has advantages below：1st, the present invention is due to changing hole opening
Caliber size and shape at end, the depth-to-width ratio of hole is reduced, hence in so that the material of the first conductive layer of subsequent deposition is easy
In entering inside hole, make the conductive plug inner homogeneous to be formed fine and close, and due at open end parallel to substrate table
The dimension enlargement in face direction so that the material of the first conductive layer is not susceptible to accumulate in the sidewall surfaces close to openend, is open
End also will not be too early generation closed-ended question, so as to suppress formed the first conductive layer in produce larger space, make
Obtain the first formed conductive layer dense uniform, electric performance stablity.2nd, because the openend of hole is extended, therefore in openend
The time lengthening of packing phenomenon is formed, the material for the first conductive layer being filled into hole is more, and then to be deposited in opening
Position of the material of first conductive layer at end when closing moves up, i.e., moves on to openend upper end on the position that space is formed,
Part exceeds dielectric layer surface, therefore can remove less dielectric layer and first in follow-up chemical mechanical planarization process and lead
Electric layer saves cost and improves production efficiency so as to form the conductive plug of flush.3rd, due to the conductive plugs of the present invention
Space is not contained in plug, therefore the low resistance of the first conductive layer can be kept, contact resistance is reduced and increases read/write speed, together
When reduce chemical vapor deposition temperature, pressure and flow.4th, the conductive plug that the inventive method is formed has tight, resistance
Low, high reliability.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to is limited in any way.Except foregoing description
Schematical aspect, outside embodiment and feature, it is further by reference to accompanying drawing and the following detailed description, the present invention
Aspect, embodiment and feature would is that what is be readily apparent that.
Brief description of the drawings
In the accompanying drawings, unless specified otherwise herein, otherwise represent same or analogous through multiple accompanying drawing identical references
Part or element.What these accompanying drawings were not necessarily to scale.It should be understood that these accompanying drawings depict only according to the present invention
Some disclosed embodiments, and should not serve to limit the scope of the present invention.
Fig. 1 is the flow chart of the embolism forming method of the present invention；
Fig. 2 is the structural representation that dielectric layer is formed on substrate of the present invention；
Fig. 3 is the structural representation of the chamfering of the hole openend of the present invention；
Fig. 4 is the structural representation of the first conductive layer deposition of the present invention；
Fig. 5 is the structural representation of the conductive plug of the present invention；
Fig. 6 is the deposition process schematic diagram of the second conductive layer of the present invention；
Fig. 7 is the structural representation of the second conductive layer deposition of the present invention；
Fig. 8 is the structural representation of the barrier deposition of the present invention；
Fig. 9 is the structural representation of the semiconductor devices of the present invention.
Reference：
1- substrates；2- dielectric layers；21- retaining layers portion；22- sacrifice layers portion；The tabular surfaces of 23- first；3- holes；31- is open
End；The conductive layers of 4- first；41- embolisms portion；42- spaces；The bottom in 43- spaces；The upper end in 44- spaces；5- conductive plugs；
The tabular surfaces of 51- second；6- barrier layers；The conductive layers of 7- second.
Embodiment
Hereinafter, some exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present invention, described embodiment can be changed by various different modes.
Therefore, accompanying drawing and description are considered essentially illustrative rather than restrictive.
In the description of the invention, it is to be understood that term " center ", " longitudinal direction ", " transverse direction ", " length ", " width
Degree ", " thickness ", " go up ", " under ", " preceding ", " afterwards ", " left side ", " right side ", " heavily fortified point, and directly ", " level ", " top ", " bottom ", " is interior ", " outside ", "
Clockwise the orientation of the instruction such as ", " counterclockwise " or position relationship be based on orientation shown in the drawings or position relationship, merely to
Be easy to the description present invention and simplify description, rather than instruction or imply signified device or element must have specific orientation,
With specific azimuth configuration and operation, therefore it is not considered as limiting the invention.In addition, term " first ", " second " are only
For descriptive purposes, and it is not intended that instruction or hint relative importance or the implicit number for indicating indicated technical characteristic
Amount.Thus, " first " is defined, the feature of " second " can be expressed or implicitly includes one or more spy
Sign.In the description of the invention, " multiple " are meant that two or more, unless otherwise specifically defined.
In the description of the invention, it is necessary to illustrate, unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected, or be integrally connected:Can
To be mechanical connection or electrical connection or can mutually communicate；Can be joined directly together, can also be by between intermediary
Connect connected, can be connection or the interaction relationship of two elements of two element internals.For the ordinary skill of this area
For personnel, the concrete meaning of above-mentioned term in the present invention can be understood as the case may be.
In the present invention, unless otherwise clearly defined and limited, fisrt feature second feature its " upper " or it " under "
Can directly it be contacted including the first and second features, it is not directly to contact but pass through it that can also include the first and second features
Between other characterisation contact.Moreover, fisrt feature second feature " on ", " top " and " above " include first spy
Sign is directly over second feature and oblique upper, or is merely representative of fisrt feature level height and is higher than second feature.Fisrt feature exists
Second feature " under ", " lower section " and it is " following " including fisrt feature directly over second feature and oblique upper, or be merely representative of
Fisrt feature level height is less than second feature.
Following disclosure provides many different embodiments or example is used for realizing the different structure of the present invention.In order to
Simplify disclosure of the invention, hereinafter the part and setting of specific examples are described.Certainly, they are only example, and
And purpose does not lie in the limitation present invention.In addition, the present invention can in different examples repeat reference numerals and/or reference letter,
This repetition is for purposes of simplicity and clarity, between itself not indicating discussed various embodiments and/or setting
Relation.In addition, the invention provides various specific techniques and material examples, but those of ordinary skill in the art can be with
Recognize the application of other techniques and/or the use of other materials.
As shown in figure 1, present embodiments providing a kind of embolism forming method, following steps are specifically included：
Semiconductor substrate 1 is provided, dielectric layer 2 is formed on the surface of Semiconductor substrate 1, connection substrate 1 is formed on dielectric layer 2
The hole 3 (as shown in Figure 2) of upper surface, dielectric layer 2 include retaining layer portion 21 and sacrifice layer portion 22；Wherein, retaining layer portion 21 is
The bottom of dielectric layer 2, sacrifice layer portion 22 are the top of dielectric layer 2, and retaining layer portion 21 and sacrifice layer portion 22 collectively form dielectric layer 2, and
Both are the body of dielectric layer 2 and non-physical visible layer, for the ease of difference description so that the top of dielectric layer 2 be needed to be removed portion
Divide and be named as sacrifice layer portion 22, and it is retaining layer portion 21 that dielectric layer 2 is not removed into part names.
Expand the bore at the openend 31 of hole 3, increase opening size, and the caliber size inside hole 3 is constant, with
Reduce depth-to-width ratio of the hole 3 at openend 31, form reaming inclined-plane (as shown in Figure 3) at the openend 31 of hole 3, reaming is oblique
The depth in face is less than the thickness in sacrifice layer portion 22；
As shown in figure 4, form the first conductive layer 4 includes embolism portion in the upper surface , And of dielectric layer 2 and the first conductive layer 4
41, embolism portion 41 is filled in hole 3, has space 42 in embolism portion 41, and space 42 extends along the length direction of hole 3, space
42 bottom 43 is no more than the thickness definition scope in sacrifice layer portion 22, and the upper end 44 in space 42 is no more than the first conductive layer 4
Formation surface；
As shown in figure 5, sacrifice layer portion 22 is removed, to remove space 42 and the first conductive layer of part 4 simultaneously, until exposing
Thickness definition scope of the conductive plug 5 of flush in retaining layer portion 21.
In certain embodiments, the technique of the bore at enlarged openings end 31 can use sputtering technology or grey chemical industry in situ
Skill, reaming inclined-plane is set to form the first chamfering (as shown in Figure 3), and then enlarged openings by bombardment relative to the upper surface of dielectric layer 2
The bore at end 31, is easy to the material of the first conductive layer 4 of subsequent deposition to be easy to enter inside hole 3, makes the conductive plugs to be formed
The densification of 5 inner homogeneous is filled in, and due to the dimension enlargement at open end 31 parallel to substrate surface direction, even if first is conductive
The material of layer 4 is accumulated in the sidewall surfaces close to openend 31, the generation closed-ended question that openend 31 also will not be too early, from
And it can suppress to produce larger space in formed the first conductive layer 4.So that the first conductive layer dense uniform formed,
Electric performance stablity.
In a preferred embodiment, the expansion of openend 31 is realized using argon sputtering technology.It should be noted that open
The change method at mouth end 31 is not limited to mode mentioned above, any-mode of the prior art can be used, as long as can realize
The change of the shape and size of openend 31.
In a preferred embodiment, the angular range of the first chamfering is between 30 °~70 °, preferably 45 °, this angle
The gradient of first chamfering of degree is moderate, it is possible to increase the material deposition velocity of the first conductive layer 4 during deposition, and will not be because of stream
Dynamic excessive velocities cause the first conductive layer 4 of opening to be accumulated, too early closure opening.
In another preferred embodiment, the first chamfering can be fillet, deposit the first conductive layer 4 more smooth.
In certain embodiments, the surface of dielectric layer 2 around openend 31 forms the second chamfering (not shown), the
Two chamfer angles are not more than the angle of the first chamfering, make 4 more smooth filling hole of the first conductive layer.
It should be noted that when 31 too small openings of openend of the hole 3 on substrate 1, first in openend 31 falls
Angle it is circumferential by sputtering technology or cineration technics in situ, bombard the surface of dielectric layer 2 of the first chamfering dimension, formed and the
Second chamfering of one chamfering connection, preferable second chamfer angle is equal with the first chamfer angle, so as to form smooth guiding
Structure, the bore of the openend 31 of hole 3 is further expanded, the material deposition speed of the first conductive layer 4 when improving deposition
Degree, prevents material stacking openend 31 from closing too early.
In certain embodiments, before the first conductive layer 4 is formed, deposition barrier layer 6 is in the upper surface of dielectric layer 2 and hole
The bottom in hole 3 and side wall, so that the deposition of the first conductive layer 4 and embolism portion 41 on barrier layer 6 forms (as shown in Figure 7).Need
It is noted that the material on barrier layer 6 is selected from tungsten nitride, one or more combinations in titanium or titanium nitride.Barrier layer 6 is used for
Stop that the material of the first conductive layer 4 spreads into substrate 1 and dielectric layer 2, while can also play and more preferably be connect with the first conductive layer 4
The purpose of conjunction, prevent the generation peeled off.
In a preferred embodiment, the material of the first conductive layer 4 is selected from tungsten, now the He of the first conductive layer 4
Zygosity between barrier layer 6 is good.It should be noted that barrier layer 6 is by chemical vapor deposition technique, gas phase physical deposition
Technique or ald are formed on the surface of hole 3 and the surface of dielectric layer 2.
In certain embodiments, before barrier layer 6 is formed, the formation material of deposit second conductive layer 7 is in dielectric layer 2
The bottom and side wall (as shown in Figure 6) of upper surface and hole 3, and gone out by depositing with annealing process in the bottom-exposed of hole 3
The surface of substrate 1 forms the second conductive layer 7 (as shown in Figure 7), so that barrier layer forms 6 (as shown in Figure 8)；Second conductive layer 7
Material is selected from one of titanium silicide, zirconium silicide, tantalum silicide, cobalt silicide and nickle silicide.
Wherein, the forming process of the second conductive layer 7 is：After the caliber size of the openend 31 of hole 3 changes, in hole
At 3 openend 31 Co, CoSi and Co are deposited to the inwall of hole 32Si combination material, annealing process, group are carried out after deposition
The layer component that compound material forms the bottom for being deposited on hole 3 by reacting is CoSi2The second conductive layer 7.
In certain embodiments, wet clean process is carried out after the second conductive layer 7 is formed, removal is attached to second and led
The surface impurity of electric layer 7, the madial wall of hole 3 and openend 31, makes that the surface of above-mentioned three is smoother, and pattern is more excellent, avoids
Influence the performance of conductive plug eventually formed.Wherein, the cleaning liquid level acidic cleaning solution that wet clean process is used.
In certain embodiments, the first conductive layer 4 is formed in the surface of dielectric layer 2 and filling by chemical vapor deposition method
In hole 3.The material of first conductive layer 4 is selected from one of tungsten, copper, aluminium or polysilicon.
In certain embodiments, the first conductive layer 4 on dielectric layer 2 surface and sacrificial is removed using chemical mechanical milling tech
Domestic animal layer portion 22.
In certain embodiments, the material of dielectric layer 2 is selected from oxide, is chosen in particular from silica, silicon nitride or nitrogen
One or more combinations in silica.
In certain embodiments, dielectric layer 2 is formed on the surface of substrate 1 by depositing operation；Hole 3 passes through etching technics shape
Into in dielectric layer 2.Specifically, the formation process of dielectric layer 2 is chemical vapor deposition method or physical gas-phase deposition；Hole
The formation process in hole 3 is anisotropic dry etch process.
In certain embodiments, substrate 1 includes semiconductor base, is formed in semiconductor substrate surface or semiconductor base
Semiconductor devices, the conductive structure for electrically connecting semiconductor devices and for being electrically isolated semiconductor devices and conductive knot
The insulating barrier of structure.Semiconductor base includes silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator substrate, germanium on insulator
Substrate, glass substrate.Semiconductor devices includes transistor, and the first conductive layer 4 electrically connects with transistor, realizes read/write function.
Illustrate the embolism forming method in the present invention below by a preferred embodiment.
Embodiment
A kind of embolism forming method, comprises the following steps：
1) Semiconductor substrate 1 is provided, dielectric layer 2 is formed by chemical vapor deposition method on the surface of substrate 1, in dielectric layer
The hole 3 for exposing the upper surface of substrate 1 is formed on 2 by anisotropic dry etch process；
2) bore at the openend 31 of hole 3, relative reduction hole are expanded using sputtering technology or cineration technics in situ
The depth-to-width ratio in hole 3；
3) Co, CoSi and Co are deposited to the inside of hole 3 at the openend 31 of hole 32Si combination material；
4) annealing process is carried out after depositing, combination material forms a layer component of the bottom for being deposited on hole 3 by reacting
For CoSi2The second conductive layer 7；
5) wet clean process is carried out after the second conductive layer 7 is formed, removal is attached to the second conductive layer 7, in hole 3
Side wall and the surface impurity of openend 31；
6) barrier layer 6 is deposited in the side wall of hole 3 and the upper surface of the second conductive layer 7；
7) form the first conductive layer 4 in the upper surface of dielectric layer 2, the first conductive layer 4 include being locally filled with hole 3 and
Embolism portion 41 with space 42, space 42 are located at the top in embolism portion 41, and space 42 is elongate and along the length side of hole 3
To extension, the bottom 43 in space 42 is located at openend 31, and the upper end 44 in space 42 is located at the table beyond dielectric layer 2
Face opening position；
8) space 42, certain media layer 2 and the first conductive layer of part 4 are removed using chemical mechanical milling tech, until energy
Enough expose the conductive plug 5 electrically isolated of flush.
As shown in figure 9, a kind of semiconductor devices with embolism is present embodiments provided, including：
Semi-conductive substrate 1；
One dielectric layer 2, is formed at the surface of substrate 1, and dielectric layer 2 has the hole 3 and first for being communicated to the surface of substrate 1
Tabular surface 23, the opening of hole 3 are exposed to the first tabular surface 23；And conductive plug 5, it is filled in hole 3, conductive plug 5 is
The homogeneous solid being made up of the first conductive layer 4, conductive plug 5 have the second tabular surface 51, and the second tabular surface 51 is without depression
And the opening of hole is filled up, the second tabular surface 51 and the first tabular surface 23 are in same plane.
In certain embodiments, barrier layer 6 is provided between the surface of hole 3 and conductive plug 5.
In certain embodiments, it is conductive that second is provided between the barrier layer 6 of the bottom of hole 3 and the lower surface of hole 3
Layer 7.
In certain embodiments, barrier layer 6 has rim, be revealed in the opening of hole 3 and the first tabular surface 23 with
Between second tabular surface 51, the second tabular surface 51 is formed in a continuous surface via rim and the first tabular surface 23.I.e. first
Tabular surface 23, the second tabular surface 51 and rim three are in the same plane.
In certain embodiments, the technique of the bore at enlarged openings end 31 can use sputtering technology or grey chemical industry in situ
Skill, reaming inclined-plane is set to form the first chamfering (as shown in Figure 3), and then enlarged openings by bombardment relative to the upper surface of dielectric layer 2
The bore at end 31, is easy to the material of the first conductive layer 4 of subsequent deposition to be easy to enter inside hole 3, makes the conductive plugs to be formed
The densification of 5 inner homogeneous is filled in, and due to the dimension enlargement at open end 31 parallel to substrate surface direction, even if first is conductive
The material of layer 4 is accumulated in the sidewall surfaces close to openend 31, the generation closed-ended question that openend 31 also will not be too early, from
And it can suppress to produce larger space in formed the first conductive layer 4.So that the first conductive layer dense uniform formed,
Electric performance stablity.
In a preferred embodiment, the angular range of the first chamfering is between 30 °~70 °, preferably 45 °, this angle
The gradient of first chamfering of degree is moderate, it is possible to increase the material deposition velocity of the first conductive layer 4 during deposition, and will not be because of stream
Dynamic excessive velocities cause the first conductive layer 4 of opening to be accumulated, too early closure opening.
In another preferred embodiment, the first chamfering can be fillet, deposit the first conductive layer 4 more smooth.
In certain embodiments, the surface of dielectric layer 2 around openend 31 forms the second chamfering (not shown), the
Two chamfer angles are not more than the angle of the first chamfering, make 4 more smooth filling hole of the first conductive layer.
It should be noted that when 31 too small openings of openend of the hole 3 on substrate 1, first in openend 31 falls
Angle it is circumferential by sputtering technology or cineration technics in situ, bombard the surface of dielectric layer 2 of the first chamfering dimension, formed and the
Second chamfering of one chamfering connection, preferable second chamfer angle is equal with the first chamfer angle, so as to form smooth guiding
Structure, the bore of the openend 31 of hole 3 is further expanded, the material deposition speed of the first conductive layer 4 when improving deposition
Degree, prevents material stacking openend 31 from closing too early.
In certain embodiments, the material on barrier layer 6 is selected from tungsten nitride, one or more groups in titanium or titanium nitride
Close.Barrier layer 6 is used to stop that the material of the first conductive layer 4 spreads into substrate 1 and dielectric layer 2, while can also play and the
The purpose that one conductive layer 4 more preferably engages, prevent the generation peeled off.
In a preferred embodiment, the material on barrier layer 6 is selected from titanium, and the material of the first conductive layer 4 is selected from tungsten,
Zygosity now between the first conductive layer 4 and barrier layer 6 is good.
It should be noted that barrier layer 6 is by chemical vapor deposition technique, gas phase physical deposition process or atomic layer deposition
Product is formed on the surface on the surface of hole 3 and with dielectric layer 2.
In certain embodiments, the second conductive layer 7, barrier layer 6 are formed in the bottom of hole 3 with annealing process by depositing
Formed on the surface of the second conductive layer 7；The material of second conductive layer 7 is selected from titanium silicide, zirconium silicide, tantalum silicide, cobalt silicide and silicon
Change one of nickel.
In certain embodiments, the first conductive layer 4 is formed in the surface of dielectric layer 2 and filling by chemical vapor deposition method
In hole 3.
In certain embodiments, the material of the first conductive layer 4 is selected from tungsten.
In certain embodiments, the material of dielectric layer 2 is selected from oxide, is chosen in particular from silica, silicon nitride or nitrogen
One or more combinations in silica.
In certain embodiments, dielectric layer 2 is formed on the surface of substrate 1 by depositing operation；Hole 3 passes through etching technics shape
Into in dielectric layer 2.Specifically, the formation process of dielectric layer 2 is chemical vapor deposition method or physical gas-phase deposition；Hole
The formation process in hole 3 is anisotropic dry etch process.
In certain embodiments, substrate 1 includes semiconductor base, is formed in semiconductor substrate surface or semiconductor base
Semiconductor devices, the conductive structure for electrically connecting semiconductor devices and for being electrically isolated semiconductor devices and conductive knot
The insulating barrier of structure.Semiconductor base includes silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator substrate, germanium on insulator
Substrate, glass substrate.Semiconductor devices includes transistor, and the first conductive layer 4 electrically connects with transistor, realizes read/write function.
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, its various change or replacement can be readily occurred in,
These should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the guarantor of the claim
Shield scope is defined.
Claims (14)
- A kind of 1. embolism forming method, it is characterised in that including：Semiconductor substrate is provided, dielectric layer is formed in the substrate surface, is formed on the dielectric layer and is communicated to the substrate The hole on surface, the dielectric layer include a retaining layer portion and a sacrifice layer portion；Expand the bore at the openend of described hole, to reduce depth-to-width ratio of the described hole at the openend, the hole Reaming inclined-plane is formed at the openend in hole, the depth on the reaming inclined-plane is less than the thickness in the sacrifice layer portion；Form the first conductive layer includes embolism portion in the upper surface , And of the dielectric layer and first conductive layer, is filled in institute State in hole, there is space in the embolism portion, the space extends along described hole length direction, the bottom in the space No more than the thickness definition scope in the sacrifice layer portion, the upper end in the space is no more than the formation table of first conductive layer Face；The sacrifice layer portion is removed, to remove the space and part first conductive layer simultaneously, is put down until exposing surface Thickness definition scope of the neat conductive plug in the retaining layer portion.
- 2. embolism forming method as claimed in claim 1, it is characterised in that the technique for expanding the bore at the openend is Using sputtering technology or cineration technics in situ, the reaming inclined-plane is formed first relative to the upper surface of the dielectric layer and fall Angle, and then expand the bore of the openend.
- 3. embolism forming method as claimed in claim 1, it is characterised in that also include：Formed first conductive layer it Before, deposition barrier layer in the bottom and side wall of the upper surface of the dielectric layer and described hole, for first conductive layer and Deposition of the embolism portion on the barrier layer is formed.
- 4. embolism forming method as claimed in claim 3, it is characterised in that the material on the barrier layer selected from tungsten nitride, One of titanium and titanium nitride.
- 5. embolism forming method as claimed in claim 3, it is characterised in that also include：Before the barrier layer is formed, lead to Cross deposition and annealing process and form the second conductive layer in the substrate surface that described hole bottom-exposed goes out, for the stop Layer is formed；The material of second conductive layer selected from titanium silicide, zirconium silicide, tantalum silicide, cobalt silicide and nickle silicide wherein it One.
- 6. embolism forming method as claimed in claim 5, it is characterised in that also include：Formed second conductive layer it After carry out wet clean process, removal is attached to second conductive layer, described hole madial wall and the surface of the openend Impurity.
- 7. embolism forming method as claimed in claim 1, it is characterised in that first conductive layer passes through chemical vapor deposition Technique is formed in the dielectric layer surface and is filled in described hole.
- 8. embolism forming method as claimed in claim 1, it is characterised in that the material of the dielectric layer is selected from oxide； The material of first conductive layer is selected from one of tungsten, copper, aluminium or polysilicon.
- 9. the embolism forming method as described in any one of claim 1 to 8, it is characterised in that utilize chemical mechanical milling tech Remove first conductive layer on the dielectric layer surface and the sacrifice layer portion.
- A kind of 10. semiconductor devices with embolism, it is characterised in that including：Semi-conductive substrate；One dielectric layer, is formed at the surface of the substrate, the dielectric layer have the hole that is communicated to the substrate surface and First tabular surface, the opening of described hole are exposed to first tabular surface；And conductive plug, it is filled in described hole, institute It is the homogeneous solid that is made up of the first conductive layer to state conductive plug, and the conductive plug has the second tabular surface, described second Tabular surface is to be put down without being recessed and filling up the opening of described hole, second tabular surface and first tabular surface same Face.
- 11. as claimed in claim 10 have embolism semiconductor devices, it is characterised in that described hole surface with it is described Barrier layer is provided between conductive plug.
- 12. there is the semiconductor devices of embolism as claimed in claim 11, it is characterised in that described in described hole bottom The second conductive layer is provided between barrier layer and described hole lower surface.
- 13. there is the semiconductor devices of embolism as claimed in claim 10, it is characterised in that the material of first conductive layer For tungsten.
- 14. the semiconductor devices with embolism as described in claim 11 or 12, it is characterised in that the barrier layer has ring Edge, it is revealed in the opening of described hole and between first tabular surface and second tabular surface, described second Tabular surface is formed in a continuous surface via the rim and first tabular surface.
Priority Applications (2)
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| CN201710640184.1A CN107452676B (en) | 2017-07-31 | 2017-07-31 | A kind of embolism forming method |
| CN201810291816.2A CN108511416B (en) | 2017-07-31 | 2017-07-31 | Semiconductor devices with embolism |
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| CN201710640184.1A CN107452676B (en) | 2017-07-31 | 2017-07-31 | A kind of embolism forming method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110299319A (en) * | 2018-03-21 | 2019-10-01 | 联华电子股份有限公司 | The intraconnections manufacturing method of semiconductor element |
| CN113539944A (en) * | 2020-04-16 | 2021-10-22 | 长鑫存储技术有限公司 | Semiconductor structure, forming method thereof and semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070010088A1 (en) * | 2005-07-11 | 2007-01-11 | Dongbu Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
| CN103839874A (en) * | 2012-11-21 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Metal interconnection structure and manufacturing method thereof |
| CN104425710A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Phase change random access memory and forming method thereof |
| CN104752334A (en) * | 2013-12-31 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method of contact plug |
| CN105990216A (en) * | 2015-01-29 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Formation method of interconnection structure |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101635273A (en) * | 2009-06-12 | 2010-01-27 | 上海宏力半导体制造有限公司 | Preparation method of tungsten plug |
| CN102054758A (en) * | 2009-11-10 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming tungsten plug |
-
2017
- 2017-07-31 CN CN201710640184.1A patent/CN107452676B/en active Active
- 2017-07-31 CN CN201810291816.2A patent/CN108511416B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070010088A1 (en) * | 2005-07-11 | 2007-01-11 | Dongbu Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
| CN103839874A (en) * | 2012-11-21 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Metal interconnection structure and manufacturing method thereof |
| CN104425710A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Phase change random access memory and forming method thereof |
| CN104752334A (en) * | 2013-12-31 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method of contact plug |
| CN105990216A (en) * | 2015-01-29 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Formation method of interconnection structure |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110299319A (en) * | 2018-03-21 | 2019-10-01 | 联华电子股份有限公司 | The intraconnections manufacturing method of semiconductor element |
| CN113539944A (en) * | 2020-04-16 | 2021-10-22 | 长鑫存储技术有限公司 | Semiconductor structure, forming method thereof and semiconductor device |
| CN113539944B (en) * | 2020-04-16 | 2023-09-12 | 长鑫存储技术有限公司 | Semiconductor structure, forming method thereof and semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108511416A (en) | 2018-09-07 |
| CN108511416B (en) | 2019-08-30 |
| CN107452676B (en) | 2018-05-18 |
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