CN207977305U - Semiconductor devices - Google Patents
Semiconductor devices Download PDFInfo
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- CN207977305U CN207977305U CN201820484919.6U CN201820484919U CN207977305U CN 207977305 U CN207977305 U CN 207977305U CN 201820484919 U CN201820484919 U CN 201820484919U CN 207977305 U CN207977305 U CN 207977305U
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Abstract
The utility model embodiment discloses a kind of semiconductor devices, including：Substrate；A plurality of conductor wire forms over the substrate, multiple intervals is formed between the adjacent conductor wire；And medium dividing wall, the side for constituting and being formed in the conductor wire is etched by first medium separation layer, wherein there are two or more deep-hole slots at least one interval；Lattice is constituted by being identical to the etching selection ratio material of the medium dividing wall and sacrificing separation layer alternating deposit, is set in the interval, by being separated by the lattice to form vertical deep-hole slot between two deep-hole slots；And sealing buffer layer, under the support of the conductor wire, the medium dividing wall and the lattice, the sealing buffer layer seals the open end of the deep-hole slot to form medium cavity in the deep-hole slot.
Description
Technical field
The utility model is related to semiconductor dynamic RAM manufacturing technology field, more particularly to a kind of semiconductor device
Part.
Background technology
With the quick increase of semiconductor integrated circuit element integration density, as the metal of conductor wire in labyrinth
The ghost effects such as the interconnection delay that line generates signal transmission be can not ignore.At present mainly by using the material of low-k
Method to reduce metal line capacitance reduces the ghost effect in signal transmission, and preparation media cavity is material in the material
Realize a kind of method of low-k.As medium is 10 points empty between current semiconductor dynamic RAM metal wire by Fig. 1
Cloth, 10 sizes of medium cavity reduce with the increase of metal wire spacing.
Therefore, the capacitance between conductor wire how is reduced, and then reduces the parasitic capacitance of semiconductor dynamic RAM, is
Those skilled in the art are badly in need of technical problems to be solved.
Disclosed above- mentioned information is only used for reinforcing the understanding to the background of the utility model in the background technology, therefore it can
The information for not being formed as the prior art that those of ordinary skill in the art are known can be included.
Utility model content
In view of this, the utility model embodiment provides a kind of semiconductor devices, at least to solve to deposit in background technology
The technical issues of.
The technical solution of the utility model embodiment is achieved in that embodiment according to the present utility model, provides
A kind of semiconductor devices, including：
Substrate；
A plurality of conductor wire forms over the substrate, multiple intervals is formed between the adjacent conductor wire；And
Medium dividing wall is etched the side for constituting and being formed in the conductor wire by first medium separation layer, wherein extremely
There are two or more deep-hole slots in a few interval；
Lattice, by being identical to the etching selection ratio material of the medium dividing wall and sacrificing separation layer alternating deposit structure
At being set in the interval, by being separated by the lattice to form vertical deep-hole slot between two deep-hole slots；
And
Seal buffer layer, under the support of the conductor wire, the medium dividing wall and the lattice, institute
It states sealing buffer layer and seals the open end of the deep-hole slot to form medium cavity in the deep-hole slot.
The utility model embodiment due to using the technology described above, has the following advantages：In the conductor wire, described
Under the support of medium dividing wall and the lattice, the sealing buffer layer seal the open end of the deep-hole slot with
Medium cavity is formed in the deep-hole slot so that the medium cavity at the interval of more deep-hole slots is consistent with deep-hole slot quantity.One side
Face increases the quantity in the medium cavity in the interval of same more deep-hole slots, on the other hand, every in the interval of more deep-hole slots
The size in one medium cavity is larger, to reduce the dielectric relative dielectric constant of conductive interlayer, thereby reduces conduction
Capacitance between line reduces the parasitic capacitance of semiconductor dynamic RAM.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to be limited in any way.Except foregoing description
Schematical aspect, except embodiment and feature, by reference to attached drawing and the following detailed description, the utility model is into one
Aspect, embodiment and the feature of step, which will be, to be readily apparent that.
Description of the drawings
In the accompanying drawings, unless specified otherwise herein, otherwise run through the identical reference numeral of multiple attached drawings and indicate same or analogous
Component or element.What these attached drawings were not necessarily to scale.It should be understood that these attached drawings are depicted only according to this practicality
Some novel disclosed embodiments, and should not be taken as the limitation to the scope of the utility model.
Fig. 1 is the schematic diagram in conductive inter-level dielectric cavity in background technology；
Fig. 2 is the flow chart of the preparation method in the conductive inter-level dielectric cavity of the utility model embodiment；
Fig. 3 is that the preparation method in conductive inter-level dielectric cavity shown in Fig. 2 completes the schematic diagram of step S100；
Fig. 4 is that the preparation method in conductive inter-level dielectric cavity shown in Fig. 2 completes the schematic diagram of step S210；
Fig. 5 is that the preparation method in conductive inter-level dielectric cavity shown in Fig. 2 completes the schematic diagram of step S220；
Fig. 6 is that the preparation method in conductive inter-level dielectric cavity shown in Fig. 2 completes the schematic diagram of step S300；
Fig. 7 is that the preparation method in conductive inter-level dielectric cavity shown in Fig. 2 completes the schematic diagram of step S400；
Fig. 8 is that the preparation method in conductive inter-level dielectric cavity shown in Fig. 2 completes the schematic diagram of step S510；
Fig. 9 is that the preparation method in conductive inter-level dielectric cavity shown in Fig. 2 completes the schematic diagram of step S520；
Figure 10 is that the preparation method in conductive inter-level dielectric cavity shown in Fig. 2 completes the schematic diagram and semiconductor of step S600
The schematic diagram of device.
Reference sign：
In background technology：
10 media cavity；
In the utility model：
100 substrates,
210 conductor wires,
220 intervals,
221 deep-hole slots,
311 first medium separation layers,
311a medium dividing walls,
312 second medium separation layers,
313 sealing buffer layers,
321 first sacrifice separation layer,
330 media cavity,
400 lattices,
410 lattices are open.
Specific implementation mode
Hereinafter, certain exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present utility model, it can be changed by various different modes described real
Apply example.Therefore, attached drawing and description are considered essentially illustrative rather than restrictive.
Embodiment one
The utility model embodiment one provides a kind of preparation method in conductive inter-level dielectric cavity, as shown in Fig. 2, including
Following steps：
As shown in figure 3, step S100：One substrate 100 is provided, forms a plurality of conductor wire 210 on the substrate 100, it is described
Multiple intervals 220 are formed between conductor wire；
As shown in figure 4, step S210：Using the first deposition on the surface that the substrate is formed with the conductor wire side
Method depositing first material forms first medium separation layer 311, with the exposed upper for covering the substrate 100, the conduction
The upper surface and side of line 210, wherein the unfilled all intervals of first medium separation layer 311；
As shown in figure 5, step S220：First deposition is used on the first medium separation layer 311
Second material forms first and sacrifices separation layer 321, wherein described first sacrifices the unfilled all intervals of separation layer；Using
First material and second material described in the first deposition method alternating deposit, until as shown in fig. 6, step S300 kth
Secondary deposition forms second medium separation layer 312, and k is greater than the positive integer equal to 3；
As shown in fig. 7, step S400：It polishes from the upper table of the second medium separation layer 312 and is covered until exposing downwards
The first medium separation layer 311 that is placed on the conductor wire upper surface and it is revealed in the adjacent first medium separation layer
Interlayer is isolated with the second medium described first sacrifices separation layer 321；
As shown in figure 8, step S510：It etches the first sacrifice separation layer and is deposited on the substrate top surface until exposing
First medium separation layer 311；Etch the vertical portion for the layer structure that second material is formed；
As shown in figure 9, step S520：The first medium separation layer is etched until exposing the substrate and the conduction
Line, to form vertical deep-hole slot 221 between the conductor wire and be formed by the first medium separation layer and in institute
State the medium dividing wall 311a of the side of conductor wire, wherein there are two or more depths at least one interval
Hole slot 221 is separated by the lattice 400 being made of first material and the second material between two deep-hole slots；With
And
As shown in Figure 10, step S600：Using second material described in the second deposition formed sealing medium every
Absciss layer 313, wherein described under the support of the conductor wire 210, the medium dividing wall 311a and the lattice
Sealing buffer layer 313 seals the open end of the deep-hole slot to form medium cavity 330 in the deep-hole slot.
The preparation method in the conductive inter-level dielectric cavity of the utility model embodiment, by etch away the first medium every
Absciss layer is until expose the substrate and the conductor wire, to form vertical deep-hole slot between the conductor wire so that first
Vertical portion that buffer layer is not etched away forms medium dividing wall, at least one interval there are two tools or two
Above deep-hole slot is separated by the lattice being made of first material and the second material between two deep-hole slots,
The interval is known as the interval of more deep-hole slots；The second material described in the second deposition is used to form sealing medium isolation later
Layer, wherein under the support of the conductor wire, the medium dividing wall and the lattice, the sealing medium isolation
Layer seals the open end of the deep-hole slot to form medium cavity in the deep-hole slot so that the medium at the interval of more deep-hole slots
Cavity is consistent with deep-hole slot quantity.On the one hand the quantity in the medium cavity in the interval of same more deep-hole slots is increased, it is another
The size of aspect, each medium cavity in the interval of more deep-hole slots is larger, to reduce the dielectric phase of conductive interlayer
To dielectric constant, the capacitance between conductor wire is thereby reduced, reduces the parasitic capacitance of semiconductor dynamic RAM.
In order to realize it is as big as possible reduce the dielectric relative dielectric constant of conductive interlayer, the deep-hole slot in interval
Quantity is The more the better.Therefore, the second medium separation layer fills up all intervals.In this way, deep-hole slot in widest interval
Quantity it is most.
About the value of k, it is and the widest relevant amount in interval in multiple intervals.Specifically, the value of k meets with ShiShimonoseki
It is formula：
Wherein, ceil is the function that rounds up, LIt is maximumIt is the width at widest interval, h1It is the thickness of first medium separation layer
Degree, h2It is the thickness of the first sacrifice separation layer.
In this way, according to the width at the widest interval of conductive interlayer, the thickness of first medium separation layer and first sacrifice every
After the thickness of absciss layer determines, the value of k determines that.
The preparation method in above-mentioned conduction inter-level dielectric cavity, which is suitable for multiple intervals, has at least two width.
In step S300, when kth time deposition forms second medium separation layer 312, used is that the first material is formed
Second medium separation layer 312；
Then in step S510, it only includes second of deposition to etch the layer structure that second of material is formed, and arrives kth -1
The first sacrifice separation layer that secondary deposition is formed.
In step S300, when kth time deposition forms second medium separation layer 312, used is that second of material is formed
Second medium separation layer 312；
Then in step S510, it includes not only depositing to kth-for the second time to etch the layer structure that second of material is formed
The first sacrifice separation layer that 2 depositions are formed, and include that kth time second of material of deposition forms first medium separation layer.
About the first deposition method and the second deposition method, first deposition method includes atomic layer deposition method, described
Second deposition method includes the vapour deposition process of plasma enhanced chemical.
The first material is deposited about kth time or second of material forms the deposition method of the third dielectric layer, can be adopted
With the second deposition method, the first deposition method can also be used.From the angle of control cost, second side of deposition of generally use
Method, the i.e. vapour deposition process of plasma enhanced chemical.Influence unobvious using two kinds of deposition methods to subsequent handling, and the
One deposition method, the i.e. cost of atomic layer deposition method are higher than the cost of the vapour deposition process of plasma enhanced chemical.
The step of kth time deposition forms second medium separation layer include：
When k is odd number, with the first material described in first deposition, the first medium isolation is formed
Layer is used as the second medium separation layer, or with the first material described in second deposition, forms described the
One buffer layer is as the second medium separation layer；And
When k is even number, with second of material described in first deposition, forms described first and sacrifice isolation
Layer is used as the second medium separation layer, or with second of material described in second deposition, forms described the
One sacrifices separation layer as the second medium separation layer.
As an example, Fig. 3 to Figure 10 is shown, k 4, and is deposited second using second of deposition method the 4th
Material forms the specific example of second medium separation layer.
As shown in figure 9, in step S520, including：
At least one lattice opening 410 is formed on the top of the lattice 400；
Correspondingly, as shown in Figure 10, in step S600, including：
The sealing buffer layer 131 is additionally operable to seal the lattice opening 410 in lattice opening
Middle formation medium cavity 330.
In this way, being not only formed with medium cavity in deep-hole slot, but also medium cavity 330 is formed in lattice opening 410, from
And the dielectric relative dielectric constant of conductive interlayer is reduced, the capacitance between conductor wire is thereby reduced, it is dynamic to reduce semiconductor
The parasitic capacitance of state random access memory.
About the requirement of the first material and the second material, the dielectric constant of second of material is less than or equal to 5, the first
The dielectric constant of material is less than or equal to 5 and less than the dielectric constant of second material.The first material and second of material can
To be selected in following material, silica (dielectric constant minimum can reach 3.9), (dielectric constant is most for polycrystalline boron nitrogen film
It is small to reach 2.2), fluorinated silicon oxide (relative dielectric constant 2.7~3.7).
In this way, the dielectric constant of the first material and the second material is all relatively low, conductive line capacitance can be reduced, is posted with reducing
It comes into force and answers.
About step S100, specifically comprise the following steps：
Conductive layer is formed in substrate；
The conductive layer is patterned；
The conductive layer is performed etching according to composition, is formed with removing the part conductive layer until exposing the substrate
A plurality of conductor wire.
In this way, conductive layer can be formed very easily.
Specifically, being polished using chemical mechanical polishing technique in polishing.
Embodiment two
The utility model embodiment two provides the semiconductor devices that a kind of embodiment one is prepared, as shown in Figure 10, including：
Substrate 100；
A plurality of conductor wire 210 is formed over the substrate, and multiple intervals 220 are formed between the adjacent conductor wire；And
Medium dividing wall 311a, the side for constituting and being formed in the conductor wire is etched by first medium separation layer,
In, there are two or more deep-hole slots 221 at least one interval；
Lattice 400 is alternately sunk by being identical to the etching selection ratio material of the medium dividing wall and sacrificing separation layer
Product is constituted, and is set in the interval, is formed vertically between two deep-hole slots by being separated by the lattice 400
Deep-hole slot；And
Buffer layer 313 is sealed, in the conductor wire 210, the medium dividing wall 311a and the lattice
Under support, the sealing buffer layer 313 seals the open end of the deep-hole slot to form medium in the deep-hole slot
Cavity 330.
The quantity in the medium cavity in the interval of same more deep-hole slots of the semiconductor devices of the utility model embodiment
More, on the other hand, the size in each medium cavity in the interval of more deep-hole slots is larger, to reduce conductive interlayer electricity
The relative dielectric constant of medium thereby reduces the capacitance between conductor wire, reduces the parasitism of semiconductor dynamic RAM
Capacitance.
About the requirement of material, it is described sealing buffer layer material dielectric constant be less than or equal to 5, the medium every
The dielectric constant of material from wall is less than or equal to 5.It can be selected in following material, (dielectric constant minimum can be with for silica
Reach 3.9), polycrystalline boron nitrogen film (dielectric constant minimum can reach 2.2), fluorinated silicon oxide (relative dielectric constant 2.7~
3.7)。
The configuration quantity of the lattice of above-mentioned semiconductor device is one or more so that multiple institutes in same interval
It is same widths to state deep-hole slot.
As shown in Figure 9 and Figure 10, the top of the lattice 400 has at least one lattice opening 410, the sealing
Buffer layer 313 is additionally operable to seal the lattice opening 410 with the middle formation medium cavity in lattice opening
330.In this way, being not only formed with medium cavity in deep-hole slot, but also medium cavity 330 is formed in lattice opening, to reduce
Conductive interlayer dielectric relative dielectric constant thereby reduces the capacitance between conductor wire, reduces semiconductor dynamic random
The parasitic capacitance of memory.
As shown in Figure 9 and Figure 10, the width of the lattice opening is more than the width of the deep-hole slot.
In the description of the utility model and embodiment, it is to be understood that the fingers such as term "top", "bottom", " height "
The orientation or positional relationship shown be based on the orientation or positional relationship shown in the drawings, be merely for convenience of description the utility model and
Simplify description, does not indicate or imply the indicated device or element must have a particular orientation, with specific azimuth configuration
And operation, therefore should not be understood as limiting the present invention.
In the utility model and embodiment unless specifically defined or limited otherwise, term " setting ", " installation ",
The terms such as " connected ", " connection ", " fixation " shall be understood in a broad sense, and can also be detachably to connect for example, it may be being fixedly connected
It connects, or integral；It can be mechanical connection, can also be electrical connection, can also be communication；It can be directly connected, it can also
Indirectly connected through an intermediary, can be the interaction relationship of connection or two elements inside two elements.For this
For the those of ordinary skill in field, the concrete meaning of above-mentioned term in the present invention can be understood as the case may be.
In the utility model and embodiment unless specifically defined or limited otherwise, fisrt feature is in second feature
"upper" or "lower" may include that the first and second features are in direct contact, can also include the first and second features not be direct
It contacts but passes through the other characterisation contact between them.Moreover, fisrt feature second feature " on ", " side " and " on
Face " includes fisrt feature right over second feature and oblique upper, or to be merely representative of fisrt feature level height special higher than second
Sign.Fisrt feature second feature " under ", " lower section " and " below " include fisrt feature right over second feature and tiltedly on
Side, or be merely representative of fisrt feature level height and be less than second feature.
Above disclosure provides many different embodiments or example is used for realizing the different structure of the utility model.
In order to simplify the disclosure of the utility model, above the component of specific examples and setting are described.Certainly, they are only
Example, and purpose does not lie in limitation the utility model.In addition, the utility model can in different examples repeat reference numerals
And/or reference letter, this repetition are for purposes of simplicity and clarity, itself not indicate discussed various embodiments
And/or the relationship between setting.In addition, the example for the various specific techniques and material that the utility model provides, but this
Field those of ordinary skill can be appreciated that the application of other techniques and/or the use of other materials.
Above description is only a specific implementation of the present invention, but the scope of protection of the utility model is not limited to
In this, any one skilled in the art within the technical scope disclosed by the utility model, it is each can to readily occur in it
Kind change or replacement, these should be covered within the scope of the utility model.Therefore, the scope of protection of the utility model
It should be based on the protection scope of the described claims.
Claims (6)
1. a kind of semiconductor devices, which is characterized in that including：
Substrate；
A plurality of conductor wire forms over the substrate, multiple intervals is formed between the adjacent conductor wire；And
Medium dividing wall is etched the side for constituting and being formed in the conductor wire by first medium separation layer, wherein at least one
There are two or more deep-hole slots in a interval；
Lattice is constituted by being identical to the etching selection ratio material of the medium dividing wall and sacrificing separation layer alternating deposit,
It is set in the interval, by being separated by the lattice to form vertical deep-hole slot between two deep-hole slots；And
Seal buffer layer, under the support of the conductor wire, the medium dividing wall and the lattice, the envelope
Mouth buffer layer seals the open end of the deep-hole slot to form medium cavity in the deep-hole slot.
2. semiconductor devices according to claim 1, which is characterized in that the dielectric of the material of the sealing buffer layer
Constant is less than or equal to 5, and the dielectric constant of the material of the medium dividing wall is less than or equal to 5.
3. semiconductor devices according to claim 1, which is characterized in that multiple intervals have at least two width.
4. semiconductor devices according to claim 1, which is characterized in that the configuration quantity of the lattice is one or one
More than a so that multiple deep-hole slots are same widths in same interval.
5. semiconductor devices according to claim 1, which is characterized in that the top of the lattice has at least one point
It is open every portion, the sealing buffer layer is additionally operable to seal the lattice open end with the middle shape in lattice opening
At medium cavity.
6. semiconductor devices according to claim 5, which is characterized in that the width of the lattice opening is more than the depth
The width of hole slot.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820484919.6U CN207977305U (en) | 2018-04-04 | 2018-04-04 | Semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820484919.6U CN207977305U (en) | 2018-04-04 | 2018-04-04 | Semiconductor devices |
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| Publication Number | Publication Date |
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| CN207977305U true CN207977305U (en) | 2018-10-16 |
Family
ID=63763934
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| CN201820484919.6U Active CN207977305U (en) | 2018-04-04 | 2018-04-04 | Semiconductor devices |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108321118A (en) * | 2018-04-04 | 2018-07-24 | 睿力集成电路有限公司 | The preparation method and semiconductor devices in conductive inter-level dielectric cavity |
-
2018
- 2018-04-04 CN CN201820484919.6U patent/CN207977305U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108321118A (en) * | 2018-04-04 | 2018-07-24 | 睿力集成电路有限公司 | The preparation method and semiconductor devices in conductive inter-level dielectric cavity |
| CN108321118B (en) * | 2018-04-04 | 2023-10-13 | 长鑫存储技术有限公司 | Method for preparing dielectric cavity between conductive layers and semiconductor device |
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Effective date of registration: 20181017 Address after: 230000 room 630, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee after: Changxin Storage Technology Co., Ltd. Address before: 230000 room 526, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee before: Ever power integrated circuit Co Ltd |
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| TR01 | Transfer of patent right |