CN107452324A - Multiple receptions of one kind upgrading block anti-interference optimization method and display screen control system - Google Patents
Multiple receptions of one kind upgrading block anti-interference optimization method and display screen control system Download PDFInfo
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- CN107452324A CN107452324A CN201710577492.4A CN201710577492A CN107452324A CN 107452324 A CN107452324 A CN 107452324A CN 201710577492 A CN201710577492 A CN 201710577492A CN 107452324 A CN107452324 A CN 107452324A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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Abstract
The invention provides one kind upgrading, multiple receive the anti-interference optimization method of card and display screen control system, method and included：S1, the data forwarding module sampling time delay time is set to 4ns 8ns；S2, data forwarding module data output delay time is set to 0.5ns 1ns.Matched by doing data forwarding transmission delay in data forwarding module, the data delay time between different reception cards of same time is short, and data syn-chronization is more preferable；S3, catch in the same delay time cycle, data forwarding module receives the time that the rising edge of each data and trailing edge occur, and records each data waveform；S4, multiple data waveforms in the same delay time cycle are overlapped calculating, draw data rising edge starting time of origin and data trailing edge cut-off time of origin, sampled clock signal located at starting time of origin and is ended into the median between time of origin, sampling can accommodate more data deviations,, can correct gathered data when multistage receives card transmission data.
Description
Technical field
The present invention relates to LED control system technical field, more particularly to a kind of multiple anti-interference optimization sides of reception card of upgrading
Method and display screen control system.
Background technology
As LED display is fast-developing, LED display control system requires more and more higher, between multiple reception monomers
Upgrading is the data flow for being sent host computer by netting twine at present, and the information for reconfiguring FPGA module in other words is sent to FPGA
The storage chip of module, after storage terminates, restart FPGA module.Second configuration information for receiving card, then be by first
Open and receive card by the rearrangement transmission of FPGA module chip, the transmission of one-level one-level is gone down.
Early production reception card quantity is fewer, and interference is also few, so what is used is all the universal standard, not to confidence
Breath does rigorous SECO and optimization and can still showed well.But increasing with FPGA module internal processes, it is outside
The increasing of the electromagnetic interference of netting twine, slowly will produce problem.For example, 12M crystal oscillator and 11.0592M crystal oscillator are to baud
Be not in problem in a short time as the influence of rate, running up to certain time will go wrong.
The content of the invention
To solve problem above, sequential is carried out in the multistage reception card data transmission procedure of upgrading the invention provides one kind
One kind of optimization upgrades multiple and receives the anti-interference optimization method of card and display screen control system.
Technical scheme is as follows：
Multiple receive and block anti-interference optimization methods and display screen control system for one kind upgrading, it is described receive card include FPGA module,
First network chip and the second network chip, the FPGA module include data forwarding module, and the data forwarding module is by
For data forwarding in one network chip to the second network chip, second network chip sends data to next stage reception
Card, the described method comprises the following steps：S1, the data forwarding module sampling time delay time is set to 4ns-8ns；S2, by data turn
Hair module data output delay time is set to 0.5ns-1ns；S3, the data forwarding module caught in the same delay time cycle connect
The time that the rising edge of each data and trailing edge occur is received, records each data waveform；S4, will be more in the same delay time cycle
Individual data waveform is overlapped calculating, draws in the single delay time cycle, under data rising edge starting time of origin and data
For drop along cut-off time of origin, the median that will be originated between time of origin and cut-off time of origin is set to sampled clock signal.
Further, the data forwarding module sampling time delay time is set to 6ns-8ns；By data forwarding module data output
Delay time is set to 0.5ns.
Preferably, also include after step s4：
S5, change over time, the data waveform in the same delay time cycle also changes, and recalculates and draws in data
Rise along starting time of origin and data trailing edge cut-off time of origin, and correct sampled clock signal.
Specifically, also include in step S1, be used to accommodate the single delay time cycle in data forwarding module inner setting
The data space of the data of interior reception.
Invention additionally discloses with one kind, using a kind of upgrading as described above, multiple receive the anti-interference optimization method of card and display
Shield control system, including information release terminal machine, sending card, reception card array, control main frame and LED display, shown in LED
Column driver circuitry module is provided with screen, the collection of information release terminal machine and transmission include the data of Chinese character, character, information hair
Cloth terminating machine is connected with memory module by serial ports, and by control main frame, sending card array is connected in memory module, sends out
Card feed, which is connected to, receives card array, receives card array and the display configuration data received is connected into LED display.
Preferably, reception data are provided for inside information release terminal machine video card, and the output interface of video card is with sending cartoon
Cross cable connection.
Preferably, wherein described LED, which receives card array, includes the reception card monomer of more than one serial connection.
Preferably, the reception card monomer includes first network chip, FPGA module and the second network chip, the FPGA
Data forwarding module is provided with module, data are forwarded to the second network core by the data forwarding module from first network chip
Piece, the second network chip send data to next stage and receive card.
The features of the present invention and beneficial effect are：
1st, by setting sampling time delay time and the data output delay time of data forwarding module, forwarded in FPGA internal datas
The matching of data forwarding transmission delay is done inside module, when multistage reception card carries out data transmission, same time difference receives card
Between the data delay time it is short；
2nd, the data rising edge in the single delay time cycle is originated into time of origin and data trailing edge ends time of origin
For median as sampled clock signal, sampled data can accommodate more deviations, can be correct when multistage receives card transmission data
Gathered data.
Brief description of the drawings
Below in conjunction with the accompanying drawings, by the present invention embodiment be described in detail, will make technical scheme and its
Its beneficial effect is apparent.
Fig. 1 is the functional block diagram for receiving card；
Fig. 2 is the functional block diagram of display screen control system.
Main element symbol description：
10th, information release terminal machine；20th, control main frame；30th, memory module；40th, sending card；50th, card array is received；51st, receive
Card monomer；511st, first network chip；512nd, FPGA module；5121st, data forwarding module；513rd, the second network chip；60、
LED display.
Embodiment
Further to illustrate the technological means and its effect of the invention taken, below in conjunction with being preferable to carry out for the present invention
Example and its accompanying drawing are described in detail.
Multiple receive the anti-interference optimization method of card and display screen control system for one kind upgrading, and the card that receives includes FPGA moulds
Block 512, the network chip 513 of first network chip 511 and second, the FPGA module 512 include data forwarding module 5121, institute
Data forwarding module 5121 is stated by the data forwarding in first network chip 511 to the second network chip 513, second network
Chip 513 sends data to next stage and receives card, the described method comprises the following steps：
S1, the sampling time delay time of data forwarding module 5121 is set to 4ns-8ns；Preferably, data forwarding module 5121 is adopted
Sample delay time is set to 6ns-8ns, suitable for existing market data forwarding module 5121 and the crystal oscillator frequency of external network chip；
S2, the data output delay time of data forwarding module 5121 is set to 0.5ns-1ns；Preferably, by data forwarding module
5121 data output delay times are set to 0.5ns, and delay matching effect is more preferable.
Above method by setting sampling time delay time and the data output delay time of data forwarding module 5121,
The matching of data forwarding transmission delay is done in the inside of FPGA internal datas forwarding module 5121, when multistage reception card carries out data transmission,
The data delay time between different reception cards of same time is short, and data syn-chronization is more preferable.
S3, the data forwarding module 5121 caught in the same delay time cycle receive the rising edge and trailing edge of each data
The time of generation, record each data waveform；
S4, multiple data waveforms in the same delay time cycle are overlapped calculating, drawn in the single delay time cycle,
Data rising edge originates time of origin and data trailing edge cut-off time of origin, by sampled clock signal located at starting time of origin
The median between cut-off time of origin, sampled data can accommodate more deviations, can be with when multistage receives card transmission data
Correct gathered data, data syn-chronization are more preferable.
Preferably, also include step S5 after step s4, change over time, the data in the same delay time cycle
Waveform also changes, and recalculates and draws data rising edge starting time of origin and data trailing edge cut-off time of origin, and
Correct sampled clock signal.The Controllable Error of the data of reception is increased, relative to existing upgrade method, the data that can be received are prolonged
When it is more, acquisition capacity is improved, even if on netting twine, the interference on PCB has an impact to signal rising edge, trailing edge, in entirety
In the case that signal quality declines, it is also easier to collect, if described with eye pattern, is just to try to collect the central position of eye
Put, so most of signal could can be collected correctly.
Further, data forwarding module 5121, as the data sending terminal of the second network chip 513, inside program
Multiple alignment of data has been done, has preferably calculated and control delay in order to facilitate compiler, many program adjustment has been done, has turned in data
Between the hair output end of module 5121 can accomplish the data on same clock edge, it is not delayed or big phase deviation.
Fig. 2 is refer to, invention additionally discloses multiple receive the anti-interference optimization of card using a kind of upgrading as described above with one kind
Method and display screen control system, including information release terminal machine 10, sending card 40, reception card array 50, the and of control main frame 20
LED display 60, column driver circuitry module is provided with LED display 60, information release terminal machine 10 is gathered and sent
Data including Chinese character, character, information release terminal machine 10 is connected with memory module 30 by serial ports, and passes through control main frame
20, the array of sending card 40 is connected in memory module 30, sending card 40, which is connected to, receives card array 50, and receiving card array 50 will
The display configuration data received is connected to LED display 60.
Preferably, it is provided for receiving the video card of data, the output interface and sending card of video card inside information release terminal machine 10
40 are connected by cable.
Preferably, wherein described LED, which receives card array 50, includes the reception card monomer of more than one serial connection
51。
Specifically, it refer to Fig. 2, the reception card monomer 51 includes first network chip 511, FPGA module 512 and the
Two network chips 513, are provided with data forwarding module 5121 in the FPGA module 512, and the data forwarding module 5121 is by number
The second network chip 513 is forwarded to according to from first network chip 511, the second network chip 513 sends data to next stage and connect
Receive card.
Above content is to combine specific preferred embodiment further description made for the present invention, it is impossible to is assert
The specific implementation of the present invention is confined to these explanations, for general technical staff of the technical field of the invention,
On the premise of not departing from present inventive concept, some simple deduction or replace can also be made, should all be considered as belonging to the present invention's
Protection domain.
Claims (8)
1. multiple receive and block anti-interference optimization methods for one kind upgrading, it is described receive card include FPGA module, first network chip and
Second network chip, the FPGA module include data forwarding module, and the data forwarding module is by first network chip
To the second network chip, second network chip sends data to next stage and receives card data forwarding, it is characterised in that
It the described method comprises the following steps：
S1, the data forwarding module sampling time delay time is set to 4ns-8ns；
S2, data forwarding module data output delay time is set to 0.5ns-1ns；
When S3, the data forwarding module caught in same delay time cycle receive the rising edge of each data and trailing edge occurs
Between, record each data waveform；
S4, multiple data waveforms in the same delay time cycle are overlapped calculating, drawn in the single delay time cycle,
Data rising edge originate time of origin and data trailing edge cut-off time of origin, will starting time of origin and cut-off time of origin it
Between median be set to sampled clock signal.
2. multiple receive the anti-interference optimization method of card for a kind of upgrading according to claim 1, data forwarding module is sampled
Delay time is set to 6ns-8ns；Data forwarding module data output delay time is set to 0.5ns.
3. multiple receive the anti-interference optimization method of card for a kind of upgrading according to claim 1, also include after step s4：
S5, change over time, the data waveform in the same delay time cycle also changes, and recalculates and draws in data
Rise along starting time of origin and data trailing edge cut-off time of origin, and correct sampled clock signal.
4. multiple receptions of a kind of upgrading according to claim 1 block anti-interference optimization method, it is characterised in that in step S1
Also include, the data space for accommodating the data received in the single delay time cycle is used in data forwarding module inner setting.
5. one kind application is a kind of as any one of claim 1 ~ 3 to upgrade multiple displays for receiving the anti-interference optimization method of card
Shield control system, it is characterised in that show including information release terminal machine, sending card, reception card array, control main frame and LED
Screen, is provided with column driver circuitry module in LED display, and the collection of information release terminal machine and transmission include Chinese character, character
Data, information release terminal machine is connected with memory module by serial ports, and memory module is connected to hair by control main frame
Card feed array, sending card, which is connected to, receives card array, and the display configuration data received is connected to LED and shown by reception card array
Screen.
6. a kind of display screen control system according to claim 5, it is characterised in that set inside information release terminal machine
For receiving the video card of data, the output interface of video card is connected with sending card by cable.
7. a kind of display screen control system according to claim 5, it is characterised in that wherein described LED receives card battle array
Row include the reception card monomer of more than one serial connection.
8. a kind of display screen control system according to claim 7, it is characterised in that the reception card monomer includes first
Network chip, FPGA module and the second network chip, the FPGA module is interior to be provided with data forwarding module, the data forwarding mould
Data are forwarded to the second network chip by block from first network chip, and the second network chip sends data to next stage reception
Card.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710577492.4A CN107452324B (en) | 2017-07-15 | 2017-07-15 | It is a kind of to upgrade multiple anti-interference optimization methods of reception card and display screen control system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710577492.4A CN107452324B (en) | 2017-07-15 | 2017-07-15 | It is a kind of to upgrade multiple anti-interference optimization methods of reception card and display screen control system |
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| Publication Number | Publication Date |
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| CN107452324A true CN107452324A (en) | 2017-12-08 |
| CN107452324B CN107452324B (en) | 2019-07-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201710577492.4A Active CN107452324B (en) | 2017-07-15 | 2017-07-15 | It is a kind of to upgrade multiple anti-interference optimization methods of reception card and display screen control system |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109215561A (en) * | 2018-10-30 | 2019-01-15 | 惠科股份有限公司 | Delay adjustment circuit and method, display device |
| CN109272925A (en) * | 2018-12-12 | 2019-01-25 | 湖南众益文化传媒股份有限公司 | A kind of control system and application method of the mono- red display advertising equipment of Led |
| US20220309196A1 (en) * | 2020-03-04 | 2022-09-29 | Shenzhen Absen Optoelectronic Co., Ltd. | Configuration update method for led display screen, receiver card, led display module, and led display screen |
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| CN102595730A (en) * | 2012-02-21 | 2012-07-18 | 电子科技大学 | Single line transmission device of cascade signals of LED (Light Emitting Diode) controlling and driving chip |
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| CN109215561A (en) * | 2018-10-30 | 2019-01-15 | 惠科股份有限公司 | Delay adjustment circuit and method, display device |
| CN109215561B (en) * | 2018-10-30 | 2021-04-23 | 惠科股份有限公司 | Delay adjusting circuit and method and display device |
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| US11615217B2 (en) * | 2020-03-04 | 2023-03-28 | Shenzhen Absen Optoelectronic Co., Ltd. | Configuration update method for LED display screen, receiver card, LED display module, and LED display screen |
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