CN107437540A - 具有堆叠电子芯片的电子设备 - Google Patents
具有堆叠电子芯片的电子设备 Download PDFInfo
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- CN107437540A CN107437540A CN201611272842.8A CN201611272842A CN107437540A CN 107437540 A CN107437540 A CN 107437540A CN 201611272842 A CN201611272842 A CN 201611272842A CN 107437540 A CN107437540 A CN 107437540A
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Abstract
本公开涉及一种具有堆叠电子芯片的电子设备,包含:载体基板(2);至少第一电子芯片(4)和第二芯片(15);其中第一芯片(4)安装在载体基板(2)上,经由***的电连接元件(14)将第一芯片的正面电连接网络(8)与载体基板的电连接网络(3)进行连接;第二芯片(15)安装在第一芯片上,经由***的电连接元件(21)将第二芯片的正面电连接网络(19)与第一芯片的背面电连接网络(11)进行连接;并且电连接线(22)将第一芯片的背面电连接网络与载体基板的电连接网络进行连接。
Description
技术领域
本发明涉及包含堆叠电子芯片的电子设备领域。
背景技术
目前,在电子设备领域中,电子设备包含载体基板、安装在该载体基板顶部的第一电子芯片和安装在该第一芯片顶部的第二电子芯片,第二芯片与载体基板之间的电连接通过使用俗称为TSV的电连接通孔的第一芯片来实现。
然而,制造这类通孔耗时、困难,因而成本高,因为需要多种操作,特别是需要对第一芯片的半导体基板进行钻孔和减薄,结合该半导体基板正面上的集成电路和包含正面电连接网络的层的生产。
发明内容
提出一种电子设备,包含设置有电连接网络的载体基板;至少第一电子芯片,其在第一侧上设置有集成电路和包含正面电连接网络并具有正面的层,并且在与第一侧相反的第二侧上设置有包含背面电连接网络并具有背面的层,以及至少第二电子芯片,其在第一侧上设置有集成电路和包含正面电连接网络并具有正面的层。
第一芯片安装在载体基板的某一位置上,使得其正面朝向载体基板的一个面,并且经由***的电连接元件,将第一芯片的正面电连接网络与载体基板的电连接网络进行连接。
第二芯片安装在第一芯片的某一位置上,使得其正面朝向第一芯片的背面,并且经由***的电连接元件,将第二芯片的正面电连接网络与第一芯片的背面电连接网络进行连接。
电连接线将第一芯片的背面电连接网络的背面焊盘与载体基板的电连接网络的焊盘进行连接,第一芯片的焊盘布置在第一芯片的背面的没有被第二芯片覆盖的区域上,载体基板的焊盘布置在载体基板没有被第一芯片覆盖的区域上。
因此,第一芯片的背面电连接网络形成了用于在外周重新分配第二芯片正面焊盘的方法,由此允许对第二芯片更高密度的电连接,这并不取决于第一芯片的内部结构。
载体基板的没有被第一芯片覆盖的所述区域可围绕第一芯片的整个外周延伸。
第一芯片的没有被第二芯片覆盖的所述区域可围绕第二芯片的整个外周延伸。
电连接线可远离第一芯片的外周伸出一段距离。
电连接线嵌入在封装块中。
外部电连接元件可布置在载体基板的与支承第一芯片的面相对的一个面上,并连接至载体基板的电连接网络。
附图说明
下文将通过非限制性示例实施例来描述该电子设备,其截面示出在图1中。
具体实施方式
附图中所示的电子设备1包含设置有集成电连接网络3的载体基板2,例如包含多个彼此连接的集成金属电连接层级的多层基板。
电子设备1包含第一电子芯片4,在其第一侧上设置有半导体基板5,集成电路6和包含正面电连接网络8并具有正面9的正面层7。
第一电子芯片4还在与第一侧相反的第二侧上设置有包含背面电连接网络11并具有背面12的层10。该背面电连接网络11例如可以在金属层级中制造。
第一芯片4安装在载体基板2的某一位置上,使得其正面9朝向载体基板2的面13,并且经由多个***的电连接元件14。这些电连接元件14将载体基板2的电连接网络3的焊盘与第一芯片4的正面电连接网络8的正面焊盘进行连接。这些电连接元件14可以例如包含金属球,本领域技术人员称为“倒装焊球”(或“倒装焊”),或铜柱。
电子设备1包含第一电子芯片15,在其第一侧上设置有半导体基板16,集成电路17和包含正面电连接网络19并具有正面20的正面层18。
第二芯片15安装在第一芯片4的某一位置上,使得其正面20朝向第一芯片4的背面12,并且经由多个***的电连接元件21。这些电连接元件21将第一芯片4的背面电连接网络11的背面焊盘与第二芯片15的正面电连接网络19的正面焊盘进行连接。这些电连接元件21可以例如包含金属球,本领域技术人员称为“倒装焊球”(或“倒装焊”),或铜柱。
第一芯片4没有覆盖载体基板2的整个表面13。有利地,第一芯片4留下载体基板2的面13的围绕该第一芯片4的整个外周延伸的区域没有被覆盖。
第二芯片15没有覆盖第一芯片4的整个背面12。有利地,第二芯片15留下第一芯片4的背面13的围绕该第二芯片15的整个外周延伸的区域没有被覆盖,第二芯片15的表面区域小于第一芯片4的表面区域。
电子设备1包含多个电连接线22,其远离第一芯片4的外周伸出一段距离,并且一方面连接第一芯片4的背面电连接网络11的背面焊盘11a,另一方面连接载体基板2的电连接网络3的焊盘3a,第一芯片的焊盘布置在第一芯片4的背面12的没有被第二芯片15覆盖的区域上,载体基板2的焊盘布置在载体基板2的没有被第一芯片4覆盖的区域上。电连接线22可按行或多个错开的行布置。
需要注意电连接网络3在第一芯片4的下方延伸以便连接至连接元件14,并且在所述未被覆盖的区域内超出第一芯片4的外周延伸,以便连接至电连接线22。
还需要注意第一芯片4的背面电连接网络11在第二芯片15的下方延伸以便连接至连接元件21,并且在所述未被覆盖的区域内超出第二芯片15的外周延伸以便连接至电连接线22。
有益地,电连接线22可在第二芯片15被放置就位之前或之后通过通常在微电子领域中使用的焊线机放置就位。
电子设备1包含布置在载体基板2的面13上的封装块23,并且在其内部嵌入有芯片4和15以及电连接线22,这样电子设备1便具有平行六面体的形状。
在一个变形实施例中,封装块23为水珠状,其中嵌入有电连接线22,该水珠阻塞了载体基板2与第一芯片4之间的空间外周以及第一芯片4与第二芯片15之间的空间外周。
电子设备1包含多个外部电连接元件24,如金属球,其布置在载体基板2的与其面13相对的面25上,并且连接至电连接网络3。该多个外部电连接元件24被本领域技术人员称为“球栅阵列”(BGA)。
因此,电连接网络11和电连接线可以允许第二芯片15电连接至外部电连接球和/或连接至第一芯片4,用于交换信号和/或电力。
根据一个具体的应用,第一芯片4和第二芯片15可以是需要高度互连密度的芯片(电连接元件14和21),这就不需要在芯片的正面通过外周的焊盘来焊线。由于第二芯片15的尺寸小于第一芯片4,因此第一芯片4的背面可包含一个或多个背面电互连层级11,形成第二芯片15的电连接元件21的外周扇出,允许第二芯片15通过电线电连接至第一芯片4和基板2,并因此使得成本低于硅通孔(TSV)。
根据一个变形实施例,多个第二芯片15可以安装在第一芯片4背面的顶部上,经由连接至第一芯片4的背面电连接网络11的相应电连接元件21。有利地,第一芯片4的背面电连接网络11还可用来将多个第二芯片15彼此电连接。
Claims (6)
1.一种电子设备,包含:
载体基板(2),设置有电连接网络(3);
至少第一电子芯片(4),其在第一侧上设置有集成电路和包含正面电连接网络(8)并具有正面(9)的层,并且在与所述第一侧相反的第二侧上设置有包含背面电连接网络(11)并具有背面(12)的层,以及
至少第二电子芯片(15),其在第一侧上设置有集成电路和包含正面电连接网络(19)并具有正面(20)的层;
设备,在该设备中:
第一芯片(4)安装在所述载体基板(2)的某一位置,使得其正面面对所述载体基板的一个面,并且经由***的电连接元件(14),将所述第一芯片的正面电连接网络(8)与所述载体基板的电连接网络(3)进行连接;
第二芯片(15)安装在所述第一芯片的某一位置,使得其正面面对所述第一芯片的背面,并且经由***的电连接元件(21),将所述第二芯片的正面电连接网络(19)与所述第一芯片的背面电连接网络(11)进行连接;并且
电连接线(22)将所述第一芯片的背面电连接网络的背面焊盘(11a)与所述载体基板的电连接网络的焊盘(3a)进行连接,第一芯片的焊盘布置在第一芯片的背面的没有被第二芯片覆盖的区域上,所述载体基板的焊盘布置在所述载体基板的没有被第一芯片覆盖的区域上。
2.根据权利要求1所述的设备,其中所述载体基板的没有被第一芯片覆盖的所述区域围绕所述第一芯片的整个外周延伸。
3.根据权利要求1和2中任一项所述的设备,其中所述第一芯片的没有被所述第二芯片覆盖的所述区域围绕所述第二芯片的整个外周延伸。
4.根据前述权利要求中任一项所述的设备,其中所述电连接线(22)远离第一芯片的外周伸出一段距离。
5.根据前述权利要求中任一项所述的设备,包含所述电连接线嵌入在其中的封装块(23)。
6.根据前述权利要求中任一项所述的设备,包含外部电连接元件(24),位于所述载体基板的与支承所述第一芯片的面相对的一个面上,并连接至所述载体基板(2)的电连接网络。
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US20080265397A1 (en) * | 2007-04-30 | 2008-10-30 | Chipmos Technology Inc. | Chip-Stacked Package Structure |
US8471376B1 (en) * | 2009-05-06 | 2013-06-25 | Marvell International Ltd. | Integrated circuit packaging configurations |
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DE102004038989A1 (de) * | 2004-08-10 | 2005-12-29 | Infineon Technologies Ag | Halbleitermodul mit einem internen Halbleiterchipstapel und Verfahren zur Herstellung desselben |
EP2309536A1 (fr) * | 2009-10-08 | 2011-04-13 | STmicroelectronics SA | Assemblage de puces ou tranches semiconductrices par diffusion du matériau des plots de connexion dans un diélectrique claqué |
-
2016
- 2016-05-26 FR FR1654746A patent/FR3051974A1/fr active Pending
- 2016-11-29 CN CN201621496811.6U patent/CN206259351U/zh not_active Expired - Fee Related
- 2016-11-29 CN CN201611272842.8A patent/CN107437540A/zh active Pending
- 2016-12-27 US US15/391,211 patent/US20170345796A1/en not_active Abandoned
Patent Citations (3)
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---|---|---|---|---|
JP2001223326A (ja) * | 2000-02-09 | 2001-08-17 | Hitachi Ltd | 半導体装置 |
US20080265397A1 (en) * | 2007-04-30 | 2008-10-30 | Chipmos Technology Inc. | Chip-Stacked Package Structure |
US8471376B1 (en) * | 2009-05-06 | 2013-06-25 | Marvell International Ltd. | Integrated circuit packaging configurations |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN111244073A (zh) * | 2018-11-28 | 2020-06-05 | 意法半导体(格勒诺布尔2)公司 | 包括支撑衬底和堆叠的电子芯片的电子设备 |
US10978426B2 (en) * | 2018-12-31 | 2021-04-13 | Micron Technology, Inc. | Semiconductor packages with pass-through clock traces and associated systems and methods |
US11488938B2 (en) * | 2018-12-31 | 2022-11-01 | Micron Technology, Inc. | Semiconductor packages with pass-through clock traces and associated systems and methods |
US11855048B2 (en) | 2018-12-31 | 2023-12-26 | Micron Technology, Inc. | Semiconductor packages with pass-through clock traces and associated systems and methods |
Also Published As
Publication number | Publication date |
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US20170345796A1 (en) | 2017-11-30 |
CN206259351U (zh) | 2017-06-16 |
FR3051974A1 (fr) | 2017-12-01 |
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