CN107437538B - 集成电路、垂直金属-绝缘体-金属电容器及其制造方法 - Google Patents
集成电路、垂直金属-绝缘体-金属电容器及其制造方法 Download PDFInfo
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- CN107437538B CN107437538B CN201611114134.1A CN201611114134A CN107437538B CN 107437538 B CN107437538 B CN 107437538B CN 201611114134 A CN201611114134 A CN 201611114134A CN 107437538 B CN107437538 B CN 107437538B
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- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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Abstract
在芯片的多层级金属互连***的多个层内形成垂直的金属‑绝缘体‑金属(MIM)电容器。垂直的MIM电容器具有第一电极、第二电极和设置在第一电极和第二电极之间的高k电容器介电材料。电容器介电材料的介电常数大于层间介电(ILD)材料的介电常数。从垂直定向、相互交叉的部分第一电极和第二电极之间去除ILD后,电容器介电材料的介电常数大于设置在第一电极和第二电极之间的ILD材料的介电常数。本发明的实施例还涉及集成电路、垂直的金属‑绝缘体‑金属电容器及其制造方法。
Description
技术领域
本发明的实施例涉及集成电路、垂直的金属-绝缘体-金属电容器及其制造方法。
背景技术
半导体工艺的不断改善已经允许制造商和设计者能够创建更小、更强大的电子器件。半导体工艺已经从1971年左右达到的10μm工艺发展到2012年左右达到了22nm工艺技术。半导体工艺预期在2019年左右进一步发展到5nm的技术节点。随着半导体制造工艺的每一个进展,集成电路的器件和结构已经变得更小,这就允许在一个芯片上制造更多的组件。
面临的一个挑战涉及在为更小的部件尺寸设计的工艺中电容器的制造。电容器的生产商和设计者在芯片上具有更小的可用的实空间来用每个新一代的半导体工艺制造电容器。制造商和设计者已经开始探索具有先进的半导体技术节点的可用的其它选择以构建电容器,所构建的电容器与用过去的半导体工艺技术创建的电容器以类似的方式操作而不牺牲性能。
发明内容
本发明的实施例提供了一种垂直的金属-绝缘体-金属(MIM)电容器,包括:第一电极,包括:第一导电板,水平定向且平行于衬底,第一组导电结构,物理地连接且电连接至所述第一导电板,并且相对于所述衬底垂直定向;第二电极,包括:第二导电板,水平定向且平行于所述衬底,第二组导电结构,物理地连接且电连接至所述第二导电板,并且相对于所述衬底垂直定向;高k介电材料,设置在所述第一电极和所述第二电极之间,其中,所述高k介电材料设置在形成在第二介电材料内的凹槽内,所述第二介电材料的介电常数小于所述高k介电材料的介电常数。
本发明的另一实施例提供了一种制造垂直的金属-绝缘体-金属(MIM)电容器的方法,所述方法包括:在第一组导电结构和第二组导电结构上方沉积保持层,从而使得所述保持层水平定向且平行于衬底,并且所述第一组导电结构和所述第二组导电结构的每个相对于所述衬底垂直定向并且由第一介电材料围绕,并且其中,所述第一组导电结构物理地连接且电连接至第一导电板;蚀刻所述保持层,从而使得暴露所述第一介电材料的部分顶面;去除所述第一介电材料,其中,在去除所述第一介电材料后,所述第一组导电结构和所述第二组导电结构保持机械地固定至所述保持层;在先前被所述第一介电材料占据的间隔中沉积第二介电材料,所述第二介电材料具有比所述第一介电材料更高的介电常数;以及形成第二导电板,所述第二组导电结构物理地连接且电连接至所述第二导电板。
本发明的又一实施例提供了一种集成电路,包括:衬底;多个场效应晶体管(FET),通过至少一个第一介电层与第一金属互连层级物理地分离;以及垂直的金属-绝缘体-金属(MIM)电容器的第一电极,包括:第一导电板,水平定向且平行于所述衬底,以及第一组导电结构,相对于所述衬底垂直定向,所述第一组导电结构物理地连接且电连接至所述第一导电板,以及所述垂直的金属-绝缘体-金属电容器的第二电极,包括:第二导电板,水平定向且平行于所述衬底,以及第二组导电结构,相对于所述衬底垂直定向,所述第二组导电结构物理地连接且电连接至所述第二导电板,以及第二介电材料,设置在所述第一电极和所述第二电极之间,所述第二介电材料具有比所述第一介电层更高的介电常数。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或减小。
图1示出根据实施例的位于集成电路内的MIM电容器的集成。
图2A示出根据实施例的具有高介电常数(高k)材料的示例性的垂直的金属-绝缘体-金属(MIM)电容器的三维表示。
图2B至图2D示出根据一些实施例的图2A的示例性的垂直的MIM电容器的二维表示。
图3A至图3O示出根据实施例的图2A的示例性的垂直的MIM电容器的示例性制造方法。
图4示出根据实施例的在制造MIM电容器期间的集成电路的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为了便于描述,在此可以使用诸如“在…下方”、“在…下面”、“下”、“在…之上”、“上”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),并且在此使用的空间相对描述符可以同样地作出相应的解释。
表述“高k”指的是高介电常数。高k指的是介电常数大于SiO2的介电常数(即,大于约3.9)。类似地,“低k”指的是低介电常数并且指的是介电常数小于或等于SiO2的介电常数(即,小于或等于约3.9)。
术语通孔指的是用于导体与不同互连层级的电连接的结构。本领域中通孔有时用于描述绝缘体中的开口(将要完成的结构)和已经完成的结构自身这两种。对于本发明的目的,通孔指的是完成的结构。
本领域中的术语芯片、集成电路、半导体器件和微电子器件可经常互换使用。由于在本领域中它们是普遍理解的,本公开的实施例适用于所有上述内容。
在半导体层堆叠件上形成具有高k电介质的金属-绝缘体-金属(MIM)电容器,半导体层堆叠件具有与电容器的第一电极相关联的多个导电层,与电容器的第一电极相关联的多个导电层和与电容器的第二电极相关联的多个导电层相互交叉。每个电容器的第一电极和第二电极分别包括第一导电板和第二导电板,第一导电板和第二导电板在垂直方向上间隔开,但是彼此平行。第一组导电结构穿过导电板之间的垂直方向,并且物理地连接且电连接至第一导电板,同时第二组导电结构穿过在导电板之间的垂直方向,并且物理地连接且电连接至第二导电板。MIM电容器包括位于第一导电板和第二导电板之间以及第一组导电结构和第二组导电结构之间的介电材料。
图1是包括与衬底103上方的晶体管106集成的MIM电容器101的示例集成电路100的截面图。衬底103是通常是但是不限于硅衬底。在其它实施例中,衬底103可包括诸如锗的另外的元素半导体;包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体;包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半导体或它们的组合。在实施例中,衬底103是绝缘体上半导体(SOI)。晶体管106可以是任何类型的场效应晶体管,包括但不限于p沟道FET、n沟道FET、平面FET、鳍式FET。
MIM电容器101包括具有第一导电板102的第一电极和具有第二导电板104的第二电极。MIM电容器101的每个电极都包括垂直导电结构,与第一导电板102物理地连接和电连接的垂直导电结构和与第二导电板104物理地连接和电连接的垂直导电结构相互交叉。即,示例性第一电极包括相对于衬底103水平定向的第一导电板102,并且进一步包括相对于衬底103垂直定向的多个导电结构。
在MIM电容器101的电极之间设置介电材料108。在集成电路100中,相同的介电材料108也形成了用于各个金属线的层间介电(ILD)层,各个金属线在集成电路100上的器件之间路由信号。
由于集成电路100中MIM电容器101与其它器件的集成,经常限制了介电材料的选择。例如,介电材料108可以是具有约3.9的介电常数的二氧化硅。本领域普通技术人员应当理解,如果MIM电容器的电极之间的介电材料的介电常数增加,MIM电容器的电容将增加。然而,简单地使用较高k的材料作为介电材料108是不可能的,因为它将导致集成电路100的其它区域中的寄生电容的不期望增加。本文中涉及的具有高k电介质的MIM电容器的实施例,同时仍然集成在其他地方使用较低k的介电材料的集成电路内。
具有高k电介质的示例性垂直的MIM电容器
图2A示出根据本发明的示例性实施例的具有高k材料的示例性垂直的金属-绝缘体-金属(MIM)电容器的三维表示。垂直的MIM电容器101包括分别形成MIM电容器100的部分第一电极和第二电极的第一导电板102和第二导电板104。第一导电板102和第二导电板104布置在水平方向上。从多个导电层的相应的导电层图案化第一导电板102和第二导电板104。导电层包括但不限于诸如钨(W)、铝(Al)、钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)和铜(Cu)的一种或多种导电材料。在这个示例性实施例中,图案化一种或多种导电材料以形成第一导电板102和/或第二导电板104。第一导电板102和第二导电板104通过介电材料与其它导电元件隔离。介电材料可以包括但不限于二氧化硅(SiO2)。
MIM电容器101额外地包括多个垂直导电结构202。多个垂直导电结构202相对于衬底103垂直定向。如图2A所示,多个垂直导电结构202位于芯片的多层金属互连***的多个层内。在这个示例性实施例中的多个垂直导电结构202包括来自多个互连层级的图案化的金属互连结构,每个垂直导电结构202的图案化的金属互连结构彼此垂直地对准。每个图案化的金属互连结构的导电材料可以包括但不限于W、Al、Ti、TiN、Ta、TaN和Cu的一种或多种。垂直导电结构202进一步包括连接不同层级上的图案化的金属互连结构的通孔。例如,在MIM电容器101的示图中,灰色块代表图案化的导电块,而白色块代表通孔。通孔可以包括但不限于W、Al、Ti、TiN、Ta、TaN和Cu的任何一种或多种。在一个实例中,通孔具有比导电块更小的水平截面面积。如图2B所示,第一组导电结构和第二组导电结构分别物理地连接和电连接至第一导电板102和第二导电板104。
MIM电容器101进一步包括位于第一导电板102和第二导电板104之间的介电区204。如图2A所示,介电区204存在于第一导电板102和第二导电板104之间,并且围绕多个垂直导电结构202。根据一些实施例,介电区204包括诸如氧化铝(Al2O3)、二氧化铪(HfO2)、硅酸铪(HfSiO4)、氧化镧(La2O3)、氮化硅(SiN)、氧化锶(SrO)、二氧化钛(TiO2)、五氧化二钽(Ta2O5)、氧化钇(Y2O3)、二氧化锆(ZrO2)、硅酸锆(ZrSiO4)的高k材料或介电常数大于二氧化硅(SiO2)的介电常数的任何其它合适的材料的一层或多层。MIM电容器101的电容与介电区204的介电常数相关。
在示例性实施例中,介电区204包括介电常数大于传统的MIM电容器的介电常数的一种或多种高k材料,例如,其可以以二氧化硅作为其介电材料。在一个实施例中,在保持相同电容的同时,相比于传统的MIM电容器,具有高k介电区204的MIM电容器101占据半导体晶圆中较小的实空间(即具有较小的占有面积)。在另外的实施例中,在保持相同的占有面积的同时,相比于传统的MIM电容器,具有高k介电区204的MIM电容器101具有更大的电容。在实施例中,介电区204可以包括具有不同介电常数的介电材料的组合。
示例性垂直的MIM电容器的进一步说明
图2B至图2D是根据一些实施例的图2A的示例性垂直的MIM电容器的二维表示。图2B示出MIM电容器101的顶视图201。图2C示出MIM电容器101的前视图203。图2D示出MIM电容器101的右侧视图205。如顶视图201所示,多个垂直导电结构202包括第一组导电结构206.1至206.k(在此称为第一组导电结构206)和第二组导电结构208.1至208.n(在此称为第二组导电结构208)。第一组导电结构206和第二组导电结构208可以包括来自多个垂直导电结构202中的相同或不同数量的导电结构。第一组导电结构206和第二组导电结构208布置在行和列的矩阵中。然而,相关领域中的普通技术人员可以理解,在不背离本发明的精神和范围的情况下,第一组导电结构206和第二组导电结构208的其它布置是可能的。这些其它布置可以包括由线性部分构成的规则或不规则的多边形,由非线性部分构成的闭合曲线或对于相关领域的技术人员来说显而易见的使用线性部分和非线性部分的任何合适的组合创建的任何其它几何形状。如图2B所示,第一组导电结构206和第二组导电结构208相互交叉在行和列内。例如,第一组导电结构206和第二组导电结构208在行和列中彼此之间交替。
如图2B所示,第一组导电结构206物理地连接且电连接至第一导电板102,并且第二组导电结构208物理地连接且电连接至第二导电板104。第一组导电结构206不物理地连接或不电连接至第二导电板104,并且第二组导电结构208不物理地连接或不电连接至第一导电板102。为了方便,在顶视图201中没有阴影来示出第二导电板104。如前视图203和右侧视图205所示,第一组导电结构206和第二组导电结构208在第一导电板102和第二导电板104之间的垂直方向上穿过。
在垂直方向上的第一间隔210将第一组导电结构206与第二导电板104隔离,在垂直方向上的第二间隔212将第二组导电结构208与第一导电板102隔离。第一间隔210和第二间隔212可以用与介电区204相同的介电材料或不同的介电材料填充。在逐层工艺中图案化一种或多种导电材料以形成导电结构206和/或第二组导电结构208。每个导电结构包括与导电块交替的通孔。例如,在MIM电容器101的示图中,灰色块代表图案化的导电块,而白色块代表通孔。通孔可以包括但不限于W、Al、Ti、TiN、Ta、TaN和Cu的一种或多种。
仍参照图2B,介电区204位于第一导电板102和第二导电板104之间,并且围绕第一组导电结构206和第二组导电结构208。根据一些实施例,介电区204包括诸如氧化铝(Al2O3)、二氧化铪(HfO2)、硅酸铪(HfSiO4)、氧化镧(La2O3)、氮化硅(SiN)、氧化锶(SrO)、二氧化钛(TiO2)、五氧化二钽(Ta2O5)、氧化钇(Y2O3)、二氧化锆(ZrO2)、硅酸锆(ZrSiO4)或介电常数大于二氧化硅(SiO2)的介电常数的任何其它合适的材料中的一种或多种高k材料。
如图2B所示,一种或多种高k材料位于行和列的矩阵中的行和列之间,从而使得一种或多种高k材料封装位于第一导电板102和第二导电板104之间的第一组导电结构206和第二组导电结构208。介电区204防止第一组导电结构206中的每个导电结构彼此物理地连接和/或电连接并且防止物理地连接和/或电连接第二组导电结构208。同样地,介电区204防止第二组导电结构208中的每个导电结构彼此物理地连接和/或电连接并且防止物理地连接和/或电连接第一组导电结构206。在一些情况下,一种或多种低k材料可以位于行和列的矩阵中的一些行和列之间,从而使得一种或多种高k材料和一种或多种低k材料的组合位于介电区204中。
制造垂直的MIM电容器的示例性方法
图3A至图3O示出制造垂直的MIM电容器的示例性方法。该方法包括光刻和化学处理步骤的多步骤顺序,以创建具有高k介电材料的诸如MIM电容器的101的垂直的MIM电容器。本领域的技术人员将理解,可以通过用于形成多层级金属互连的任何合适的工艺形成这样的示例性MIM电容器的电极。互连层级通过中间介电层彼此隔离,并且通过设置在中间介电层中的导电通孔选择性地连接。
图3A示出根据实施例的制造MIM电容器的开始阶段。在具有绝缘层302的衬底103上方形成MIM电容器。绝缘层302可以是用于将电容器的导电结构与衬底103隔离的任何绝缘材料。绝缘层302的实例包括二氧化硅和氮化硅。在绝缘层302上方图案化第一导电板102。在一个实例中,第一导电板102的形状像金属片(如图2A所示),但在其它实例中,第一导电板102包括连接的金属条。第一导电板102形成了MIM电容器的部分第一电极。
图3B示出介电层304.1的沉积和通孔306.1的形成。介电层304.1可以是常用在集成电路中的任何介电材料(诸如二氧化硅)。使用传统的光刻技术图案化介电层304.1以形成通孔开口,用金属填充通孔开口以创建通孔306。图案化表面以创建介电层304.1和金属通孔306的光滑的顶面。本领域的技术人员将理解可以使用化学机械抛光(CMP)来实施抛光。贯穿MIM电容器的制造,介电层304.1形成多个介电层的第一个介电层。
图3C是在介电层304.1的表面上沉积和图案化金属焊盘308后的图3B的结构的截面图。金属焊盘308可以是任何合适的金属、金属合金或者金属堆叠件,包括但不限于W、Al和Cu的一种或多种。在一个实施例中,图案化第一组金属焊盘308以与通孔306对准,并且因此与通孔306物理地连接或电连接。第二组金属焊盘308形成在介电层304.1的表面上方并且与第一组金属焊盘电隔离。第一组金属焊盘308是MIM电容器的部分第一电极,而第二组金属焊盘308是MIM电容器的部分第二电极。
图3D示出介电层304.2和通孔310的沉积和图案化。特别地,蚀刻介电层304.2以在每个金属焊盘308上方形成通孔开口,并且用金属填充通孔开口以形成通孔310。通常抛光表面以创建介电层304.2和通孔310的平坦的顶面。本领域的技术人员将理解,可以使用化学机械抛光(CMP)来实施抛光。虚线水平线用于区分不同的介电层。介电层304.2可以包括与介电层304.1相同的材料。
本领域的技术人员将理解,可以通过镶嵌或双镶嵌金属化的方法,或可选地通过通孔填充和消减金属蚀刻来形成图案化的互连金属和通孔。
图3E示出重复参照图3C和图3D上面讨论的制造步骤后的MIM电容器的层结构。最终,沉积n个介电层,穿过n个介电层形成垂直导电结构(第n介电层被识别为304.n.)制造步骤产生物理地连接且电连接至第一导电板102的第一组垂直导电结构312以及与第一导电板102电隔离的第二组垂直导电结构314。如图2A和图2B所示,第一垂直导电结构和第二垂直导电结构可以形成为交错的布置。
应当理解,如本领域的技术人员将理解的,可以使用其它金属沉积技术以形成垂直导电结构。例如,可以穿过多个介电层蚀刻深通孔,并且在深通孔内沉积金属以形成垂直导电结构。
图3F示出到达图3E中示出的制造阶段时MIM电容器的顶视图。第一组垂直导电结构312(灰色框)示出为与第二组垂直导电结构314(白色框)交错。应当理解,在不背离本文所描述的示例性实施例的范围或精神的情况下的其它布置也是可能的。
图3G示出横跨MIM电容器的顶面的保持层316的沉积。保持层316可以是至少对用于介电层304.1-304.n的材料具有蚀刻选择性的任何合适的刚性材料。保持层306.1可以具有介于约10nm和约100nm之间的厚度。保持层316可以是但不限于诸如氮化钛或氮化钽的材料。
图3H示出使用传统的光刻技术图案化保持层316以形成支撑带318。支撑带318连接至每个垂直导电结构并且当在稍后的操作中去除介电材料时支撑垂直导电结构。
图3I是到达图3H中示出的制造阶段时MIM电容器的顶视图。可以看到支撑带318跨越多个垂直导电结构(被图案化在带下方)连接。每个支撑带318也连接至组成保持层316的膜的剩余部分。顶介电层304.n的顶面暴露于支撑带318之间。可以以不同的方式图案化保持层316以创建支撑带318。例如,可以水平地、垂直地或以十字形的图案图案化支撑带(所有都是从图的自上而下的角度观察)。
图3J示出MIM电容器的每个介电层(304.1-304.n)的去除。使用各种活性气体或湿蚀刻剂蚀刻掉每个介电层。例如,氢氟酸(HF)可以用于蚀刻掉二氧化硅介电层。在一个特定的实例中,在室温下使用约40%的NH4F和50%的HF的水基溶液以蚀刻掉MIM电容器的每个介电层。任何湿蚀刻工艺可以接着临界点干燥过程以试图避免垂直导电结构周围的湿蚀刻剂的去除对垂直导电结构的损坏。示例干蚀刻技术包括具有氟基活性气体的蚀刻。氟基气体的实例包括CF4、C4F8等。可以在具有介于10mTorr和100mTorr之间的室压力的腔室中应用氟基气体。可以实施多个蚀刻步骤以实现从所有垂直导电结构周围近乎完全地去除介电材料。例如,在不同的蚀刻步骤中使用不同的气体浓度或化学品,或者可以实施干蚀刻和湿蚀刻的组合以尽可能多的去除每个介电层(304.1-304.n)。由于支撑带318,所有垂直导电结构保持机械地固定在位置中。
图3K示出根据实施例的集成电路317的实例,示出具有从电容器的导电结构周围去除的介电材料108的部分地制造的MIM电容器301。可以应用掩模层319以保护介电材料108避免在集成电路的其它地方去除。掩模层319可以是光刻胶或诸如氮化硅的硬掩模。
图3L示出在MIM电容器内的各个垂直导电结构周围的高k电介质320的沉积,随后是保持层316(和其支撑带318)的去除。可使用诸如但不限于,化学汽相沉积(CVD)、原子层化学汽相沉积(CVD)和旋涂技术的任何已知的工艺来沉积高k电介质320。在实例中,首先使用ALCVD沉积高k电介质320的薄膜(例如,5nm-50nm),随后使用CVD沉积高k电介质320,以填充垂直导电结构312和314之间保留的间隔。CVD工艺可以是可流动CVD工艺。高k电介质320的实例包括氧化铝(Al2O3)、二氧化铪(HfO2)、硅酸铪(HfSiO4)、氧化镧(La2O3)、氮化硅(SiN)、氧化锶(SrO)、二氧化钛(TiO2)、五氧化二钽(Ta2O5)、氧化钇(Y2O3)、二氧化锆(ZrO2)、硅酸锆(ZrSiO4)或介电常数大于二氧化硅(SiO2)的介电常数的任何其它合适的材料。
在实施例中,可以沉积第一高k介电材料,随后沉积第二高k介电材料。例如,可以首先使用ALCVD沉积任何的Ta2O5、TiO2、HfO2、ZrO2、Al2O3、La2O3和Pr2O3,随后使用可流动CVD沉积任何的Ta2O5、TiO2、HfO2、ZrO2、Al2O3、La2O3、Pr2O3、SrTiO3、BaTiO3、PbTiO3、CaCu3Ti4O12和Pb[ZrxTi1-x]O3,以填充垂直导电结构312和314之间保留的区域。
图3M示出高k电介质320的沉积且平坦化后的集成电路317。在图中可以看到,通过介电材料108(其可以是低k电介质)电绝缘集成电路317的其它器件,同时部分地制造的MIM电容器301包括高k电介质320。在实施例中,在形成在介电材料108内的凹槽内设置高k电介质320。
图3N示出介电层322的沉积,其中形成在介电层322内的金属焊盘和通孔对准在第二组垂直导电结构314上方。注意,根据实施例,这些额外的金属焊盘和通孔仅图案化在第二组垂直导电结构314上方,并且不图案化在第一组垂直导电结构312上方。介电层322可以是与高k电介质320相同的材料或者可以是不同的介电材料。
图3O示出横跨最终的介电层322的顶面的第二导电板104的图案化。在一个实例中,第二导电板104的形状像金属片(如图2A所示),但是在其它的实例中,第二导电板104包括连接的金属带。第二导电板104形成了MIM电容器301的部分第二电极。根据实施例,在制造的结尾处,MIM电容器301包括具有第一物理地连接且电连接垂直导电结构的第一导电板102的第一电极以及具有第二物理地连接且电连接垂直导电结构(与第一物理地连接且电连接的垂直导电结构相互交叉)的第二导电板104的第二电极。MIM电容器301也包括设置在第一导电板102和第二导电板104之间的高k电介质320。
图4示出根据实施例的具有使用各向同性蚀刻从电容器的导电结构周围去除的介电材料108的部分地制造的MIM电容器301的另一实例。可以应用掩模层319以保护介电材料108避免在集成电路的其它地方被去除。各向同性蚀刻可以使用诸如氢氟酸(HF)或约40%的NH4F和50%的HF的水基溶液的湿化学蚀刻剂。各向同性蚀刻导致一些介电材料108从掩模层319下面的底切区402去除。
上面详细的描述公开了垂直(MIM)电容器。在第一实施例中,MIM电容器包括每个水平定向且平行于衬底并且彼此分隔开一定距离的第一导电板和第二导电板。垂直MIM电容器还包括相对于衬底垂直定向的第一组导电结构和第二组导电结构,第一组导电结构和第二组导电结构分别物理地连接且电连接至第一导电板和第二导电板。在第一电极和第二电极之间设置高k介电材料。在形成在第二介电材料内的凹槽内设置高k介电材料,第二介电材料具有小于高k介电材料的介电常数。
在上述MIM电容器中,其中,所述高k介电材料的介电常数大于二氧化硅(SiO2)的介电常数。
在上述MIM电容器中,其中,所述第一组导电结构和所述第二组导电结构布置在行和列的矩阵中。
在上述MIM电容器中,还包括设置在所述第一电极和所述第二电极之间的第二高k介电材料。
在上述MIM电容器中,还包括设置在所述第一电极和所述第二电极之间的第二高k介电材料,使用化学汽相沉积沉积所述第二高k介电材料,并且使用原子层化学汽相沉积沉积所述高k介电材料。
在上述MIM电容器中,其中,所述高k介电材料选自由氧化铝(Al2O3)、二氧化铪(HfO2)、硅酸铪(HfSiO4)、氧化镧(La2O3)、氮化硅(SiN)、氧化锶(SrO)、二氧化钛(TiO2)、五氧化二钽(Ta2O5)、氧化钇(Y2O3)、二氧化锆(ZrO2)和硅酸锆(ZrSiO4)构成的组中。
在上述MIM电容器中,其中,所述高k介电材料不同于包括所述金属-绝缘体-金属电容器的集成电路的多个层间介电层中的每一个。
在上述MIM电容器中,其中,所述第一组导电结构和所述第二组导电结构包括由通孔连接的金属焊盘。
在第二实施例中,集成电路包括衬底、通过至少一个第一介电层与设置在多个FET之上的第一金属互连层级物理地分离的多个场效应晶体管(FET)以及包括水平定向且平行于衬底的第一导电板的垂直的金属-绝缘体-金属(MIM)电容器的第一电极,和相对于衬底垂直定向的第一组导电结构(该第一组导电结构物理地连接且电连接至第一导电板),和包括水平定向且平行于衬底的第二导电板的垂直的MIM电容器的第二电极,和相对于衬底垂直定向的第二组导电结构(该第二组导电结构物理地连接且电连至第二导电板),和设置在第一电极和第二电极之间的第二介电材料(该第二介电材料具有比第一介电材料更高的介电常数)。
在上述集成电路中,其中,所述第二介电材料的介电常数大于二氧化硅(SiO2)的介电常数。
在上述集成电路中,其中,所述第一介电层的介电常数小于或等于二氧化硅的介电常数。
在上述集成电路中,其中,所述第一组导电结构和所述第二组导电结构布置在行和列的矩阵中。
在上述集成电路中,其中,所述第一组导电结构和所述第二组导电结构包括由通孔连接的金属焊盘。上述详细的描述也公开了用于制造垂直的MIM电容器的方法。该方法包括在第一组导电结构和第二组导电结构上方沉积保持层。该保持层水平定向且平行于衬底,并且第一组导电结构和第二组导电结构相对于衬底垂直定向并且由第一介电材料围绕。第一组导电结构物理地连接且电连接至第一导电板。该方法还包括蚀刻保持层,从而使得暴露第一介电材料的部分顶面并且去除第一介电材料,从而使得在去除第一介电材料后,第一组导电结构和第二组导电结构保持机械地固定至保持层。然后在先前被第一介电材料占据的间隔中沉积第二介电材料。第二介电材料具有比第一介电材料更高的介电常数。该方法还包括形成第二导电板。第二组导电结构物理地连接且电连接至第二导电板。
在上述方法中,其中,所述第二介电材料包括:介电常数大于二氧化硅(SiO2)的介电常数的材料,以及其中,所述第一介电材料包括介电常数小于或等于二氧化硅的介电常数的材料。
在上述方法中,其中,所述蚀刻包括蚀刻所述保持层以形成连接在所述第一组导电结构和所述第二组导电结构之间的平行带。
在上述方法中,其中,所述第一组导电结构和所述第二组导电结构布置在行和列的矩阵中。
在上述方法中,还包括:在沉积所述第二介电材料后,沉积第三介电材料。
在上述方法中,还包括:在沉积所述第二介电材料后,沉积第三介电材料,其中,所述第三介电材料的介电常数与所述第一介电材料的介电常数相同。
在上述方法中,还包括:在沉积所述第二介电材料后,去除所述保持层。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (17)
1.一种集成电路,包括:
位于衬底上的多个层间介电层;以及
垂直的金属-绝缘体-金属电容器,所述垂直的金属-绝缘体-金属电容器包括:第一电极,包括:
第一导电板,水平定向且平行于所述衬底,
第一组导电结构,物理地连接且电连接至所述第一导电板,
并且相对于所述衬底垂直定向;
第二电极,包括:
第二导电板,水平定向且平行于所述衬底,
第二组导电结构,物理地连接且电连接至所述第二导电板,并且相对于所述衬底垂直定向;
高k介电材料,设置在所述第一电极和所述第二电极之间,其中,所述高k介电材料设置在形成在所述多个层间介电层内的凹槽内,所述多个层间介电层的每层的介电常数小于所述高k介电材料的介电常数,其中,所述第一组导电结构和所述第二组导电结构布置在行和列的矩阵中且在每个所述行和所述列中交替。
2.根据权利要求1所述的集成电路,其中,所述高k介电材料的介电常数大于二氧化硅的介电常数。
3.根据权利要求1所述的集成电路,还包括设置在所述第一电极和所述第二电极之间的第二高k介电材料。
4.根据权利要求3所述的集成电路,其中,使用化学汽相沉积沉积所述第二高k介电材料,并且使用原子层化学汽相沉积沉积所述高k介电材料。
5.根据权利要求1所述的集成电路,其中,所述高k介电材料选自由氧化铝、二氧化铪、硅酸铪、氧化镧、氮化硅、氧化锶、二氧化钛、五氧化二钽、氧化钇、二氧化锆和硅酸锆构成的组中。
6.根据权利要求1所述的集成电路,其中,所述第一组导电结构和所述第二组导电结构包括由通孔连接的金属焊盘。
7.一种制造垂直的金属-绝缘体-金属电容器的方法,所述方法包括:
在第一组导电结构和第二组导电结构上方沉积保持层,从而使得所述保持层水平定向且平行于衬底,并且所述第一组导电结构和所述第二组导电结构的每个相对于所述衬底垂直定向并且由第一介电材料围绕,并且其中,所述第一组导电结构物理地连接且电连接至第一导电板;
蚀刻所述保持层,从而使得暴露所述第一介电材料的部分顶面;
去除所述第一介电材料,其中,在去除所述第一介电材料后,所述第一组导电结构和所述第二组导电结构保持机械地固定至所述保持层;
在先前被所述第一介电材料占据的间隔中沉积第二介电材料,所述第二介电材料具有比所述第一介电材料更高的介电常数;以及
形成第二导电板,所述第二组导电结构物理地连接且电连接至所述第二导电板。
8.根据权利要求7所述的方法,其中,所述第二介电材料包括:
介电常数大于二氧化硅的介电常数的材料,以及
其中,所述第一介电材料包括介电常数小于或等于二氧化硅的介电常数的材料。
9.根据权利要求7所述的方法,其中,所述蚀刻包括蚀刻所述保持层以形成连接在所述第一组导电结构和所述第二组导电结构之间的平行带。
10.根据权利要求7所述的方法,其中,所述第一组导电结构和所述第二组导电结构布置在行和列的矩阵中。
11.根据权利要求7所述的方法,还包括:
在沉积所述第二介电材料后,沉积第三介电材料。
12.根据权利要求11所述的方法,其中,所述第三介电材料的介电常数与所述第一介电材料的介电常数相同。
13.根据权利要求7所述的方法,还包括:
在沉积所述第二介电材料后,去除所述保持层。
14.一种集成电路,包括:
衬底,设置在所述衬底上的至少一个第一介电层;
多个场效应晶体管,通过所述至少一个第一介电层与第一金属互连层级物理地分离;以及
垂直的金属-绝缘体-金属电容器的第一电极,包括:
第一导电板,水平定向且平行于所述衬底,以及
第一组导电结构,相对于所述衬底垂直定向,所述第一组导电结构物理地连接且电连接至所述第一导电板,以及
所述垂直的金属-绝缘体-金属电容器的第二电极,包括:
第二导电板,水平定向且平行于所述衬底,以及
第二组导电结构,相对于所述衬底垂直定向,所述第二组导电结构物理地连接且电连接至所述第二导电板,以及
第二介电材料,设置在所述第一电极和所述第二电极之间并且位于所述至少一个第一介电层中的凹槽中,所述第二介电材料具有比所述至少一个第一介电层中的每个第一介电层更高的介电常数,
所述第一组导电结构和所述第二组导电结构布置在行和列的矩阵中且在每个所述行和所述列中交替。
15.根据权利要求14所述的集成电路,其中,所述第二介电材料的介电常数大于二氧化硅的介电常数。
16.根据权利要求14所述的集成电路,其中,所述第一介电层的介电常数小于或等于二氧化硅的介电常数。
17.根据权利要求14所述的集成电路,其中,所述第一组导电结构和所述第二组导电结构包括由通孔连接的金属焊盘。
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