CN107423505A - A kind of reusable checking system of module level and SoC level and verification method - Google Patents
A kind of reusable checking system of module level and SoC level and verification method Download PDFInfo
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- CN107423505A CN107423505A CN201710600749.3A CN201710600749A CN107423505A CN 107423505 A CN107423505 A CN 107423505A CN 201710600749 A CN201710600749 A CN 201710600749A CN 107423505 A CN107423505 A CN 107423505A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2117/00—Details relating to the type or aim of the circuit design
- G06F2117/08—HW-SW co-design, e.g. HW-SW partitioning
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Abstract
A kind of reusable checking system of module level and SoC level of the invention, ENV units are connected with including test and excitation unit, the ENV units include being connected with test and excitation unit successively and generator module to be opened/closed, proxy module, for driving the Drive Module of DUT configuration interfaces, ENV units also include two monitors for being used to monitor DUT configuration interfaces, scoring board for generating with reference to the Golden Model units of output and for carrying out comparing, two monitors connect Golden Model units and scoring board respectively, Golden Model units are connected with scoring board.The beneficial effects of the invention are as follows：The present invention solves the problems, such as that code is not reusable and verification efficiency is low caused by module level respectively has a set of verification platform with SoC levels in conventional authentication platform, realize the integration of module level verification platform and Software-hardware co-verification platform, facilitate the optimization and management of verification platform, substantially reduce verification platform and build the time, so as to improve verification efficiency.
Description
Technical field
The present invention relates to the reusable checking system of a kind of module level and SoC levels.
Background technology
With the development of SoC (System on Chip, on-chip system) technology, increasing module has been encapsulated into one
On chip, such as CPU (Central Processor Unit), memory, clock circuit, ancillary equipment and various interfaces etc.,
SoC technologies improve the reliability of system design, but are so that the complexity of chip design complexities and application scenarios significantly
Increase, logical function verification and chip level verification to chip functions module propose higher requirement.As shown by data according to statistics,
For the complicated chip development of a logic, 60% ~ 70% time of whole production life cycle needs to be used for chip checking work
Make, chip checking work becomes the key point that chip is successfully developed and listed in time.How more efficient covering chip work(
Chip logic capability error can be found, realize SoC chip software-hardware co-designing, have become and shorten overall product time institute face
The challenge faced.
The content of the invention
To solve technical deficiency above, the invention provides a kind of high module level of verification efficiency and SoC levels to weigh
Checking system and verification method.
The present invention is achieved by the following measures：
A kind of reusable checking system of module level and SoC level of the invention, including test and excitation unit are connected with ENV units,
The ENV units include being connected with test and excitation unit successively and generator module to be opened/closed, proxy module, for driving
DUT configures the Drive Module of interface, and ENV units also include two monitors that interface is configured for monitoring DUT, for generating
Scoring board with reference to the Golden Model units of output and for carrying out comparing, two monitors connect respectively
Golden Model units and scoring board, Golden Model units are connected with scoring board.
The verification method of the reusable checking system of module level and SoC level of the present invention, comprises the following steps：
Step 1, using script and ATL generation verification platform framework and the ENV unit related to DUT units, and according to
The function of DUT units completes writing for ENV Elementary Function codes, completes building for verification platform；
Step 2, DUT units are connected with verification platform by interface in top document, then writes module level test
Excitation, it is sent to DUT units after the processing of generator module, proxy module and Drive Module, the module in ENV units is completed
Corresponding monitoring and comparing, complete module level verification；
Step 3, ENV units are configured, write chip-scale test and excitation, DUT units are directly transmitted directly to by CPU, in ENV units
Module complete corresponding monitoring and comparing, complete chip level verification.
The beneficial effects of the invention are as follows：The present invention solve the module level in conventional authentication platform respectively have with SoC levels it is a set of
The problem of code caused by verification platform is not reusable low with verification efficiency, realizes module level verification platform and software-hardware synergism
The integration of verification platform, the optimization and management of verification platform are facilitated, verification platform is substantially reduced and builds the time, so as to improve
Verification efficiency.
Brief description of the drawings
Fig. 1 is the structured flowchart of the present invention.
Fig. 2 is the FB(flow block) of module level verification of the present invention.
Fig. 3 is the FB(flow block) of the chip level verification of the present invention.
Embodiment
Further detailed description is done to the present invention below in conjunction with the accompanying drawings：
As shown in figure 1, the checking system that a kind of module level and SoC level of the present invention is reusable, module level verification in tradition is put down
Platform and SoC level verifications Platform integration turn into a verification platform, general checking framework are generated using script and ATL, in life
Into checking framework in add reusable checking assembly, according to module level verification either the SoC level verification stages difference, add
Add corresponding test and excitation, module level test and excitation is typically write by checking language, and system level testing excitation is typically compiled by C language
Write, complete building for module level and SoC level verification platforms.In the verification platform, in addition to test and excitation, other assemblies are equal
It can be reused in module level verification and SoC level verifications, while take into account the flexibility of test case, greatly reduced size of code, test
Card platform is easier to manage, and substantially increases chip checking efficiency.Be shown in Fig. 1 the present invention general frame, grey oblique line frame
Checking assembly configurable opened or closed according to module level or SoC level verification stages.ENV and bus in the present invention
Probe is not limited to DUT and 2 BUS, can be generalized in multiple DUT and a plurality of BUS checkings.
The present invention includes test and excitation unit and is connected with ENV units, the ENV units including successively with test and excitation unit
Connect and generator module to be opened/closed, proxy module, the Drive Module for driving DUT configuration interfaces, ENV units also wrap
Two are included to be used to monitor the monitor of DUT configuration interfaces, the Golden Model units for generating reference output and be used for
The scoring board of comparing is carried out, two monitors connect Golden Model units and scoring board, Golden Model respectively
Unit is connected with scoring board.
The verification method of the reusable checking system of module level and SoC level of the present invention, comprises the following steps：
Step 1, using script and ATL generation verification platform framework and the ENV unit related to DUT units, and according to
The function of DUT units completes writing for ENV Elementary Function codes, completes building for verification platform；
Step 2, DUT units are connected with verification platform by interface in top document, then writes module level test
Excitation, it is sent to DUT units after the processing of generator module, proxy module and Drive Module, the module in ENV units is completed
Corresponding monitoring and comparing, complete module level verification；
Step 3, ENV units are configured, write chip-scale test and excitation, DUT units are directly transmitted directly to by CPU, in ENV units
Module complete corresponding monitoring and comparing, complete chip level verification.
In bottom-up checking flow, module level verification is carried out first, then carries out SoC level verifications.Module level is tested
Concern is primarily with fast searching leak for card, it is ensured that module can realize predetermined logic function, realize code and functional coverage
Rate；SoC level verifications then lay particular emphasis on the test for paying close attention to line and subsystem between each module.The excitation of the checking of module level is
Write by checking language, and the excitation of SoC levels is write by C language, is parsed by CPU excitation being sent to module, is soft
The checking of hardware collaboration；In module level verification, the checking assembly in verification platform is all based on the physical interface of module,
SoC level verification platforms can only see the external interface of chip package, can not see the physical interface of module, so as to module level verification
Platform can not be reused in the verification platform of SoC levels, it is therefore desirable to built two verification platforms, reduced the effect of chip checking
Rate.
As shown in Fig. 2 complete first be verification platform build and module level verification.First by script and template
Storehouse generates verification platform (Testbench) framework and the ENV related to DUT (Design Under Test)
(Environment) writing for ENV function codes, is completed according to DUT function, completes building for Testbench, in top layer text
DUT and Testbench is connected by interface (Interface) in part, then writes module level test and excitation, carries out mould
Block level verification.It is the framework of module level verification platform as shown in Figure 3, includes test and excitation in verification platform, it is reusable
ENV, include the generator related to parsing test and excitation, agency, the driver of driving DUT configuration interfaces, monitoring in ENV
DUT configures the monitor of interface, monitors the monitor of DUT output interfaces, Golden Model, Yi Jijin of the generation with reference to output
The scoring board of row comparing.In the verification platform, except driver and monitor carry out data exchange by interface bus
In addition, other modules use TLM (Transaction Level Modeling) connections, pass through things level (Transaction
Level) packet carries out data exchange, improves the abstraction hierarchy of data, realizes the reusable of module.
As shown in figure 3, then carrying out chip level verification, ENV is configured first, by the generator in ENV, agency and driver
Close, because the test and excitation of chip-scale is sent to DUT by CPU, excitation need not be sent by driving interface；
Bus probe are inserted in Testbench to be used for extracting the bus signals in chip, and by Bus Wrapper into Interface, with prison
Survey device to be connected, complete building for top layer Testbench；DUT is replaced with into SoC in top layer, bus probe extract in SoC with
Bus signals related DUT are packaged, and the Interface is connected with monitor；Test case is write, the test case
Make to show a C language, the transmission to DUT excitations completed by CPU after compiling, the module in ENV complete corresponding monitoring and
The function of comparing, complete chip level verification.Verification platform has simply carried out easy configuration to module level verification platform, selects
The closing of checking assembly or opening in Testbench.
Described above is only the preferred embodiment of this patent, it is noted that for the ordinary skill people of the art
For member, on the premise of the art of this patent principle is not departed from, some improvement and replacement can also be made, these improve and replaced
Also it should be regarded as the protection domain of this patent.
Claims (2)
1. a kind of module level and the reusable checking system of SoC levels, it is characterised in that：ENV is connected with including test and excitation unit
Unit, the ENV units include being connected with test and excitation unit successively and generator module to be opened/closed, proxy module, are used for
The Drive Module of DUT configuration interfaces is driven, ENV units also include two and are used to monitor the monitor of DUT configuration interfaces, are used for
Scoring board of the generation with reference to the Golden Model units of output and for carrying out comparing, two monitors connect respectively
Golden Model units and scoring board, Golden Model units are connected with scoring board.
2. a kind of module level as claimed in claim 1 and the verification method of the reusable checking system of SoC levels, it is characterised in that
Comprise the following steps：
Step 1, using script and ATL generation verification platform framework and the ENV unit related to DUT units, and according to
The function of DUT units completes writing for ENV Elementary Function codes, completes building for verification platform；
Step 2, DUT units are connected with verification platform by interface in top document, then writes module level test
Excitation, it is sent to DUT units after the processing of generator module, proxy module and Drive Module, the module in ENV units is completed
Corresponding monitoring and comparing, complete module level verification；
Step 3, ENV units are configured, write chip-scale test and excitation, DUT units are directly transmitted directly to by CPU, in ENV units
Module complete corresponding monitoring and comparing, complete chip level verification.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108829592A (en) * | 2018-06-01 | 2018-11-16 | 天津芯海创科技有限公司 | The quickly verification method of access register and list item, device and verifying equipment |
| CN109101355A (en) * | 2018-06-26 | 2018-12-28 | 天津飞腾信息技术有限公司 | A kind of processor debugging method for extracting wrong presence feature test and excitation |
| CN109444726A (en) * | 2018-10-12 | 2019-03-08 | 盛科网络（苏州）有限公司 | The inspection method and check device of test and excitation behavior congruence |
| CN109885905A (en) * | 2019-01-29 | 2019-06-14 | 北京中科微电子技术有限公司 | A kind of verifying system improving digital circuitry functions verification efficiency |
| CN111858207A (en) * | 2020-06-30 | 2020-10-30 | 浪潮(北京)电子信息产业有限公司 | SoC chip verification test system and method |
| CN113254296A (en) * | 2021-06-25 | 2021-08-13 | 上海励驰半导体有限公司 | Software implementation method and system for chip SLT test |
| CN113297017A (en) * | 2021-05-07 | 2021-08-24 | 杭州德旺信息技术有限公司 | SOC verification system and method based on UVM |
| CN113392025A (en) * | 2018-03-14 | 2021-09-14 | 上海微小卫星工程中心 | Method for monitoring process of reconfigurable FPGA software |
| CN114330221A (en) * | 2021-11-22 | 2022-04-12 | 北京百度网讯科技有限公司 | Score board implementation method, score board, electronic device and storage medium |
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| CN113297017A (en) * | 2021-05-07 | 2021-08-24 | 杭州德旺信息技术有限公司 | SOC verification system and method based on UVM |
| CN113297017B (en) * | 2021-05-07 | 2023-08-29 | 杭州德旺信息技术有限公司 | SOC verification system and method based on UVM |
| CN113254296B (en) * | 2021-06-25 | 2021-10-01 | 上海励驰半导体有限公司 | Software implementation method and system for chip SLT test |
| CN113254296A (en) * | 2021-06-25 | 2021-08-13 | 上海励驰半导体有限公司 | Software implementation method and system for chip SLT test |
| CN114330221A (en) * | 2021-11-22 | 2022-04-12 | 北京百度网讯科技有限公司 | Score board implementation method, score board, electronic device and storage medium |
| CN114330221B (en) * | 2021-11-22 | 2022-09-23 | 北京百度网讯科技有限公司 | Score board implementation method, score board, electronic device and storage medium |
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Application publication date: 20171201 |