CN107369428A - A kind of shift register and its driving method, gate driving circuit - Google Patents
A kind of shift register and its driving method, gate driving circuit Download PDFInfo
- Publication number
- CN107369428A CN107369428A CN201710867417.1A CN201710867417A CN107369428A CN 107369428 A CN107369428 A CN 107369428A CN 201710867417 A CN201710867417 A CN 201710867417A CN 107369428 A CN107369428 A CN 107369428A
- Authority
- CN
- China
- Prior art keywords
- node
- signal
- module
- control
- output part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Shift Register Type Memory (AREA)
Abstract
The embodiment of the present invention provides a kind of shift register and its driving method, gate driving circuit, wherein, wherein, the shift register includes：Input module, output module, pull-up module, drop-down module, reseting module and control module；Control module is used for the current potential for controlling first node, to cause the current potential of first node to be less than the preset multiple of the current potential of signal input part input signal；Technical scheme provided by the invention is by setting control module so that the current potential of first node will not be too high, avoids due to causing part thin film transistor (TFT) to produce threshold shift, improves job stability, use reliability and the display effect of display panel.
Description
Technical field
The present embodiments relate to display technology field, espespecially a kind of shift register and its driving method, raster data model
Circuit.
Background technology
With the development of Display Technique, high-resolution, the display panel of narrow frame turn into the trend of development, occur for this
Array base palte raster data model (Gate Driver on Array, abbreviation GOA) technology.GOA technologies are directly by the grid of display panel
Pole drive circuit is integrated on array base palte, to replace external driving chip, has the advantages that cost is low, process is few, production capacity is high.
Display panel is made up of vertically and horizontally array picture element matrix, defeated by gate driving circuit during display
Go out gated sweep signal, progressive scan accesses each pixel；Gate driving circuit is used for the gated sweep voltage for producing pixel, each
GOA unit passes to scanning signal next GOA unit successively as a shift register, opens thin film transistor (TFT) line by line and opens
Close, complete the data-signal input of pixel cell.
Study and find through inventor, in each GOA unit course of work, the voltage of key node can be excessive, causes portion
Thin film transistor (TFT) is divided to produce threshold shift, so as to reduce the job stability of display panel, use reliability and display effect.
The content of the invention
In order to solve the above-mentioned technical problem, the embodiments of the invention provide a kind of shift register and its driving method, grid
Pole drive circuit, to solve due to the working stability of the too high caused display panel of key node, use reliability in GOA unit
The technical problem reduced with display effect.
In one aspect, the embodiments of the invention provide a kind of shift register, including：Input module, output module, on
Drawing-die block, drop-down module, reseting module and control module；
The control module, for controlling the current potential of first node, to cause the current potential of first node to be inputted less than signal
Hold the preset multiple of the current potential of input signal；
The input module, is connected with signal input part and first node, under the control of signal input part, to
One node provides the signal of signal input part；
The output module, it is connected with the first clock signal terminal, first node and signal output part, in first node
Control under, to signal output part provide the first clock signal terminal signal；
The reseting module, it is connected with reset terminal, the first power end, signal output part and first node, for resetting
Under the control at end, the signal of the first power end is provided to first node and signal output part；
The pull-up module, is connected with second clock signal end and section point, for the work in second clock signal end
Under, the signal of second clock signal end is provided to section point；
The drop-down module, it is connected with first node, section point, the first power end and signal output part, for
Under the control of two nodes, the signal of the first power end is provided to first node and signal output part.
Alternatively, the control module, it is connected with first node, the first power end, second source end and signal output part,
Second source end is provided under the control of signal output part, avoiding the current potential of first node from rising, and to first node
Signal.
Alternatively, the output module：Including：Electric capacity；
The electric capacity, it is connected by control module with first node, for drawing high the current potential of first node；
The control module includes：First control unit and the second control unit；
First control unit, it is connected, uses with first node, the first power end, second source end and signal output part
In under the control of signal output part, the connection of electric capacity and first node is disconnected, to avoid the current potential of first node from being driven high；
Second control unit, it is connected with first node, second source end and signal output part, in signal output
Under the control at end, the signal at second source end is provided to first node.
Alternatively, first control unit includes：11st transistor, the tenth two-transistor and the 13rd transistor；
The grid of 11st transistor and the first pole are connected with second source end, and the second pole is connected with the 3rd node；
The grid of tenth two-transistor is connected with the 3rd node, and the first pole is connected with first node, the second pole and institute
State capacitance connection；
The grid of 13rd transistor is connected with signal output part, and the first pole is connected with the 3rd node, the second pole with
First power end connects.
Alternatively, the 11st transistor is used to draw high the 3rd node to the signal at second source end；Described tenth
Two-transistor is used to open when the 3rd node is high level, is charged, is additionally operable in the 3rd node to electric capacity by first node
To be turned off during low level, the connection of electric capacity and first node is disconnected；It is height that 13rd transistor, which is used in signal output part,
Opened during level, the current potential of the 3rd node is pulled low to the low level of the first power end.
Alternatively, second control unit includes：14th transistor；
The grid of 14th transistor is connected with signal output part, and the first pole is connected with first node, the second pole with
Second source end connects.
Alternatively, the 14th transistor is used to open when signal output part is high level, controls first node
Current potential is the high level at second source end.
On the other hand, the embodiment of the present invention also provides a kind of gate driving circuit, including：The shift LD of multiple cascades
Device.
It yet still another aspect, the embodiment of the present invention also provides a kind of driving method of shift register, applied to shift LD
In device, including：
Input module provides the signal of signal input part to first node under the control of signal input part；
Output module provides the signal of the first clock signal terminal to signal output part under the control of first node；Control
Module controls the current potential of first node, to cause the current potential of first node to be less than the default of the current potential of signal input part input signal
Multiple；
Reseting module provides the signal of the first power end to first node and signal output part under the control of reset terminal；
Module is pulled up in the presence of second clock signal end, the signal of second clock signal end is provided to section point；
Module is pulled down under the control of section point, the letter of the first power end is provided to first node and signal output part
Number.
Alternatively, the current potential of the control module control first node, to avoid the current potential of first node too high, including：
The control module provides to first node the signal at second source end under the control of signal output part.
The embodiment of the present invention provides a kind of shift register and its driving method, gate driving circuit, wherein, the displacement is posted
Storage includes：Input module, output module, pull-up module, drop-down module, reseting module and control module；Control module is used for
The current potential of first node is controlled, to cause the current potential of first node to be less than default times of the current potential of signal input part input signal
Number；Technical scheme provided by the invention is by setting control module so that the current potential of first node will not be too high, avoid due to
Cause part thin film transistor (TFT) to produce threshold shift, improve job stability, use reliability and the display effect of display panel
Fruit.
Certainly, any product or method for implementing the present invention it is not absolutely required to reach all the above excellent simultaneously
Point.Other features and advantages of the present invention will illustrate in subsequent specification embodiment, also, partly implement from specification
Become apparent in example, or understood by implementing the present invention.The purpose of the embodiment of the present invention and other advantages can pass through
Specifically noted structure is realized and obtained in specification, claims and accompanying drawing.
Brief description of the drawings
Accompanying drawing is used for providing further understanding technical solution of the present invention, and a part for constitution instruction, with this
The embodiment of application is used to explain technical scheme together, does not form the limitation to technical solution of the present invention.
Fig. 1 is the equivalent circuit diagram of existing shift register
Fig. 2 is a structural representation of shift register provided in an embodiment of the present invention；
Fig. 3 is another structural representation of shift register provided in an embodiment of the present invention；
Fig. 4 is the equivalent circuit diagram of shift register provided in an embodiment of the present invention；
Fig. 5 is the working timing figure of shift register provided in an embodiment of the present invention；
Fig. 6 is the flow chart of the driving method of shift register provided in an embodiment of the present invention；
Fig. 7 is the structural representation of gate driving circuit provided in an embodiment of the present invention.
Description of reference numerals:
INPUT-signal input part；OUTPUT-signal output part；
The clock signal terminals of CLK-first；CLKB-second clock signal end；
RST-reset terminal；The power ends of VSS-first；
VGH-second source end；PU-first node；
PD-section point；The nodes of PB-the 3rd；
C-electric capacity；M1~M12-transistor.
Embodiment
For the object, technical solutions and advantages of the present invention are more clearly understood, below in conjunction with accompanying drawing to the present invention
Embodiment be described in detail.It should be noted that in the case where not conflicting, in the embodiment and embodiment in the application
Feature can mutually be combined.
Unless otherwise defined, the embodiment of the present invention discloses the technical term used or scientific terminology should be institute of the present invention
The ordinary meaning that the personage with general technical ability is understood in category field." first ", " second " used in the embodiment of the present invention
And similar word is not offered as any order, quantity or importance, and it is used only to distinguish different parts.
The element or flase drop that the similar word such as " comprising " or "comprising" goes out before the word always, which are covered, appears in the word presented hereinafter
Element or object and its equivalent, and be not excluded for other elements or flase drop.
It will be understood by those skilled in the art that the transistor used in all embodiments of the application can be film crystal
Pipe or FET or other characteristic identical devices.Preferably, the thin film transistor (TFT) used in the embodiment of the present invention can be
Oxide semi conductor transistor.Because the source electrode of the transistor that uses here, drain electrode are symmetrical, so its source electrode, drain electrode can
To exchange.In embodiments of the present invention, to distinguish the two poles of the earth of transistor in addition to grid, one of electrode is referred to as first
Pole, another electrode are referred to as the second pole, and first extremely can be source electrode or drain electrode, and second extremely can be drain electrode or source electrode.
Fig. 1 is the equivalent circuit diagram of existing shift register, as shown in figure 1, shift register includes：Signal input part
INPUT, the first clock signal terminal CLK, second clock signal end CLKB, reset terminal RST, the first power end VSS and signal output
OUTPUT, transistor M1~M10 and electric capacity C are held, wherein, what signal output part OUTPUT was exported is the grid for driving grid
Signal.
The course of work of shift register is described below：First stage, signal input part INPUT input signal is high electricity
Flat, the first transistor M1 is opened, and pull-up node PU current potential is drawn high, electric capacity C is charged.Second stage S2, due to electricity
Hold C bootstrap effect, first node PU current potential continues to be driven high, and first node PU high level opens second transistor M2
Open, signal output part OUTPUT exports the first clock signal terminal CLK signal.
Study and find through inventor, in order to fully open transistor, ensure the charge rate of pixel electrode, in general, the
In one stage, the current potential of signal input part input signal needs to reach more than 25V, and in second stage, due to electric capacity C from
Effect is lifted, first node PU current potential can be caused to reach 2 times of the current potential of signal input part output signal, that is, reach more than 50V.
And first node PU current potential is excessive, will cause by second transistor M2, the 7th transistor M7 and the of first node control
Eight transistor M8 produce threshold shift, so as to reduce the job stability of display panel, use reliability and display effect.
In order to solve due to the working stability of the too high caused display panel of key node, use reliability in GOA unit
The problem of being reduced with display effect, the embodiments of the invention provide a kind of shift register and its driving method, raster data model electricity
Road.
Embodiment one
Fig. 2 is the structural representation of shift register provided in an embodiment of the present invention, as shown in Fig. 2 the embodiment of the present invention
The shift register of offer, including：Input module, output module, pull-up module, drop-down module, reseting module and control module.
Specifically, control module, for controlling first node PU current potential, to cause the current potential of first node to be less than signal
The preset multiple of the current potential of input input signal.Input module, it is connected, uses with signal input part INPUT and first node PU
Under the control in signal input part INPUT, signal input part INPUT signal is provided to first node PU.Output module, with
First clock signal terminal CLK, first node PU connect with signal output part OUTPUT, under first node PU control,
First clock signal terminal CLK signal is provided to signal output part OUTPUT.Reseting module, with reset terminal RST, the first power end
VSS, signal output part OUTPUT connect with first node PU, under reset terminal RST control, to first node PU and letter
Number output end OUTPUT provides the first power end VSS signal.Module is pulled up, with second clock signal end CLKB and section point
PD connections, in the presence of second clock signal end CLKB, providing second clock signal end CLKB's to section point PD
Signal.Module is pulled down, is connected with first node PU, section point PD, the first power end VSS and signal output part OUTPUT, is used
Under the control in section point PD, the first power end VSS signal is provided to first node PU and signal output part OUTPUT.
Alternatively, the characteristic of electric capacity of the preset multiple in output module is determined, the present invention is not limited this,
As long as so that the current potential of the first node in the present embodiment is less than to pass through passes through the first node that electric capacity is drawn high in the prior art
Current potential.Preferably, preset multiple can be 2.
Specifically, the first clock signal terminal CLK signal and second clock signal end CLKB signal inversion signal each other.
It should be noted that second clock signal end CLKB signal and the first clock signal terminal CLK signal have 180 degree phase
Difference.And preferable first clock signal terminal CLK signal and second clock signal end CLKB signal are in respective work
Half the time exports high level, second half time output low level in cycle.
It should be noted that the first power end VSS persistently provides low level signal, second source end VGH persistently provide height
Level signal, signal input part INPUT input signal is pulse signal, is only high level in input phase, signal output part
OUTPUT output signal is pulse signal, is only high level in the output stage, and reset terminal RST input signal is believed for pulse
Number, only it is high level in reseting stage.
Shift register provided in an embodiment of the present invention includes：Input module, output module, pull-up module, drop-down module,
Reseting module and control module；Control module is used for the current potential for controlling first node, to cause the current potential of first node to be less than letter
The preset multiple of the current potential of number input input signal；Input module, it is connected with signal input part and first node, for believing
Under the control of number input, the signal of signal input part is provided to first node；Output module, with the first clock signal terminal,
One node connects with signal output part, under the control of first node, the first clock signal terminal to be provided to signal output part
Signal；Reseting module, it is connected with reset terminal, the first power end, signal output part and first node, for the control in reset terminal
Under system, the signal of the first power end is provided to first node and signal output part；Module is pulled up, with second clock signal end and the
Two nodes connect, in the presence of second clock signal end, the signal of second clock signal end to be provided to section point；Under
Drawing-die block, it is connected with first node, section point, the first power end and signal output part, under the control of section point,
The signal of the first power end is provided to first node and signal output part, technical scheme provided by the invention controls mould by setting
Block, control the current potential of first node so that the current potential of first node will not be too high, avoids because key node is too high caused
Part thin film transistor (TFT) produces threshold shift, and then improves job stability, use reliability and the display effect of display panel
Fruit.
Alternatively, control module, with first node PU, the first power end VSS, second source end VGH and signal output part
OUTPUT connections, under signal output part OUTPUT control, second source end VGH letter to be provided to first node PU
Number.
Alternatively, Fig. 3 is another structural representation of shift register provided in an embodiment of the present invention, as shown in figure 3, control
Molding block includes：First control unit and the second control unit.
It is to be understood that output module includes electric capacity (not shown), electric capacity passes through control module and first node
PU connections, for drawing high first node PU current potential.
First control unit, with first node PU, the first power end VSS, second source end VGH and signal output part
OUTPUT connections, under signal output part OUTPUT control, the connection of electric capacity and first node PU is disconnected, to avoid the
One node PU current potential is driven high.
Second control unit, be connected with first node PU, second source end VGH and signal output part OUTPUT, for
Under signal output part OUTPUT control, second source end VGH signal is provided to first node PU.
Fig. 4 is the equivalent circuit diagram of shift register provided in an embodiment of the present invention, and input mould has been shown in particular in Fig. 4
Block, output module, reseting module, pull-up module, the exemplary knot for pulling down module, the first control unit and the second control unit
Structure.Skilled addressee readily understands that it is the implementation not limited to this of each module of the above, as long as can realize that its is respective
Function.
Alternatively, input module includes：The first transistor M1；The first transistor M1 grid and the first pole input with signal
INPUT connections are held, the second pole is connected with first node PU.
Alternatively, output module includes：Second transistor M2 and electric capacity C；Second transistor M2 grid and first node
PU connections, the first pole are connected with the first clock signal terminal CLK, and the second pole is connected with signal output part OUTPUT；Electric capacity C one end
It is connected with the tenth two-transistor M12 the second pole, the other end is connected with signal output part OUTPUT.
Alternatively, reseting module includes：Third transistor M3 and the 4th transistor M4；Third transistor M3 grid is with answering
Position end RST connections, the first pole are connected with first node PU, and the second pole is connected with the first power end VSS；4th transistor M4 grid
Pole is connected with reset terminal RST, and the first pole is connected with signal output part OUTPUT, and the second pole is connected with the first power end VSS.
Alternatively, pull-up module includes：5th transistor M5 and the 6th transistor M6.5th transistor M5 grid and
One pole is connected with second clock signal end CLKB, and the second pole is connected with the 6th transistor M6 grid.The of 6th transistor M6
One pole is connected with second clock signal end CLKB, and the second pole is connected with section point PD.
Alternatively, drop-down module includes：7th transistor M7, the 8th transistor M8, the 9th transistor M9 and the tenth crystal
Pipe M10.7th transistor M7 grid is connected with first node PU, and the first pole is connected with the 6th transistor M6 grid, and second
Pole is connected with the first power end VSS.8th transistor M8 grid is connected with first node PU, and the first pole connects with section point PD
Connect, the second pole is connected with the first power end VSS.9th transistor M9 grid is connected with section point PD, the first pole and first
Node PU connections, the second pole are connected with the first power end VSS；Tenth transistor M10 grid is connected with section point PD, and first
Pole is connected with signal output part OUTPUT, and the second pole is connected with the first power end VSS.
Alternatively, the first control unit includes：11st transistor M11, the tenth two-transistor M12 and the 13rd transistor
M13.11st transistor M11 grid and the first pole are connected with second source end VGH, and the second pole is connected with the 3rd node PB；
Tenth two-transistor M12 grid is connected with the 3rd node PB, and the first pole is connected with first node PU, and the second pole connects with electric capacity C
Connect；13rd transistor M13 grid is connected with signal output part OUTPUT, and the first pole is connected with the 3rd node PB, the second pole
It is connected with the first power end VSS.
Specifically, the 11st transistor M11 is used to draw high the 3rd node PB to second source end VGH signal；Tenth
Two-transistor M12 is used to open when the 3rd node PB is high level, is charged, is additionally operable to electric capacity C by first node PU
3rd node PB is turned off when being low level, disconnects electric capacity C and first node PU connection；13rd transistor M13 is used to believe
Number output end OUTPUT is opened when being high level, and the 3rd node PB current potential is pulled low to the first power end VSS low level.
Alternatively, the second control unit includes：14th transistor M14.14th transistor M14 grid and signal is defeated
Go out to hold OUTPUT to connect, the first pole is connected with first node PU, and the second pole is connected with second source end VGH.
Specifically, the 14th transistor is used to open when signal output part OUTPUT is high level, first node is controlled
PU current potential is second source end VGH high level.
In the present embodiment, transistor M1~M14 can be N-type TFT or P-type TFT, Ke Yitong
One technological process, manufacturing process can be reduced, be favorably improved the yield of product.In addition, it is contemplated that low-temperature polysilicon film is brilliant
The leakage current of body pipe is smaller, and therefore, preferably all transistors of the embodiment of the present invention are low-temperature polysilicon film transistor, and film is brilliant
Body pipe body can select the thin film transistor (TFT) of bottom grating structure or the thin film transistor (TFT) of top gate structure, as long as switch can be realized
Function.
It should be noted that electric capacity C can be the liquid crystal capacitance that is made up of pixel electrode and public electrode or by
The equivalent capacity that the liquid crystal capacitance and storage capacitance that pixel electrode is formed with public electrode are formed, the present invention are not limited this
It is fixed.
The technical scheme of the embodiment of the present invention is further illustrated below by the course of work of shift register.Need to illustrate
, here is illustrated by taking the course of work of first order shift register as an example.
Fig. 5 is the working timing figure of shift register provided in an embodiment of the present invention, and as shown in Figure 4 and Figure 5, the present invention is real
Applying the shift register of example offer includes 12 transistor units (M1~M14), 1 capacitor cell (C), 4 inputs
(INPUT, RST, CLK and CLKB), 1 output end (OUTPUT) and 2 power ends (VSS and VGH), its course of work includes：
First stage S1, i.e. input phase, signal input part INPUT input signal are high level, the first transistor M1
Open, first node PU current potential is drawn high, in addition, second source end VGH is high level, the 11st transistor M11 is opened, will
3rd node PB current potential is drawn high to second source end VGH high level, and the tenth two-transistor M12 is opened, PU pairs of first node
Electric capacity C is charged.Because first node PU current potential is drawn high, the 7th transistor M7 and the 8th transistor M8 are opened, by second
Node PD current potential is pulled low to the first power end VSS low level.
In this stage, the input signal and second clock signal end CLKB of the signal input part INPUT in input are
High level, reset terminal RST and the first clock signal terminal CLK input signal are low level, and signal output part OUTPUT's is defeated
It is low level to go out signal, and the first power end VSS is low level, and second source end VGH is high level.Due to section point PD electricity
Position is low level, and therefore, the 9th transistor M9 and the tenth transistor M10 are turned off all the time, do not drag down first node PU current potential.
Second stage S2, that is, export the stage, and signal input part INPUT input signal is low level, the first transistor M1
Shut-off, first node PU continue to keep high level, and section point PD continues to keep low level.Because first node PU is high electricity
Flat, second transistor M2 is opened, and the first clock signal terminal CLK input signal is changed into high level, and signal output part OUTPUT is defeated
Go out the first clock signal terminal CLK signal, i.e. gate drive signal.Because signal output part OUTPUT exports high level signal,
13rd transistor M13 is opened, and the 3rd node PB current potential is pulled low to the first power end VSS low level, the 12nd crystal
Pipe M12 is turned off, and electric capacity C and first node PU connection disconnects, then electric capacity C will not continue to draw high first node PU current potential, the
14 transistor M14 are opened, the high level that the current potential for controlling first node PU is second source end VGH.
In this stage, the input signal of the first clock signal terminal CLK in input is high level, signal input part
INPUT, reset terminal RST, second clock signal end CLKB input signal are low level, signal output part OUTPUT output
Signal is high level, and the first power end VSS is low level, and second source end VGH is high level.Due to first node PU still in
High level, the 7th transistor M7 and the 8th transistor M8 are kept it turned on, and therefore, section point PD is still in low level.
Phase III S3, i.e. reseting stage, reset terminal RST input signal are high level, third transistor M3 and the 4th
Transistor M4 is opened, and third transistor M3, which opens, to discharge first node PU, and first node PU current potential is pulled low into the first electricity
Source VSS low level, while turn off second transistor M2, to reduce noise, because first node PU is low level, then the
Seven transistor M7 and the 8th transistor T8 shut-offs；4th transistor M4, which opens, to discharge signal output part OUTPUT, and signal is defeated
Go out to hold OUTPUT current potential to be pulled low to the first power end VSS low level, to reduce signal output part OUTPUT noise, due to
7th transistor M7 and the 8th transistor M8 shut-offs, second clock signal end CLKB is high level, now, second clock signal end
CLKB draws high section point PD current potential, and the 9th transistor M9 and the tenth transistor M10 are opened, and further drag down first node
PU and signal output part OUTPUT current potential.
In this stage, the input signal of reset terminal RST and second clock signal end CLKB in input are high level, the
One clock signal terminal CLK and signal input part INPUT input signal is low level, signal output part OUTPUT output signal
For low level, the first power end VSS is low level, and second source end VGH is high level.It is defeated due to signal output part OUTPUT
It is low level to go out signal, and the 13rd transistor M13 is turned off, and the 3rd node PB current potential still controls second source end VGH height
Level, the tenth two-transistor M12 are opened.
In the present embodiment, reset terminal RST is connected with the signal output part OUTPUT of next stage shift register, reset terminal
RST high level signal is the high level of the signal output part OUTPUT outputs of next stage shift register.
Fourth stage S4, the first clock signal terminal CLK input signal are high level, because now second transistor M2 is
Off state, therefore the first clock signal terminal CLK high level can not be output to signal output part OUTPUT, signal output part
OUTPUT keeps the low level output in upper stage, and second clock signal end CLKB input signal is low level, section point PD
It is pulled low as low level.
In this stage, the input signal of the first clock signal terminal CLK in input is high level, signal input part
INPUT, reset terminal RST and second clock signal end CLKB input signal are low level, and signal output part OUTPUT's is defeated
It is low level to go out signal, and the first power end VSS is low level, and second source end VGH is high level.
5th stage S5, second clock signal end CLKB input signal are high level, due to now the 7th transistor M7
It is off state with the 8th transistor M8, therefore, section point PD current potential is second clock signal end CLKB input signal
High level, the 9th transistor M9 and the tenth transistor M10 opened, and first node PU potential duration is pulled low into the first power supply
VSS is held, to avoid noise, the tenth transistor M10 is opened, and signal output part OUTPUT potential duration is pulled low into the first power supply
VSS low level is held, to avoid noise.
In this stage, the input signal of the second clock signal end CLKB in input is high level, signal input part
INPUT, reset terminal RST and the first clock signal terminal CLK input signal are low level, signal output part OUTPUT output
Signal is low level, and the first power end VSS is low level, and second source end VGH is high level.
In the present embodiment, in the first stage after S1, signal input part INPUT input signal is continuously low level；
After two-stage S2, signal output part OUTPUT output signal is continuously low level；After phase III S3, reset terminal RST's
Input signal is continuously low level；In all stages, the first power end VSS input signal is continuously low level；Second source
End VGH input signal is continuously high level；Since second stage S2, every a stage, the first input end of clock CLK's
Input signal is high level, and since phase III S3, every a stage, second clock input CLKB input signal is
High level, the i.e. input signal of the first input end of clock CLK and second clock input CLKB are anti-phase.After the 5th stage S5,
First input end of clock CLK and second clock input CLKB input signal be repeated in one or many fourth stage S4 and
5th stage S5, the first input end of clock CLK and second clock input CLKB keep low level afterwards, until signal is defeated
The input signal for entering to hold INPUT is high level, then is restarted from the first stage.
The embodiment of the present invention by output the stage, under the control of signal output part, by turn off the tenth two-transistor,
The connection of first node and electric capacity is have turned off, avoids the current potential that electric capacity draws high first node, meanwhile, in the control of signal output part
Under system, the signal at second source end is provided to first node, avoids the too high caused part film of current potential of first node
Transistor produces threshold shift, improves job stability, use reliability and the display effect of display panel.
Embodiment two
Inventive concept based on above-described embodiment, the embodiment of the present invention also provide a kind of driving method of shift register,
In the shift register provided applied to embodiment one, the shift register includes：Input module, output module, control module,
Reseting module, pull-up module and drop-down module, and signal input part INPUT, reset terminal RST, the first clock signal terminal CLK,
Second clock signal end CLKB, the first power end VSS, second source end VGH and signal output part OUTPUT, Fig. 6 are the present invention
The flow chart of the driving method of the shift register of embodiment, as shown in fig. 6, this method specifically includes：
Step 100, input module provide the signal of signal input part to first node under signal input part control.
Specifically, signal input part INPUT input signal is pulse signal, in step 100, signal input part it is defeated
It is high level to enter signal, and input module has drawn high the current potential of first node.
Step 200, output module provide the letter of the first clock signal terminal to signal output part under the control of first node
Number；Control module controls the current potential of first node, to cause the current potential of first node to be less than the electricity of signal input part input signal
The preset multiple of position.
Specifically, in this step, the input signal of the first clock signal terminal is high level, and the output of signal output part is believed
Number it is high level.
Alternatively, preset multiple determines according to the characteristic of electric capacity in output module, it is preferable that preset multiple 2.
Specifically, the current potential of control module control first node includes：Control of the control module in signal output part OUTPUT
Under system, second source end VGH signal is provided to first node.
Step 300, reseting module provide the first power end under the control of reset terminal, to first node and signal output part
Signal.
Specifically, reset terminal RST input signal is pulse signal, and in step 300, reset terminal RST input signal
For high level, the level of first node and signal output part OUTPUT is pulled low to the first power end VSS low electricity by reseting module
Ordinary mail number, to avoid noise.
Step 400, pull-up module provide second clock signal end in the presence of second clock signal end to section point
Signal.
Specifically, in the step, second clock signal end CLKB input signal is high level, and pull-up unit is at second
The current potential of section point has been drawn high under clock signal end CLKB control.
Step 500, drop-down module provide the first power supply under the control of section point to first node and signal output part
The signal at end.
Specifically, the level of first node and signal output part OUTPUT is pulled low to the first power end VSS by drop-down module
Low level signal, to avoid noise.
The driving method of shift register provided in an embodiment of the present invention, including：Control of the input module in signal input part
Under system, the signal of signal input part is provided to first node；Output module carries under the control of first node to signal output part
For the signal of the first clock signal terminal；Control module controls the current potential of first node, to cause the current potential of first node to be less than letter
The preset multiple of the input signal current potential of number input；Reseting module is defeated to first node and signal under the control of reset terminal
Go out the signal that end provides the first power end；Module is pulled up in the presence of second clock signal end, second is provided to section point
The signal of clock signal terminal；Module is pulled down under the control of section point, the first electricity is provided to first node and signal output part
The signal of source, technical scheme provided by the invention control the current potential of first node by control module so that first node
Current potential will not be too high, avoids the part thin film transistor (TFT) caused by key node is too high and produces threshold shift, and then improves
The job stability of display panel, use reliability and display effect.
Embodiment three
Inventive concept based on above-described embodiment, the embodiment of the present invention also provide a kind of gate driving circuit, and Fig. 7 is this hair
The structural representation for the gate driving circuit that bright embodiment provides, as shown in fig. 7, gate driving circuit includes：Multiple cascades
Shift register, including：First order shift register GOA (1), second level shift register GOA (2), third level shift LD
Device GOA (3), fourth stage shift register GOA (4) etc..
Specifically, first order shift register GOA (1) signal input part INPUT and initial signal input STV connects
Connect；Signal output part OUTPUT is connected with second level shift register GOA (2) signal input part INPUT, reset terminal RST with
Second level shift register GOA (2) signal output part OUTPUT connections；Second level shift register GOA (2) signal output
End OUTPUT is connected with third level shift register GOA (3) signal input part INPUT, and reset terminal RST posts with third level displacement
Storage GOA (3) signal output part OUTPUT connections；By that analogy.
Wherein, shift register is the shift register that embodiment one provides, and its realization principle is similar with effect is realized,
This is repeated no more.
Have it is following some need to illustrate：
Accompanying drawing of the embodiment of the present invention pertain only to the present embodiments relate to structure, other structures refer to generally set
Meter.
For clarity, in the accompanying drawing for describing embodiments of the invention, the thickness and size of layer or micro-structural
It is exaggerated.It is appreciated that ought the element of such as layer, film, region or substrate etc be referred to as "above" or "below" another element
When, the element can be " direct " "above" or "below" another element, or there may be intermediary element.
In the case where not conflicting, it is new to obtain that embodiments of the invention are that the feature in embodiment can be mutually combined
Embodiment.
Although disclosed herein embodiment as above, described content be only readily appreciate the present invention and use
Embodiment, it is not limited to the present invention.Technical staff in any art of the present invention, taken off not departing from the present invention
On the premise of the spirit and scope of dew, any modification and change, but the present invention can be carried out in the form and details of implementation
Scope of patent protection, still should be subject to the scope of the claims as defined in the appended claims.
Claims (10)
- A kind of 1. shift register, it is characterised in that including：Input module, output module, pull-up module, drop-down module, reset Module and control module；The control module, for controlling the current potential of first node, make it that it is defeated that the current potential of first node is less than signal input part Enter the preset multiple of the current potential of signal；The input module, is connected with signal input part and first node, under the control of signal input part, to first segment Point provides the signal of signal input part；The output module, it is connected with the first clock signal terminal, first node and signal output part, for the control in first node Under system, the signal of the first clock signal terminal is provided to signal output part；The reseting module, it is connected with reset terminal, the first power end, signal output part and first node, in reset terminal Under control, the signal of the first power end is provided to first node and signal output part；The pull-up module, is connected with second clock signal end and section point, in the presence of second clock signal end, The signal of second clock signal end is provided to section point；The drop-down module, it is connected with first node, section point, the first power end and signal output part, in the second section Under the control of point, the signal of the first power end is provided to first node and signal output part.
- 2. shift register according to claim 1, it is characterised in that the control module, with first node, the first electricity Source, second source end connect with signal output part, under the control of signal output part, the second electricity to be provided to first node The signal of source.
- 3. shift register according to claim 1 or 2, it is characterised in that the output module includes：Electric capacity；The electric capacity, it is connected by control module with first node, for drawing high the current potential of first node；The control module includes：First control unit and the second control unit；First control unit, be connected with first node, the first power end, second source end and signal output part, for Under the control of signal output part, the connection of electric capacity and first node is disconnected, to avoid the current potential of first node from being driven high；Second control unit, it is connected with first node, second source end and signal output part, in signal output part Under control, the signal at second source end is provided to first node.
- 4. shift register according to claim 3, it is characterised in that first control unit includes：11st is brilliant Body pipe, the tenth two-transistor and the 13rd transistor；The grid of 11st transistor and the first pole are connected with second source end, and the second pole is connected with the 3rd node；The grid of tenth two-transistor is connected with the 3rd node, and the first pole is connected with first node, the second pole and the electricity Hold connection；The grid of 13rd transistor is connected with signal output part, and the first pole is connected with the 3rd node, the second pole and first Power end connects.
- 5. shift register according to claim 4, it is characterised in that the 11st transistor is used for the 3rd node Draw high to the signal at second source end；Tenth two-transistor is used to open when the 3rd node is high level, passes through first Node charges to electric capacity, is additionally operable to turn off when the 3rd node is low level, disconnects the connection of electric capacity and first node；Described 13 transistors are used to open when signal output part is high level, and the current potential of the 3rd node is pulled low into the low of the first power end Level.
- 6. shift register according to claim 3, it is characterised in that second control unit includes：14th is brilliant Body pipe；The grid of 14th transistor is connected with signal output part, and the first pole is connected with first node, the second pole and second Power end connects.
- 7. shift register according to claim 6, it is characterised in that the 14th transistor is used in signal output Hold the high level for be opened during high level, controlling the current potential of first node for second source end.
- A kind of 8. gate driving circuit, it is characterised in that including：The displacement as described in claim 1-7 is any of multiple cascades Register.
- 9. a kind of driving method of shift register, it is characterised in that posted applied to the displacement as described in claim 1-7 is any In storage, including：Input module provides the signal of signal input part to first node under the control of signal input part；Output module provides the signal of the first clock signal terminal to signal output part under the control of first node；Control module The current potential of first node is controlled, to cause the current potential of first node to be less than default times of the current potential of signal input part input signal Number；Reseting module provides the signal of the first power end to first node and signal output part under the control of reset terminal；Module is pulled up in the presence of second clock signal end, the signal of second clock signal end is provided to section point；Module is pulled down under the control of section point, the signal of the first power end is provided to first node and signal output part.
- 10. according to the method for claim 9, it is characterised in that the current potential of the control module control first node includes：The control module provides the signal at second source end to first node under the control of signal output part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710867417.1A CN107369428B (en) | 2017-09-22 | 2017-09-22 | A kind of shift register and its driving method, gate driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710867417.1A CN107369428B (en) | 2017-09-22 | 2017-09-22 | A kind of shift register and its driving method, gate driving circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107369428A true CN107369428A (en) | 2017-11-21 |
| CN107369428B CN107369428B (en) | 2019-12-03 |
Family
ID=60302849
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710867417.1A Active CN107369428B (en) | 2017-09-22 | 2017-09-22 | A kind of shift register and its driving method, gate driving circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107369428B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108172163A (en) * | 2018-01-02 | 2018-06-15 | 京东方科技集团股份有限公司 | Shift register cell, shift-register circuit and its display panel |
| CN108230980A (en) * | 2018-01-08 | 2018-06-29 | 京东方科技集团股份有限公司 | Shift register and its put control method of making an uproar, gate driving circuit and display device |
| CN109410885A (en) * | 2018-12-27 | 2019-03-01 | 信利半导体有限公司 | Scan drive circuit, image element array substrates and display panel |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106531117A (en) * | 2017-01-05 | 2017-03-22 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, gate integrated drive circuit and display device |
| CN106683607A (en) * | 2017-01-05 | 2017-05-17 | 京东方科技集团股份有限公司 | Shift register, grid drive circuit and display panel |
| CN106683632A (en) * | 2017-03-08 | 2017-05-17 | 合肥鑫晟光电科技有限公司 | Shifting register, gate drive circuit and driving method and display device thereof |
| CN106920526A (en) * | 2017-05-04 | 2017-07-04 | 合肥鑫晟光电科技有限公司 | Shift register and its driving method and gate driving circuit |
-
2017
- 2017-09-22 CN CN201710867417.1A patent/CN107369428B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106531117A (en) * | 2017-01-05 | 2017-03-22 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, gate integrated drive circuit and display device |
| CN106683607A (en) * | 2017-01-05 | 2017-05-17 | 京东方科技集团股份有限公司 | Shift register, grid drive circuit and display panel |
| CN106683632A (en) * | 2017-03-08 | 2017-05-17 | 合肥鑫晟光电科技有限公司 | Shifting register, gate drive circuit and driving method and display device thereof |
| CN106920526A (en) * | 2017-05-04 | 2017-07-04 | 合肥鑫晟光电科技有限公司 | Shift register and its driving method and gate driving circuit |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108172163A (en) * | 2018-01-02 | 2018-06-15 | 京东方科技集团股份有限公司 | Shift register cell, shift-register circuit and its display panel |
| CN108172163B (en) * | 2018-01-02 | 2021-01-26 | 京东方科技集团股份有限公司 | Shift register unit, shift register circuit and display panel thereof |
| CN108230980A (en) * | 2018-01-08 | 2018-06-29 | 京东方科技集团股份有限公司 | Shift register and its put control method of making an uproar, gate driving circuit and display device |
| CN108230980B (en) * | 2018-01-08 | 2020-11-13 | 京东方科技集团股份有限公司 | Shift register and noise release control method thereof, gate drive circuit and display device |
| CN109410885A (en) * | 2018-12-27 | 2019-03-01 | 信利半导体有限公司 | Scan drive circuit, image element array substrates and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107369428B (en) | 2019-12-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105632441B (en) | Gate driving circuit | |
| CN104715734B (en) | Shift register, gate driving circuit and display device | |
| CN104835476B (en) | Shift register cell, gate driving circuit and its driving method, array base palte | |
| CN202443728U (en) | Shift register, gate driver and display device | |
| CN105047174B (en) | Shift register cell and its driving method, gate drive apparatus and display device | |
| CN107452350B (en) | Gate drive apparatus and display panel | |
| CN105788553B (en) | GOA circuits based on LTPS semiconductor thin-film transistors | |
| CN107039017A (en) | Shift register cell and its driving method, gate driving circuit, display device | |
| CN102930814A (en) | Shifting register as well as driving method thereof, grid electrode driving device and display device | |
| CN104952406B (en) | Shift register and its driving method, gate driving circuit and display device | |
| CN105096808B (en) | Shift register cell and its driving method, gate driving circuit and display device | |
| CN106910452B (en) | Shift register cell, its driving method, gate driving circuit and display device | |
| CN106504720A (en) | Shift register cell and its driving method, gate drive apparatus and display device | |
| CN106683632B (en) | Shift register, gate driving circuit and its driving method, display device | |
| CN106448536A (en) | Shifting register, grid driving circuit, display panel and driving method | |
| CN106228927A (en) | Shift register cell, driving method, gate driver circuit and display device | |
| CN108806628A (en) | Shift register cell and its driving method, gate driving circuit and display device | |
| CN103208263A (en) | Shift register, display device, gate drive circuit and driving method | |
| CN105869588B (en) | GOA circuits based on LTPS semiconductor thin-film transistors | |
| CN105261341B (en) | A kind of gate driving circuit and display device | |
| CN103503057A (en) | Scanning signal line driving circuit, display device provided therewith, and scanning signal line driving method | |
| CN108269539B (en) | Shift register cell, gate driving circuit and abnormal conditions processing method | |
| CN106157874A (en) | Shift register cell, driving method, gate driver circuit and display device | |
| CN104715730B (en) | A kind of gate driving circuit and display device | |
| CN106504719A (en) | Shift register cell, driving method, gate driver circuit and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |