CN106683632A - Shifting register, gate drive circuit and driving method and display device thereof - Google Patents
Shifting register, gate drive circuit and driving method and display device thereof Download PDFInfo
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- CN106683632A CN106683632A CN201710136096.8A CN201710136096A CN106683632A CN 106683632 A CN106683632 A CN 106683632A CN 201710136096 A CN201710136096 A CN 201710136096A CN 106683632 A CN106683632 A CN 106683632A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/06—Details of flat display driving waveforms
- G09G2310/061—Details of flat display driving waveforms for resetting or blanking
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/04—Maintaining the quality of display appearance
- G09G2320/043—Preventing or counteracting the effects of ageing
- G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Shift Register Type Memory (AREA)
Abstract
The invention provides a shifting register, a gate drive circuit and a driving method and a display device thereof. The problem that a liquid crystal display panel in an existing GOA drive circuit produce AD and poor display due to too high upward pull node potential can be solved. The shifting register comprises an input module, an output module and a voltage reducing module, wherein the input module is used for charging an upward pull node to reach first potential according to a signal input at the signal input end at an input stage, the output module is used for upward pulling the potential of the upward pull node to reach second potential at an output stage, the voltage reducing module is used for upward pulling the potential of the upward pull node to reach the second potential and then downward pulling the potential of the upward pull node to reach third potential at the output stage, and the third potential is greater than the first potential. The output module is further used for outputting a first clock signal input from a first clock signal input end through the signal output end under the control of the upward pull node at the output stage.
Description
Technical field
The invention belongs to display technology field, and in particular to a kind of shift register, gate driver circuit and its driving side
Method, display device.
Background technology
Generally, display panels are made up of vertically and horizontally array picture element matrix, during display, raster data model
Circuit is used to produce the gated sweep voltage of pixel, and by gate driver circuit gated sweep signal is exported, and progressively scans each picture
Element.
In the prior art, the drive circuit of liquid crystal panel in liquid crystal panel periphery by arranging integrated circuit
(Integrated Circuit, IC) is achieved.By contrast, GOA (Gate On Array) is a kind of by raster data model electricity
Road is integrated in the technology on array base palte, and each GOA unit has one by multiple thin film transistor (TFT)s and thin-film capacitor device structure
Into shift register scanning signal is passed to successively next GOA unit, line by line open thin film transistor (TFT) switch, complete picture
The data-signal input of plain unit.
Using GOA drive circuits, GOA unit is made either directly on array base palte, Gate can be saved and drive IC, reduced
Production cost, meanwhile, save Gate IC bonding techniques, the yield of product is improved, and facilitate implementation narrow frame.Cause
And, GOA drive circuits have obtained increasingly being widely applied.
Existing GOA unit by clock signal (CLK) realize arraying bread board per a line displacement export, lastrow it is defeated
Go out signal as the input signal of next line, the reset signal of the output signal of next line as lastrow.But when every a line
During signal output, because the bootstrap effect of the electric capacity in GOA drive circuits can cause the current potential moment of pull-up node (PU) to rise a height of
The twice of output voltage, so that the characteristic curve of TFT devices that grid is connected with PU points drifts about, affects part TFT devices
The normal work of part, in turn results in liquid crystal panel generation picture and shows that the display such as abnormal (AD) is bad.
The content of the invention
It is contemplated that at least solving one of technical problem present in prior art, it is proposed that one kind can avoid because
The too high caused liquid crystal panel of pull-up node current potential in GOA drive circuits produces AD etc. and shows bad shift register, grid
Pole drive circuit and its driving method, display device.
It is a kind of shift register to solve the technical scheme that adopted of present invention problem, including input module, output
Module, voltage reduction module；
The input module connection signal input part and pull-up node；
The output module connects the first clock signal input terminal, signal output part, voltage reduction module and pull-up node；
The voltage reduction module is also connected with pull-up node and signal output part；
The pull-up node is the node connected between input module, output module and voltage reduction module；
The input module, in input phase, according to the signal that the signal input part is input into, to the pull-up
Node charges to the first current potential；
The output module, in the output stage, the current potential of the pull-up node being pulled to into the second current potential；
The voltage reduction module, in the output stage, the current potential of the pull-up node to be pulled to after the second current potential, by institute
The current potential for stating pull-up node is pulled low to the 3rd current potential from second current potential, wherein, the 3rd current potential is more than the first current potential；
The output module, was additionally operable in the output stage, under the control of the pull-up node, by first clock letter
The first clock signal that number input is input into, is exported by the signal output part.
Wherein, the voltage reduction module includes switching transistor, the first pole connection storage electricity of the switching transistor
The first end of appearance and the pull-up node, the second pole of the switching transistor connects control pole, the institute of the switching transistor
State the second end of storage capacitance and the signal output part, the control pole of the switching transistor connects the of the storage capacitance
Two ends and the signal output part.
Wherein, the input module includes the first transistor, and the first pole of the first transistor connects signal input part,
The second pole connection pull-up node of the first transistor.
Wherein, the output module includes third transistor and storage capacitance；
First pole of the third transistor connects the first clock signal input terminal, and the second pole of the third transistor connects
Connect the second end and the voltage reduction module of the storage capacitance, the control pole of the third transistor connects the pull-up node and described
The first end of storage capacitance.
Wherein, the shift register also includes：It is output reseting module, pull-up node reseting module, drop-down module, drop-down
Control module, noise reduction module and boost module；
The output reseting module connection reset signal input, the first signal input part and signal output part；It is described defeated
The signal for going out reseting module for the signal output part to be exported resets；
The pull-up node reseting module connection reset signal input, the first signal input part and the pull-up node；
The pull-up node reseting module is used to that the current potential of the pull-up node to reset；
The drop-down control module connection pull-down node and second clock signal input part, the drop-down control module is used for
The current potential of the pull-down node is controlled according to the second clock signal that the second clock signal input part is input into, it is described drop-down
Node is the tie point of the drop-down control module and the drop-down module；
The drop-down module connects the pull-down node, the pull-up node, drop-down control module and the first signal input
End, the drop-down module is used under the control of the current potential of the pull-up node, is input into by first signal input part
The first signal the current potential of the pull-down node is carried out it is drop-down；
The noise reduction module connection input module, the first signal input part, pull-down node, pull-up node, output module, letter
Number output end and second clock signal input part；The noise reduction module is used for the first letter being input into by the first signal input part
Number reduce the output noise of pull-up node and signal output part；
The boost module connection signal input part, input module, second clock signal input part and pull-up node；It is described
Boost module is used for the letter that second clock signal is input into signal input part being input into according to second clock signal input part
Number boosted.
Wherein, the output reseting module includes the 4th transistor, the first pole connection step-down mould of the 4th transistor
Block, output module and signal output part, the second pole of the 4th transistor connects the first signal input part, the 4th crystal
The control pole connection reset signal input of pipe.
Wherein, the pull-up node reseting module includes transistor seconds, the first pole connection institute of the transistor seconds
Pull-up node is stated, the second pole of the transistor seconds connects the first signal input part, and the control pole of the transistor seconds connects
Connect reset signal input.
Wherein, the drop-down module includes the 6th transistor and the 8th transistor；
First pole of the 6th transistor connects the pull-down node, and the second pole connection of the 6th transistor is described
First signal input part, the control pole of the 6th transistor connects the pull-up node；
First pole of the 8th transistor connects the drop-down control module, the second pole connection of the 8th transistor
First signal input part, the control pole of the 8th transistor connects the pull-up node.
Wherein, the drop-down control module includes the 5th transistor, the 9th transistor and drop-down control node；
First pole of the 5th transistor connects the first pole of the 9th transistor and second clock signal input part,
Second pole of the 5th transistor connects the pull-down node, and the control pole of the 5th transistor connects the drop-down control
Node；
Second pole of the 9th transistor connects the drop-down control node, the control pole connection of the 9th transistor
The second clock signal input part.
Wherein, the noise reduction module includes the tenth transistor, the 11st transistor and the tenth two-transistor；
The first pole connection input module of the tenth transistor and pull-up node, the second pole of the tenth transistor connects
First signal input part is connect, the control pole of the tenth transistor connects the pull-down node；
The first pole connection output module and signal output part of the 11st transistor, the of the 11st transistor
Two poles connect first signal input part, and the control pole of the 11st transistor connects the pull-down node；
First pole of the tenth two-transistor connects the signal output part, and the second pole of the tenth two-transistor connects
First signal input part is connect, the control pole of the tenth two-transistor connects the second clock signal input part.
Used as another technical scheme, the present invention also provides a kind of gate driver circuit, and the gate driver circuit includes many
The shift register of the above-mentioned any one of level,
The signal that the gate drive signal signal generating unit of shift register described in per one-level is exported is used as the shift LD
The input signal of the signal input part of the next stage shift register of device；
The signal exported per each signal output part of shift register described in one-level be used to driving a grid line and
As the reset signal at the reset signal end of the upper level shift register of the shift register.
Used as another technical scheme, the present invention also provides a kind of display device, and display device includes above-mentioned described grid
Pole drive circuit.
Used as another technical scheme, the present invention also provides a kind of driving method of gate driver circuit, the raster data model
Circuit includes the shift register of multistage above-mentioned any one, and the driving method includes：
In the signal that input phase, the input module are input into according to the signal input part, to the pull-up node
Charge to the first current potential；
In the output stage, the current potential of the pull-up node is pulled to the second current potential by the output module, and on described
Under drawing the control of node, the first clock signal that first clock signal input terminal is input into, by the signal output
End is exported；The current potential of the pull-up node is pulled low to the 3rd current potential by the voltage reduction module from second current potential, wherein,
3rd current potential is more than the first current potential.
When wherein, using above-mentioned shift register, the driving method of the gate driver circuit also includes：
The reset noise reduction stage：The signal that signal output part is exported and the current potential of pull-up node reset.
In shift register, gate driver circuit and its driving method, the display device of the present invention, the shift register bag
Input module, output module, voltage reduction module are included, in the output stage, the voltage reduction module can be pulled up in the current potential of pull-up node
To the second current potential, the current potential of pull-up node is pulled low to into the 3rd current potential from the second current potential, so that the voltage quilt of pull-up node
It is rapid to reduce, drifted about with the TFT device property curves for avoiding grid from being connected with pull-up node, and then make TFT devices normal
Work, shows bad to avoid liquid crystal panel from producing AD etc..
Description of the drawings
Fig. 1 is the structural representation of the shift register of embodiments of the invention 1；
Fig. 2 is the circuit theory diagrams of the shift register of embodiments of the invention 1；
Fig. 3 is the working timing figure of the shift register of embodiments of the invention 1；
Fig. 4 is the structural representation of the shift register of embodiments of the invention 2；
Fig. 5 is the circuit theory diagrams of the shift register of embodiments of the invention 2；
Fig. 6 is the working timing figure of the shift register of embodiments of the invention 2；
Fig. 7 is the structural representation of the gate driver circuit of embodiments of the invention 3；
Fig. 8 is the schematic flow sheet of the driving method of the gate driver circuit of embodiments of the invention 5；
Wherein, reference is：1st, input module；2nd, output module；3rd, voltage reduction module；4th, reseting module is exported；5th, on
Draw node reset module；6th, drop-down module；7th, drop-down control module；8th, noise reduction module；9th, boost module；INPUT, signal input
End；PU, pull-up node；CLKA, the first clock signal input terminal；OUTPUT, signal output part；RESET, reset signal input
End；VSS, the first signal input part；PD, pull-down node；CLKB, second clock signal input part；PD_CN, drop-down control node.
Specific embodiment
To make those skilled in the art more fully understand technical scheme, below in conjunction with the accompanying drawings and specific embodiment party
Formula is described in further detail to the present invention.
The transistor for being adopted in the embodiment of the present invention can be thin film transistor (TFT) or FET or other characteristics
Identity unit, due to adopt transistor source electrode and drain electrode be symmetrical, so its source electrode, drain electrode be not different.
It is source electrode and the drain electrode for distinguishing transistor in the embodiment of the present invention, a wherein pole is referred to as into the first pole, another pole is referred to as second
Pole, grid is referred to as control pole.In addition distinguish and transistor can be divided into N-type and p-type, following examples according to the characteristic of transistor
In illustrated with N-type transistor, when using N-type transistor, the source electrode of the first extremely N-type transistor, the second extremely N
The drain electrode of transistor npn npn, during grid input high level, source, drain electrode conducting, P-type transistor is then contrary.It is envisioned that using
It is that those skilled in the art can readily occur under the premise of creative work is not paid that P-type transistor is realized, therefore
It is in the protection domain of the embodiment of the present invention.
Embodiment 1：
Fig. 1 to Fig. 3 is refer to, the present embodiment provides a kind of shift register, including input module 1, output module 2, drop
Die block 3.
As shown in figure 1, the connection signal input part INPUT of input module 1 and pull-up node PU；The connection of output module 2 first
Clock signal input terminal CLKA, signal output part OUTPUT, voltage reduction module 3 and pull-up node PU；Voltage reduction module 3 is also connected with pull-up
Node PU and signal output part OUTPUT；Pull-up node PU is connection between input module 1, output module 2 and voltage reduction module 3
Node.
Input module 1 is used in input phase, according to the signal that signal input part INPUT is input into, to pull-up node PU
Charge to the first current potential.
Output module 2 was used in the output stage, and the current potential of pull-up node PU is pulled to into the second current potential.
Voltage reduction module 3 was used in the output stage, and the current potential of pull-up node PU is pulled to after the second current potential, by pull-up node
The current potential of PU is pulled low to the 3rd current potential from the second current potential, wherein, the 3rd current potential is more than the first current potential.
Output module 2 was additionally operable in the output stage, under the control of pull-up node PU, by the first clock signal input terminal
The first clock signal that CLKA is input into, is exported by signal output part OUTPUT.
From figure 1 it appears that input module 1, output module 2 and voltage reduction module 3 are connected with pull-up node PU.Defeated
Enter the stage, input module 1 inputs a signal into the signal transmission for holding INPUT to be input into pull-up node PU, so that pull-up node PU
Current potential rise to the first current potential；In the moment that the output stage starts, output module 2 is electric by first by the current potential of pull-up node PU
Position is pulled to the second current potential；Subsequently (being still the output stage), voltage reduction module 3 drags down the current potential of pull-up node PU from the second current potential
To the 3rd current potential, wherein, the 3rd current potential is more than the first current potential.Now, because voltage reduction module 3 has dragged down the electricity of pull-up node PU
Position, can avoid the TFT device property curves that grid is connected with pull-up node from drifting about, and then make TFT proper device operations,
Show bad to avoid liquid crystal panel from producing AD etc..
It should be noted that in general, the 3rd current potential is more than the first current potential, if but signal output part OUTPUT
Output time long enough, the 3rd current potential is possible to be equal to the first current potential, will not be described here.
As shown in Fig. 2 wherein, voltage reduction module 3 includes switching transistor TFT1, and the first pole of switching transistor TFT1 connects
Output module 2 and pull-up node PU, the control pole of the second pole connecting valve transistor TFT1 of switching transistor TFT1, output mould
Block 2 and signal output part OUTPUT, the control pole connection output module 2 of switching transistor TFT1 and signal output part OUTPUT.
Wherein, input module 1 includes the first transistor M1, the first pole connection signal input part of the first transistor M1
Second pole connection pull-up node PU of INPUT, the first transistor M1.
Wherein, output module 2 includes third transistor M3 and storage capacitance C1；The first pole connection the of third transistor M3
One clock signal input terminal CLKA, the second end of the second pole connection storage capacitance C1 of third transistor M3 and voltage reduction module 3, the
Control pole connection pull-up node PU and the first end of storage capacitance C1 of three transistor M3.
Specifically, according to sequential chart as shown in Figure 3, the operation principle of the shift LD of the present embodiment is illustrated.
Input phase：Signal input part INPUT input high levels, the first transistor M1 is opened, and makes the electricity of pull-up node PU
Position rises to the first current potential, meanwhile, storage capacitance C1 is charged；In addition, third transistor M3 is opened, now, when first
First clock signal (low level) of clock signal input part CLKA inputs is exported from signal output part OUTPUT.
The output stage：Signal input part INPUT input low levels, the first transistor M1 is closed, but due to storage capacitance C1
Presence, the current potential of pull-up node PU continues to be increased to the second current potential (V1), now, the first clock signal input terminal CLKA inputs
First clock signal (high level), third transistor M3 is opened, and the first clock signal (high level) is from signal output part OUTPUT
Output (the as signal of the signal input part INPUT inputs of next line), and due to the boot strap of storage capacitance C1, pull-up section
The voltage of point PU rises the twice of the voltage of a height of signal output part OUTPUT outputs, while switching transistor TFT1 is opened, makes
Obtain pull-up node PU and loop is constituted by switching transistor TFT1 with signal output part OUTPUT, make the current potential of pull-up node PU fast
Speed drops to the 3rd current potential (V1 '), i.e. V1 ' ＜ V1.
That is, at a period of time after the output stage starts, because switching transistor TFT1 is opened, having dragged down defeated
Go out the current potential that the stage starts moment pull-up node PU, it is bent so as to avoid the TFT device properties that grid is connected with pull-up node PU
Line drifts about, and then makes TFT proper device operations, shows bad to avoid liquid crystal panel from producing AD etc..
The shift register of the present embodiment, including input module 1, output module 2, voltage reduction module 3, in the output stage, should
Voltage reduction module 3 can be electric from second by the current potential of pull-up node PU after the current potential of pull-up node PU is pulled to the second current potential
Position is pulled low to the 3rd current potential, so that the voltage of pull-up node is reduced rapidly, to avoid what grid was connected with pull-up node PU
TFT device property curves drift about, and then make TFT proper device operations, show bad to avoid liquid crystal panel from producing AD etc..
Embodiment 2：
Fig. 4 to Fig. 6 is refer to, the present embodiment provides a kind of shift register, and it has the shift register with embodiment 1
Similar structure, its difference is that the shift register of the present embodiment also includes：Output reseting module 4, pull-up node reset mould
Block 5, drop-down module 6, drop-down control module 7, noise reduction module 8 and boost module 9.
As shown in figure 4, the output connection reset signal input RESET of reseting module 4, the first signal input part VSS and letter
Number output end OUTPUT；The signal that output reseting module 4 is used to export signal output part OUTPUT resets.
As shown in figure 5, wherein, output reseting module 4 includes the 4th transistor M4, and first pole of the 4th transistor M4 connects
Voltage reduction module 3, output module 2 and signal output part OUTPUT, second pole of the 4th transistor M4 connects the first signal input part
The control pole connection reset signal input RESET of VSS, the 4th transistor M4.
The connection reset signal input RESET of pull-up node reseting module 5, the first signal input part VSS and pull-up node
PU；Pull-up node reseting module 5 is used to that the current potential of pull-up node PU to reset.
Wherein, pull-up node reseting module 5 includes transistor seconds M2, the first pole connection pull-up section of transistor seconds M2
Second pole of point PU, transistor seconds M2 connects the first signal input part VSS, and the control pole connection of transistor seconds M2 resets and believes
Number input RESET.
Drop-down control module 7 connects pull-down node PD and second clock signal input part CLKB, and drop-down control module 7 is used for
The current potential of pull-down node PD, pull-down node PD are controlled according to the second clock signal that second clock signal input part CLKB is input into
For the tie point of drop-down control module 7 and drop-down module 6.
Wherein, drop-down control module 7 includes the 5th transistor M5, the 9th transistor M9 and drop-down control node PD_CN.
First pole of the 5th transistor M5 connects first pole of the 9th transistor M9 and second clock signal input part CLKB,
Second pole connection pull-down node PD of the 5th transistor M5, the control pole of the 5th transistor M5 connects drop-down control node PD_CN.
Second pole of the 9th transistor M9 connects drop-down control node PD_CN, the control pole connection of the 9th transistor M9 the
Two clock signal input terminal CLKB.
Connection pull-down node PD of drop-down module 6, pull-up node PU, the signal input part VSS of drop-down control module 7 and first,
Drop-down module 6 is used under the control of the current potential of pull-up node PU, the first signal being input into by the first signal input part VSS
The current potential of pull-down node PD is carried out drop-down.
Wherein, drop-down module 6 includes the 6th transistor M6 and the 8th transistor M8.
First pole connection pull-down node PD of the 6th transistor M6, the second pole first signal of connection of the 6th transistor M6 is defeated
Enter and hold VSS, control pole connection pull-up node PU of the 6th transistor M6.
First pole of the 8th transistor M8 connects drop-down control module 7, and the second pole connection first of the 8th transistor M8 is believed
Control pole connection pull-up node PU of number input VSS, the 8th transistor M8.
The connection input module 1 of noise reduction module 8, the first signal input part VSS, pull-down node PD, pull-up node PU, output mould
Block 2, signal output part OUTPUT and second clock signal input part CLKB；Noise reduction module 8 is used to pass through the first signal input part
The first signal that VSS is input into reduces the output noise of pull-up node PU and signal output part OUTPUT.
Wherein, noise reduction module 8 includes the tenth transistor M10, the 11st transistor M11 and the tenth two-transistor M12.
The first pole connection input module 1 of the tenth transistor M10 and pull-up node PU, second pole of the tenth transistor M10
Connect the first signal input part VSS, control pole connection pull-down node PD of the tenth transistor M10.
The first pole connection output module 2 of the 11st transistor M11 and signal output part OUTPUT, the 11st transistor
Second pole of M11 connects the first signal input part VSS, control pole connection pull-down node PD of the 11st transistor M11.
The first pole connection signal output part OUTPUT of the tenth two-transistor M12, second pole of the tenth two-transistor M12 connects
Meet the first signal input part VSS, the control pole connection second clock signal input part CLKB of the tenth two-transistor M12.
The connection signal input part INPUT of boost module 9, input module 1, second clock signal input part CLKB and pull-up section
Point PU；Boost module 9 is used for the second clock signal being input into according to second clock signal input part CLKB to signal input part
The signal that INPUT is input into is boosted.
Wherein, boost module 9 includes the 13rd transistor M13, the first pole connection signal input of the 13rd transistor M13
Second pole connection pull-up node PU of end INPUT, the 13rd transistor M13, the control pole connection second of the 13rd transistor M13
Clock signal input terminal CLKB.
Due to the operation principle of input module 1, output module 2 and voltage reduction module 3 in the shift register of the present embodiment
It is same as Example 1, therefore will not be described here.
Specifically, shift LD (output reseting module 4, the pull-up according to sequential chart as shown in Figure 6, to the present embodiment
Node reset module 5, drop-down module 6, drop-down control module 7, noise reduction module 8 and boost module 9) operation principle said
It is bright.In the present embodiment, the first signal input part VSS exports always in a shift register low level.
Input phase：Second clock signal input part CLKB input high levels, the 13rd transistor M13 is opened, with to upper
The current potential for drawing node PU is boosted.
The output stage：Pull-up node PU is high level, and the 6th transistor M6 and the 8th transistor M8 is opened, and makes pull-down node
PD and drop-down control node PD_CN are connected respectively with the first signal input part VSS, make pull-down node PD current potential be pulled down to it is low
Level (drop-down control node PD_CN is also pulled down to low level, to avoid affecting the current potential of pull-down node PD), makes the tenth crystal
Pipe M10 and the 11st transistor M11 is closed, so as to avoid the current potential of pull-up node PU caused by opening because of the tenth transistor M10
Jitter unstable and because of signal output part OUTPUT outputs caused by the 11st transistor M11 unlatchings.
After the output stage, also include：
The reset noise reduction stage：
(1) reset signal input RESET input high levels, transistor seconds M2 is opened, and pull-up node PU passes through second
Transistor M2 is connected with the first signal input part VSS, and the current potential for making pull-up node PU is pulled low to low electricity from the 3rd current potential V1 '
It is flat, resetted with the current potential to pull-up node PU；
(2) reset signal input RESET input high levels, the 4th transistor M4 is opened, and signal output part OUTPUT leads to
Cross the 4th transistor M4 to be connected with the first signal input part VSS, the current potential for making signal output part OUTPUT is pulled to low level, with
The current potential of signal output part OUTPUT is resetted；
(3) first clock signal input terminal CLKA input low levels, due to pull-up node PU be low level, third transistor
M3 is closed, meanwhile, second clock signal input part CLKB input high levels, the 9th transistor M9 is opened, now, second clock letter
Number input CLKB is connected with drop-down control node PD_CN, and the current potential of drop-down control node PD_CN is raised, and makes the 5th transistor
M5 is opened, and pull-down node PD is connected with second clock signal input part CLKB, and the current potential of pull-down node PD is in high level；
(4) current potential of pull-down node PD is in high level, opens the 11st transistor M11, second clock signal input part
CLKB input high levels, open the tenth two-transistor M12, and now, signal output part OUTPUT passes through the 11st transistor M11
It is connected with the tenth two-transistor M12 with the first signal input part VSS, is pulled to the current potential that signal output part OUTPUT is exported low
Level, to reduce the output noise of signal output part OUTPUT；
(5) current potential of pull-down node PD is in high level, opens the tenth transistor M10, and now, pull-up node PU is by the
Ten transistor M10 are connected with the first signal input part VSS, and the current potential for making pull-up node PU is pulled to low level, to reduce pull-up
The output noise of node PU.
It should be noted that in the reset noise reduction stage, above-mentioned (1)-(5) are simultaneous, are not existed successively suitable
Sequence.
The shift register of the present embodiment, including input module 1, output module 2, voltage reduction module 3, in the output stage, should
Voltage reduction module 3 can be electric from second by the current potential of pull-up node PU after the current potential of pull-up node PU is pulled to the second current potential
Position is pulled low to the 3rd current potential, so that the voltage of pull-up node is reduced rapidly, to avoid what grid was connected with pull-up node PU
TFT device property curves drift about, and then make TFT proper device operations, show bad to avoid liquid crystal panel from producing AD etc..
Embodiment 3：
Fig. 7 is refer to, the present embodiment provides a kind of gate driver circuit, and gate driver circuit includes multi-stage embodiment 1
Shift register (as shown in dotted line in Fig. 7).
The signal exported per the gate drive signal signal generating unit of one-level shift register is used as the shift register
The input signal of the signal input part of next stage shift register；Exported per each signal output part of one-level shift register
Signal be used to drive grid line and the reset signal end as the upper level shift register of the shift register to answer
Position signal.
It should be noted that the signal that the output end of every grade of shift register is exported is aobvious with display floater for driving
Show the grid line that region (i.e. AA regions) connects.
The gate driver circuit of the present embodiment, including the shift register of multi-stage embodiment 1, detailed description can refer to enforcement
The shift register of example 1, will not be described here.
The gate driver circuit of the present embodiment, including the shift register of multi-stage embodiment 1, the shift register includes defeated
Enter module, output module, voltage reduction module, in the output stage, the voltage reduction module can be pulled to the in the current potential of pull-up node
After two current potentials, the current potential of pull-up node is pulled low to into the 3rd current potential from the second current potential, so that the voltage of pull-up node is rapid
Reduce, drifted about with the TFT device property curves for avoiding grid from being connected with pull-up node, and then make TFT proper device operations,
Show bad to avoid liquid crystal panel from producing AD etc..
Embodiment 4：
A kind of display device is present embodiments provided, display device includes the gate driver circuit of embodiment 2.Display device
Can be：Display panels, Electronic Paper, mobile phone, panel computer, television set, display, notebook computer, DPF, lead
Any product with display function or the parts such as boat instrument.
The display device of the present embodiment, including the gate driver circuit of embodiment 2, shift register therein includes input
Module, output module, voltage reduction module, in the output stage, the voltage reduction module can be pulled to second in the current potential of pull-up node
After current potential, the current potential of pull-up node is pulled low to into the 3rd current potential from the second current potential, so that the voltage of pull-up node is dropped rapidly
It is low, drifted about with the TFT device property curves for avoiding grid from being connected with pull-up node, and then TFT proper device operations are made, with
Avoid liquid crystal panel from producing AD etc. and show bad.
Embodiment 5：
Fig. 8 is refer to, the present embodiment provides a kind of driving method of gate driver circuit, and gate driver circuit includes multistage
The shift register of embodiment 1 or 2, driving method includes：
In the signal that input phase, input module are input into according to signal input part, first is charged to pull-up node electric
Position.
In the output stage, the current potential of pull-up node is pulled to the second current potential by output module, and in the control of pull-up node
Under, the first clock signal that the first clock signal input terminal is input into is exported by signal output part；Voltage reduction module will
The current potential of pull-up node is pulled low to the 3rd current potential from the second current potential, wherein, the 3rd current potential is more than the first current potential.
When gate driver circuit includes the shift register of multi-stage embodiment 2, driving method also includes：
The reset noise reduction stage：The signal that signal output part is exported and the current potential of pull-up node reset.
The driving method of the gate driver circuit of the present embodiment, for driving the gate driver circuit of embodiment 2, in detail
Description can refer to the gate driver circuit of embodiment 2, will not be described here.
The driving method of the gate driver circuit of the present embodiment, for driving the gate driver circuit of embodiment 2, wherein
Shift register include input module, output module, voltage reduction module, output the stage, the voltage reduction module can pull-up section
The current potential of point is pulled to after the second current potential, and the current potential of pull-up node is pulled low to into the 3rd current potential from the second current potential, so that on
Drawing the voltage of node is reduced rapidly, is drifted about with the TFT device property curves for avoiding grid from being connected with pull-up node, and then
TFT proper device operations are made, shows bad to avoid liquid crystal panel from producing AD etc..
It is understood that the embodiment of above principle being intended to be merely illustrative of the present and the exemplary enforcement for adopting
Mode, but the invention is not limited in this.For those skilled in the art, in the essence without departing from the present invention
In the case of god and essence, various modifications and improvement can be made, these modifications and improvement are also considered as protection scope of the present invention.
Claims (14)
1. a kind of shift register, it is characterised in that including input module, output module, voltage reduction module；
The input module, connection signal input part and pull-up node, in input phase, according to the signal input part institute
The signal of input, to the pull-up node the first current potential is charged to；
The output module connects the first clock signal input terminal, signal output part, voltage reduction module and pull-up node, for defeated
Go out the stage, the current potential of the pull-up node is pulled to into the second current potential；
The voltage reduction module is also connected with pull-up node and signal output part, in output stage, the current potential of the pull-up node
After being pulled to the second current potential, the current potential of the pull-up node is pulled low to into the 3rd current potential from second current potential, wherein, the 3rd
Current potential is more than the first current potential；
The output module, was additionally operable in the output stage, under the control of the pull-up node, first clock signal is defeated
Enter the first be input into clock signal of end, exported by the signal output part.The pull-up node is input module, defeated
Go out the node connected between module and voltage reduction module.
2. shift register according to claim 1, it is characterised in that the voltage reduction module includes switching transistor, institute
The first pole for stating switching transistor connects the output module and the pull-up node, the second pole connection of the switching transistor
The control pole of the switching transistor, the output module and the signal output part, the control pole of the switching transistor connects
Connect the output module and the signal output part.
3. shift register according to claim 1, it is characterised in that the input module includes the first transistor, institute
State the first pole connection signal input part of the first transistor, the second pole connection pull-up node of the first transistor.
4. shift register according to claim 1, it is characterised in that the output module includes third transistor and deposits
Storing up electricity is held；
First pole of the third transistor connects the first clock signal input terminal, the second pole connection institute of the third transistor
The second end and the voltage reduction module of storage capacitance are stated, the control pole of the third transistor connects the pull-up node and the storage
The first end of electric capacity.
5. the shift register according to Claims 1-4 any one, it is characterised in that also include：Output reset mould
Block, pull-up node reseting module, drop-down module, drop-down control module, noise reduction module and boost module；
The output reseting module connection reset signal input, the first signal input part and signal output part；The output is multiple
The signal that position module is used to export the signal output part resets；
The pull-up node reseting module connection reset signal input, the first signal input part and the pull-up node；It is described
Pull-up node reseting module is used to that the current potential of the pull-up node to reset；
The drop-down control module connection pull-down node and second clock signal input part, the drop-down control module is used for basis
The second clock signal that the second clock signal input part is input into controls the current potential of the pull-down node, the pull-down node
For the tie point of the drop-down control module and the drop-down module；
The drop-down module connects the pull-down node, the pull-up node, drop-down control module and the first signal input part, institute
Stating drop-down module is used under the control of the current potential of the pull-up node, first be input into by first signal input part
Signal carries out the current potential of the pull-down node drop-down；
The noise reduction module connection input module, the first signal input part, pull-down node, pull-up node, output module, signal are defeated
Go out end and second clock signal input part；The noise reduction module is used for the first signal drop being input into by the first signal input part
The output noise of low pull-up node and signal output part；
The boost module connection signal input part, input module, second clock signal input part and pull-up node；The boosting
The signal that second clock signal is input into signal input part that module is used to be input into according to second clock signal input part enters
Row boosting.
6. shift register according to claim 5, it is characterised in that the output reseting module includes the 4th crystal
Pipe, the first pole connection voltage reduction module of the 4th transistor, output module and signal output part, the of the 4th transistor
Two poles connect the first signal input part, the control pole connection reset signal input of the 4th transistor.
7. shift register according to claim 5, it is characterised in that the pull-up node reseting module includes that second is brilliant
Body pipe, the first pole of the transistor seconds connects the pull-up node, and the second pole connection first of the transistor seconds is believed
Number input, the control pole connection reset signal input of the transistor seconds.
8. shift register according to claim 5, it is characterised in that the drop-down module includes the 6th transistor and the
Eight transistors；
First pole of the 6th transistor connects the pull-down node, the second pole connection described first of the 6th transistor
Signal input part, the control pole of the 6th transistor connects the pull-up node；
First pole of the 8th transistor connects the drop-down control module, and the second pole connection of the 8th transistor is described
First signal input part, the control pole of the 8th transistor connects the pull-up node.
9. shift register according to claim 5, it is characterised in that the drop-down control module includes the 5th crystal
Pipe, the 9th transistor and drop-down control node；
First pole of the 5th transistor connects the first pole of the 9th transistor and second clock signal input part, described
Second pole of the 5th transistor connects the pull-down node, the control pole connection drop-down control section of the 5th transistor
Point；
Second pole of the 9th transistor connects the drop-down control node, and the control pole connection of the 9th transistor is described
Second clock signal input part.
10. shift register according to claim 5, it is characterised in that the noise reduction module include the tenth transistor, the
11 transistors and the tenth two-transistor；
The first pole connection input module of the tenth transistor and pull-up node, the second pole connection institute of the tenth transistor
The first signal input part is stated, the control pole of the tenth transistor connects the pull-down node；
The first pole connection output module of the 11st transistor and signal output part, the second pole of the 11st transistor
Connect first signal input part, the control pole of the 11st transistor connects the pull-down node；
First pole of the tenth two-transistor connects the signal output part, the second pole connection institute of the tenth two-transistor
The first signal input part is stated, the control pole of the tenth two-transistor connects the second clock signal input part.
11. a kind of gate driver circuits, it is characterised in that the gate driver circuit includes appointing in multistage claim 1 to 10
The shift register of meaning one,
The signal that the gate drive signal signal generating unit of shift register described in per one-level is exported is used as the shift register
The input signal of the signal input part of next stage shift register；
The signal that each signal output part of shift register described in per one-level is exported is used to drive a grid line and conduct
The reset signal at the reset signal end of the upper level shift register of the shift register.
12. a kind of display devices, it is characterised in that display device includes the described gate driver circuit of claim 11.
13. a kind of driving methods of gate driver circuit, it is characterised in that the gate driver circuit includes multistage claim
The shift register of any one in 1 to 10, the driving method includes：
In the signal that input phase, the input module are input into according to the signal input part, the pull-up node is charged
To the first current potential；
In the output stage, the current potential of the pull-up node is pulled to the second current potential by the output module, and in the pull-up section
Under the control of point, the first clock signal that first clock signal input terminal is input into is entered by the signal output part
Row output；The current potential of the pull-up node is pulled low to the 3rd current potential by the voltage reduction module from second current potential, wherein, the 3rd
Current potential is more than the first current potential.
The driving method of 14. gate driver circuits according to claim 13, it is characterised in that using claim 5 institute
During the shift register stated, the driving method also includes：
The reset noise reduction stage：The signal that signal output part is exported and the current potential of pull-up node reset.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710136096.8A CN106683632B (en) | 2017-03-08 | 2017-03-08 | Shift register, gate driving circuit and its driving method, display device |
| PCT/CN2017/114582 WO2018161658A1 (en) | 2017-03-08 | 2017-12-05 | Shifting register, gate driving circuit and driving method thereof, display device |
| US16/064,834 US20210209993A1 (en) | 2017-03-08 | 2017-12-05 | Shift register, gate driver-on-array circuit and driving method thereof, display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710136096.8A CN106683632B (en) | 2017-03-08 | 2017-03-08 | Shift register, gate driving circuit and its driving method, display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106683632A true CN106683632A (en) | 2017-05-17 |
| CN106683632B CN106683632B (en) | 2019-04-12 |
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|---|---|---|---|
| CN201710136096.8A Active CN106683632B (en) | 2017-03-08 | 2017-03-08 | Shift register, gate driving circuit and its driving method, display device |
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| Country | Link |
|---|---|
| US (1) | US20210209993A1 (en) |
| CN (1) | CN106683632B (en) |
| WO (1) | WO2018161658A1 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107369428A (en) * | 2017-09-22 | 2017-11-21 | 京东方科技集团股份有限公司 | A kind of shift register and its driving method, gate driving circuit |
| WO2018161658A1 (en) * | 2017-03-08 | 2018-09-13 | 京东方科技集团股份有限公司 | Shifting register, gate driving circuit and driving method thereof, display device |
| CN108648718A (en) * | 2018-08-01 | 2018-10-12 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
| CN109147704A (en) * | 2018-09-28 | 2019-01-04 | 合肥鑫晟光电科技有限公司 | Shift register cell, gate driving circuit, display device and driving method |
| CN109410885A (en) * | 2018-12-27 | 2019-03-01 | 信利半导体有限公司 | Scan drive circuit, image element array substrates and display panel |
| WO2020125432A1 (en) * | 2018-12-19 | 2020-06-25 | 惠科股份有限公司 | Shift register and display apparatus |
| CN111554229A (en) * | 2020-06-08 | 2020-08-18 | 京东方科技集团股份有限公司 | Shift register, display panel and display device |
| CN115019741A (en) * | 2022-04-19 | 2022-09-06 | 京东方科技集团股份有限公司 | Array gate driving unit, circuit and driving method and display device |
| CN115019743A (en) * | 2022-06-29 | 2022-09-06 | 惠科股份有限公司 | Display panel's drive circuit, array substrate and display panel |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140168044A1 (en) * | 2012-12-14 | 2014-06-19 | Hefei Boe Optoelectronics Technology Co., Ltd. | Shift register unit, gate driving circuit and display device |
| CN104167192A (en) * | 2014-07-22 | 2014-11-26 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit and display device |
| CN105931595A (en) * | 2016-07-13 | 2016-09-07 | 京东方科技集团股份有限公司 | Shift register unit, driving method, grid drive circuit, and display device |
| CN106128364A (en) * | 2016-07-15 | 2016-11-16 | 京东方科技集团股份有限公司 | Shift register cell and driving method, gate driver circuit, display device |
| CN106356018A (en) * | 2016-11-11 | 2017-01-25 | 京东方科技集团股份有限公司 | Shift register unit, shift register and display device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100470682C (en) * | 2006-01-19 | 2009-03-18 | 奇晶光电股份有限公司 | Shift temporary storage and plane display device using it |
| TWI465039B (en) * | 2009-10-15 | 2014-12-11 | Au Optronics Corp | Shift register circuit |
| CN105632451A (en) * | 2016-04-08 | 2016-06-01 | 京东方科技集团股份有限公司 | Shifting register unit, driving method, gate drive circuit and display device |
| CN106683632B (en) * | 2017-03-08 | 2019-04-12 | 合肥鑫晟光电科技有限公司 | Shift register, gate driving circuit and its driving method, display device |
-
2017
- 2017-03-08 CN CN201710136096.8A patent/CN106683632B/en active Active
- 2017-12-05 WO PCT/CN2017/114582 patent/WO2018161658A1/en active Application Filing
- 2017-12-05 US US16/064,834 patent/US20210209993A1/en not_active Abandoned
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140168044A1 (en) * | 2012-12-14 | 2014-06-19 | Hefei Boe Optoelectronics Technology Co., Ltd. | Shift register unit, gate driving circuit and display device |
| CN104167192A (en) * | 2014-07-22 | 2014-11-26 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit and display device |
| CN105931595A (en) * | 2016-07-13 | 2016-09-07 | 京东方科技集团股份有限公司 | Shift register unit, driving method, grid drive circuit, and display device |
| CN106128364A (en) * | 2016-07-15 | 2016-11-16 | 京东方科技集团股份有限公司 | Shift register cell and driving method, gate driver circuit, display device |
| CN106356018A (en) * | 2016-11-11 | 2017-01-25 | 京东方科技集团股份有限公司 | Shift register unit, shift register and display device |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018161658A1 (en) * | 2017-03-08 | 2018-09-13 | 京东方科技集团股份有限公司 | Shifting register, gate driving circuit and driving method thereof, display device |
| CN107369428B (en) * | 2017-09-22 | 2019-12-03 | 京东方科技集团股份有限公司 | A kind of shift register and its driving method, gate driving circuit |
| CN107369428A (en) * | 2017-09-22 | 2017-11-21 | 京东方科技集团股份有限公司 | A kind of shift register and its driving method, gate driving circuit |
| JP7315469B2 (en) | 2018-08-01 | 2023-07-26 | 京東方科技集團股▲ふん▼有限公司 | SHIFT REGISTER UNIT AND DRIVING METHOD THEREOF, GATE DRIVE CIRCUIT AND DISPLAY DEVICE |
| CN108648718A (en) * | 2018-08-01 | 2018-10-12 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
| WO2020024641A1 (en) * | 2018-08-01 | 2020-02-06 | 京东方科技集团股份有限公司 | Shift register unit and driving method thereof, gate driving circuit and display device |
| JP2021532525A (en) * | 2018-08-01 | 2021-11-25 | 京東方科技集團股▲ふん▼有限公司Boe Technology Group Co., Ltd. | Shift register unit and its drive method, gate drive circuit and display device |
| US11263953B2 (en) | 2018-08-01 | 2022-03-01 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Shift register unit and drive method thereof, gate drive circuit and display device |
| EP3832637A4 (en) * | 2018-08-01 | 2022-04-27 | BOE Technology Group Co., Ltd. | Shift register unit and driving method thereof, gate driving circuit and display device |
| CN109147704A (en) * | 2018-09-28 | 2019-01-04 | 合肥鑫晟光电科技有限公司 | Shift register cell, gate driving circuit, display device and driving method |
| WO2020125432A1 (en) * | 2018-12-19 | 2020-06-25 | 惠科股份有限公司 | Shift register and display apparatus |
| CN109410885A (en) * | 2018-12-27 | 2019-03-01 | 信利半导体有限公司 | Scan drive circuit, image element array substrates and display panel |
| CN111554229A (en) * | 2020-06-08 | 2020-08-18 | 京东方科技集团股份有限公司 | Shift register, display panel and display device |
| CN111554229B (en) * | 2020-06-08 | 2023-05-05 | 京东方科技集团股份有限公司 | Shifting register, display panel and display device |
| CN115019741A (en) * | 2022-04-19 | 2022-09-06 | 京东方科技集团股份有限公司 | Array gate driving unit, circuit and driving method and display device |
| CN115019743A (en) * | 2022-06-29 | 2022-09-06 | 惠科股份有限公司 | Display panel's drive circuit, array substrate and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| US20210209993A1 (en) | 2021-07-08 |
| WO2018161658A1 (en) | 2018-09-13 |
| CN106683632B (en) | 2019-04-12 |
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