CN107359241B - Vacuum nano pipe field effect transistor and its manufacturing method - Google Patents
Vacuum nano pipe field effect transistor and its manufacturing method Download PDFInfo
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- CN107359241B CN107359241B CN201610307101.2A CN201610307101A CN107359241B CN 107359241 B CN107359241 B CN 107359241B CN 201610307101 A CN201610307101 A CN 201610307101A CN 107359241 B CN107359241 B CN 107359241B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/10—Deposition of organic active material
- H10K71/16—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering
- H10K71/164—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering using vacuum deposition
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H—ELECTRICITY
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
- H10K10/472—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising only inorganic materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/491—Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
- H10K71/231—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers
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- H—ELECTRICITY
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
- H10K85/221—Carbon nanotubes
Abstract
In vacuum nano pipe field effect transistor provided by the invention and its manufacturing method, the vacuum nano pipe transistor of vertical structure is formed by production anodic oxidation constructed of aluminium, to further reduce device size, and promotes the performance of device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of vacuum nano pipe field effect transistor and its manufacturer
Method.
Background technique
In order to reach faster arithmetic speed, bigger data storage amount and more functions, semiconductor chip is to more
High integration direction is developed.Various semiconductor devices, the size including transistor all constantly reduce.By the ruler for reducing transistor
It is very little, increase transistor density, the integrated level of chip is improved, while reducing power consumption, so that chip performance is constantly promoted.
However, transistor cannot be made smaller according to existing manufacturing technology level.As it can be seen that transistor
Physical size has arrived the limit, extremely difficult to improve performance by reducing physical size.For this purpose, having designed and developed in the industry each
The novel transistor of kind is to meet the market requirement, such as carbon nanotube field-effect transistor.Carbon nanotube field-effect transistor is logical
The channel material that conventional MOS FET structure is replaced using Single Carbon Nanotubes or carbon nano pipe array is crossed, it can be to a certain degree
On overcome the limitation of manufacturing condition and further reduce device size degree.Currently, the carbon nano tube field with self-aligning grid
The size of effect transistor (Carbon Nano Tube Field Effect Transistor, abbreviation CNTFET) has been reduced to
20nm, the uniformity for surrounding the grid of carbon nano-tube channel are also consolidated.
However, found during actual manufacture and use, the size of existing carbon nanotube field-effect transistor and
Performance is not met by market demands.How to further reduce the size of vacuum nano pipe field effect transistor and improves device
Performance is still those skilled in the art's technical problem urgently to be resolved.
Summary of the invention
It is existing to solve the purpose of the present invention is to provide a kind of vacuum nano pipe field effect transistor and its manufacturing method
The problem of size and performance of vacuum nano pipe field effect transistor are unable to satisfy market demands in technology.
To solve the above problems, the present invention provides a kind of manufacturing method of vacuum nano pipe field effect transistor, it is described true
The manufacturing method of empty nanotube field effect transistor includes:
Semi-conductive substrate is provided；
First medium layer, source electrode, second dielectric layer and aluminium layer are sequentially formed on the semiconductor substrate；
Anodization is carried out to the aluminium layer to form anodic oxidation constructed of aluminium, the anodic oxidation constructed of aluminium has more
A evenly arranged first through hole, the bottom-exposed of the first through hole go out the second dielectric layer, the anodised aluminium knot
Structure includes grid and the gate dielectric layer for surrounding the grid；
Second dielectric layer is performed etching to form multiple second through-holes, second through-hole and the first through hole connect
It is logical, and the bottom-exposed of second through-hole goes out the source electrode；And
Drain electrode is formed under vacuum conditions, and the drain electrode is covered on the anodic oxidation constructed of aluminium, to form multiple receive
Rice vacuum tube.
Optionally, in the manufacturing method of the vacuum nano pipe field effect transistor, anode is carried out to the aluminium layer
Changing processing with the detailed process for forming anodic oxidation constructed of aluminium includes:
First time anodization is carried out to the aluminium layer in an acidic solution；
Remove oxide caused by the first time anodization；And
Second of anodization is carried out to the aluminium layer in an acidic solution.
Optionally, in the manufacturing method of the vacuum nano pipe field effect transistor, at the first time anodization
The acid solution that reason and second of anodization use is oxalic acid solution, and the concentration range of the oxalic acid solution is rubbed 0.2
To between 0.5 molar concentration, the first time anodization and second of anodized temperature are arrived at 5 DEG C that concentration
Between 15 DEG C, the first time anodization and second of anodized constant voltage are between 35V to 45V.
Optionally, in the manufacturing method of the vacuum nano pipe field effect transistor, the concentration of the oxalic acid solution
For 0.3 molar concentration, the first time anodization and second of anodized temperature are 10 DEG C, the first time
Anodization and second of anodized constant voltage are 40V.
Optionally, in the manufacturing method of the vacuum nano pipe field effect transistor, leakage is formed under vacuum conditions
Before pole, second dielectric layer is performed etching to be formed after multiple second through-holes, further includes: removed and be isolated by etching technics
Anodised aluminium in region.
Optionally, in the manufacturing method of the vacuum nano pipe field effect transistor, leakage is formed under vacuum conditions
While pole, further includes: form source emitter end on source electrode.
Optionally, in the manufacturing method of the vacuum nano pipe field effect transistor, leakage is formed under vacuum conditions
After pole and source emitter end, further includes: remove the source emitter end and second in the area of isolation by etching technics and be situated between
Matter layer；
Optionally, it in the manufacturing method of the vacuum nano pipe field effect transistor, is removed by etching technics
After drain material and second dielectric layer in the area of isolation, further includes: using annealing process to the source emitter end
It is handled, its surface is made to become arc-shaped.
Optionally, in the manufacturing method of the vacuum nano pipe field effect transistor, the reaction of the annealing process
Temperature range is between 400 DEG C to 600 DEG C, and gas that the annealing process uses is any one in hydrogen, nitrogen or argon gas
Kind or any combination thereof.
Optionally, in the manufacturing method of the vacuum nano pipe field effect transistor, in use annealing process to institute
It states after source emitter end handled, further includes: third dielectric layer, the third dielectric layer are formed in the area of isolation
It is linked together with the second dielectric layer.
Optionally, in the manufacturing method of the vacuum nano pipe field effect transistor, the first medium layer, second
The material of dielectric layer and third dielectric layer is silica.
Optionally, in the manufacturing method of the vacuum nano pipe field effect transistor, the material of the source electrode and drain electrode
Matter is low workfunction metal.
Correspondingly, the present invention provides a kind of vacuum nano pipe field effect transistor, the vacuum nano pipe field effect transistor
Pipe includes: semiconductor substrate；The first medium layer being formed in the semiconductor substrate；It is formed on the first medium layer
Source electrode；The second dielectric layer being formed on the source electrode；The anodic oxidation constructed of aluminium being formed in the second dielectric layer；It is formed
Drain electrode on the anodic oxidation constructed of aluminium；
Wherein, the anodic oxidation constructed of aluminium includes grid and the gate dielectric layer for surrounding the grid, the drain electrode
It is covered on the anodic oxidation constructed of aluminium, forms multiple nano-vacuum-tubes.
Optionally, in the vacuum nano pipe field effect transistor, further includes: third dielectric layer, the third are situated between
Matter layer is located at area of isolation and is linked together with the second dielectric layer.
Optionally, in the vacuum nano pipe field effect transistor, the length range of the nano-vacuum-tubes is in 1nm
To between 100nm, vacuum degree of the diameter range of the nano-vacuum-tubes between 1nm to 50nm, in the nano-vacuum-tubes
Range is between 0.01Torr to 50Torr.
In conclusion in vacuum nano pipe field effect transistor provided by the invention and its manufacturing method, pass through production
Anodic oxidation constructed of aluminium to further reduce device size, and is promoted with forming the vacuum nano pipe transistor of vertical structure
The performance of device.
Detailed description of the invention
Fig. 1 is the flow chart of the production method of the vacuum nano pipe field effect transistor of the embodiment of the present invention；
Fig. 2 to Fig. 9 is the structural schematic diagram of the manufacturing process of the vacuum nano pipe field effect transistor of the embodiment of the present invention；
Figure 10 is the energy band schematic diagram of the vacuum nano pipe field effect transistor of the embodiment of the present invention.
Specific embodiment
Below in conjunction with the drawings and specific embodiments to vacuum nano pipe field effect transistor proposed by the present invention and its manufacture
Method is described in further detail.According to following explanation and claims, advantages and features of the invention will be become apparent from.It needs
Bright, attached drawing is all made of very simplified form and using non-accurate ratio, only conveniently, lucidly to aid in illustrating
The purpose of the embodiment of the present invention.
Referring to FIG. 1, its flow chart for the production method of the vacuum nano pipe field effect transistor of the embodiment of the present invention.
As shown in Figure 1, the manufacturing method of the vacuum nano pipe field effect transistor includes:
Step 1: semi-conductive substrate 110 is provided；
Step 2: first medium layer 120, source electrode 130, second dielectric layer are sequentially formed in the semiconductor substrate 110
140 and aluminium layer 150；
Step 3: anodization is carried out to form anodised aluminium (AAO) structure, the anode to the aluminium layer 150
Aluminium oxide structure has multiple evenly arranged first through hole 150a, and the bottom-exposed of the first through hole 150a goes out described second
Dielectric layer 140, the anodic oxidation constructed of aluminium include grid 151 and the gate dielectric layer 152 for surrounding the grid 151；
Step 4: second dielectric layer 140 is performed etching to form multiple second through-hole 140a, the second through-hole 140a
It is connected to the first through hole 150a, and the bottom-exposed of the second through-hole 140a goes out the source electrode 130；
Step 5: forming drain electrode 160 under vacuum conditions, and the drain electrode 160 is covered on the anodic oxidation constructed of aluminium,
To form multiple nano-vacuum-tubes 180.
Specifically, the semiconductor substrate 110 can be silicon substrate, germanium silicon lining firstly, providing semi-conductive substrate 110
Bottom, III-group Ⅴ element compound substrate or well known to a person skilled in the art other semiconductive material substrates, are adopted in the present embodiment
It is silicon substrate.
Then, as shown in Fig. 2, sequentially forming first medium layer 120, source electrode 130, in the semiconductor substrate 110
Second medium layer 140 and aluminium layer 150.
Then, anodization is carried out to form anodic oxidation constructed of aluminium to the aluminium layer 150.Form anodised aluminium
(AAO) detailed process of structure includes: firstly, carrying out first time anodization to the aluminium layer 150 in an acidic solution；It connects
, remove oxide caused by the first time anodization；Then, the aluminium layer 150 is carried out in an acidic solution
Second of anodization.
In the present embodiment, the first time anodization is identical with second of anodized process conditions.It is described
The acid solution that first time anodization and second of anodization use is oxalic acid solution, the oxalic acid solution it is dense
Spend range in 0.2 molar concentration between 0.5 molar concentration, the first time anodization and second it is anodized
Temperature is between 5 DEG C~15 DEG C, and the first time anodization and second of anodized constant voltage are in 35V
Between~45V.
Preferably, the concentration of oxalic acid solution is 0.3 molar concentration, and anodized temperature is 10 DEG C, anodization
Voltage be 40V constant voltage.
As shown in figure 3, foring anodised aluminium knot in the second dielectric layer 140 after second of anodization
Structure, the anodic oxidation constructed of aluminium have multiple evenly arranged first through hole 150a, and the bottom of the first through hole 150a is sudden and violent
Expose the second dielectric layer 140, the anodic oxidation constructed of aluminium includes the grid 151 that material is aluminium and material is aluminium oxide
Gate dielectric layer 152, the gate dielectric layer 152 surround the grid 151.
It is formed after anodic oxidation constructed of aluminium, the first through hole 150a second dielectric layer 140 exposed is carved
Erosion, to form multiple second through-hole 140a.As shown in figure 4, the second through-hole 140a is connected to the first through hole 150a, and
The bottom-exposed of the second through-hole 140a goes out the source electrode 130.
Later, as shown in figure 5, removing the anodic oxidation aluminum material in area of isolation by etching technics.
Then, as shown in fig. 6, drain electrode 160 and source emitter end 162 are formed simultaneously under vacuum conditions, due to the leakage
The top of the multiple first through hole 150a is completely covered in pole 160, therefore forms multiple nano-vacuum-tubes 180, the nanometer
One end of vacuum tube 180 is arc-shaped structure (i.e. the surface of drain electrode 160), and the other end of the nano-vacuum-tubes 180 is spine
Structure (i.e. the surface at source emitter end 162)
In the present embodiment, the length range of the nano-vacuum-tubes 180 is between 1nm to 100nm, the nano-vacuum-tubes
Between 1nm to 50nm, the vacuum ranges in the nano-vacuum-tubes 180 arrive 180 diameter range in 0.01Torr
Between 50Torr.Preferably, the length of the nano-vacuum-tubes 180 be 10nm, 20nm or 50nm, the carbon nanotube 60 it is straight
Diameter is 3nm, 5nm or 10nm, the vacuum degree in the nano-vacuum-tubes 180 is 0.05Torr, 1Torr, 10Torr, 20Torr,
30Torr or 40Torr.
In the present embodiment, the material of the source electrode 130 and drain electrode 160 is low workfunction metal, e.g. zirconium (Zr), vanadium
(V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), iron (Fe), cobalt (Co), vanadium (Pd), copper (Cu), aluminium (Al), gallium
(Ga), indium (In), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), diamond any one or any combination thereof.
Hereafter, it is situated between as shown in fig. 7, removing the source emitter end 162 and second in the area of isolation by etching technics
Matter layer 140, etching stopping is in the source electrode 130.
Later, as shown in figure 8, being made annealing treatment, make the other end (the i.e. source emitter end of the nano-vacuum-tubes 180
162 surface) also become arc structure.By annealing, the reliability and service life of device can be improved.
In the present embodiment, the range of reaction temperature of the annealing process is 400 degrees Celsius~600 degrees Celsius.The high temperature
The gas that annealing process uses in hydrogen (H2), nitrogen (N2), argon gas (Ar) any one or any combination thereof.
Finally, as shown in figure 9, form third dielectric layer 170 in the area of isolation, the third dielectric layer 170 with
The second dielectric layer 140 is linked together.
In the present embodiment, the first medium layer 120, second dielectric layer 140 are identical with the material of third dielectric layer 170,
It is silica.
So far, vacuum nano pipe field effect transistor 100 is formed.The grid of the vacuum nano pipe field effect transistor 100
Pole vertical arrangement is not only able to promote the performance of device using this structure between source electrode and drain electrode, and can be further
Reduce device size.
The energy band schematic diagram of the vacuum nano pipe field effect transistor 100 at work can refer to Figure 10.Such as Figure 10 institute
Show, when grid voltage (Vg) is greater than threshold voltage (Vt), transistor is opened, since electronics or hole move to drain electrode from source electrode
Energy band migration distance it is shorter, therefore the performance of entire device is more preferably.Wherein, threshold voltage (Vt) is also referred to as cut-in voltage.
Correspondingly, the present invention also provides a kind of manufacturers using vacuum nano pipe field effect transistor as described above
Vacuum nano pipe field effect transistor made of method preparation.
With continued reference to FIG. 9, the vacuum nano pipe field effect transistor 100 includes: semiconductor substrate 110；It is formed in
First medium layer 120 in the semiconductor substrate 110；The source electrode 130 being formed on the first medium layer 120；It is formed in
Second dielectric layer 140 on the source electrode 130；The anodic oxidation constructed of aluminium being formed in the second dielectric layer 140；It is formed in
Drain electrode 160 on the anodic oxidation constructed of aluminium；Wherein, the anodic oxidation constructed of aluminium includes described in grid 151 and encirclement
The gate dielectric layer 152 of grid 151, the drain electrode 160 are covered on the anodic oxidation constructed of aluminium, form multiple nano vacuums
Pipe 180.
Specifically, the vacuum nano pipe field effect transistor 100 further includes third dielectric layer 170, the third medium
Layer 170 is located in area of isolation and is linked together with the second dielectric layer 140.The length range of the nano-vacuum-tubes 180
It is 1nm~100nm, the diameter range of the nano-vacuum-tubes 180 is between 1nm to 50nm, in the nano-vacuum-tubes 180
Vacuum ranges are between 0.01Torr to 50Torr.
To sum up, in vacuum nano pipe field effect transistor provided in an embodiment of the present invention and its manufacturing method, lead to
Production anodic oxidation constructed of aluminium is crossed to form the vacuum nano pipe transistor of vertical structure, so that device size is further reduced,
And promote the performance of device.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (15)
1. a kind of manufacturing method of vacuum nano pipe field effect transistor characterized by comprising
Semi-conductive substrate is provided；
First medium layer, source electrode, second dielectric layer and aluminium layer are sequentially formed on the semiconductor substrate；
Anodization is carried out to the aluminium layer to form anodic oxidation constructed of aluminium, the anodic oxidation constructed of aluminium has multiple equal
The first through hole of even arrangement, the bottom-exposed of the first through hole go out the second dielectric layer, the anodic oxidation constructed of aluminium packet
It includes grid and surrounds the gate dielectric layer of the grid；
Second dielectric layer being performed etching to form multiple second through-holes, second through-hole is connected to the first through hole, and
The bottom-exposed of second through-hole goes out the source electrode；And
Drain electrode is formed under vacuum conditions, and the drain electrode is covered on the anodic oxidation constructed of aluminium, true to form multiple nanometers
Blank pipe.
2. the manufacturing method of vacuum nano pipe field effect transistor as described in claim 1, which is characterized in that the aluminium layer
Anodization, which is carried out, with the detailed process for forming anodic oxidation constructed of aluminium includes:
First time anodization is carried out to the aluminium layer in an acidic solution；
Remove oxide caused by the first time anodization；And
Second of anodization is carried out to the aluminium layer in an acidic solution.
3. the manufacturing method of vacuum nano pipe field effect transistor as claimed in claim 2, which is characterized in that the first time
The acid solution that anodization and second of anodization use is oxalic acid solution, the concentration range of the oxalic acid solution
In 0.2 molar concentration between 0.5 molar concentration, the first time anodization and second of anodized temperature are equal
Between 5 DEG C to 15 DEG C, the first time anodization and second of anodized constant voltage are in 35V to 45V
Between.
4. the manufacturing method of vacuum nano pipe field effect transistor as claimed in claim 3, which is characterized in that the oxalic acid is molten
The concentration of liquid is 0.3 molar concentration, and the first time anodization and second of anodized temperature are 10 DEG C, institute
Stating first time anodization and second of anodized constant voltage is 40V.
5. the manufacturing method of vacuum nano pipe field effect transistor as described in claim 1, which is characterized in that in vacuum condition
Before lower formation drain electrode, second dielectric layer is performed etching to be formed after multiple second through-holes, further includes: pass through etching technics
Remove the anodised aluminium in area of isolation.
6. the manufacturing method of vacuum nano pipe field effect transistor as claimed in claim 5, which is characterized in that in vacuum item
While forming drain electrode under part, further includes: form source emitter end on source electrode.
7. the manufacturing method of vacuum nano pipe field effect transistor as claimed in claim 6, which is characterized in that in vacuum condition
After lower formation drain electrode and source emitter end, further includes: remove the source emitter end in the area of isolation by etching technics
And second dielectric layer.
8. the manufacturing method of vacuum nano pipe field effect transistor as claimed in claim 7, which is characterized in that passing through etching
Technique removes after drain material and second dielectric layer in the area of isolation, further includes: using annealing process to the source
Pole transmitting terminal is handled, its surface is made to become arc-shaped.
9. the manufacturing method of vacuum nano pipe field effect transistor as claimed in claim 8, which is characterized in that the lehr attendant
The range of reaction temperature of skill is between 400 DEG C to 600 DEG C, and the gas that the annealing process uses is in hydrogen, nitrogen or argon gas
Any one or any combination thereof.
10. the manufacturing method of vacuum nano pipe field effect transistor as claimed in claim 8, which is characterized in that moved back using
After fire process handles the source emitter end, further includes: third dielectric layer is formed in the area of isolation, it is described
Third dielectric layer is linked together with the second dielectric layer.
11. the manufacturing method of vacuum nano pipe field effect transistor as claimed in claim 10, the first medium layer, second
The material of dielectric layer and third dielectric layer is silica.
12. the manufacturing method of vacuum nano pipe field effect transistor as described in claim 1, which is characterized in that the source electrode
Material with drain electrode is low workfunction metal.
13. a kind of vacuum nano pipe field effect transistor, using the vacuum nano pipe as described in any in claim 1 to 12
The manufacturing method of field effect transistor is prepared characterized by comprising
Semiconductor substrate；
The first medium layer being formed in the semiconductor substrate；
The source electrode being formed on the first medium layer；
The second dielectric layer being formed on the source electrode；
The anodic oxidation constructed of aluminium being formed in the second dielectric layer；
The drain electrode being formed on the anodic oxidation constructed of aluminium；
Wherein, the anodic oxidation constructed of aluminium includes grid and the gate dielectric layer for surrounding the grid, the drain electrode covering
In on the anodic oxidation constructed of aluminium, multiple nano-vacuum-tubes are formed.
14. vacuum nano pipe field effect transistor as claimed in claim 13, which is characterized in that further include: third dielectric layer,
The third dielectric layer is located at area of isolation and is linked together with the second dielectric layer.
15. vacuum nano pipe field effect transistor as claimed in claim 13, which is characterized in that the length of the nano-vacuum-tubes
Range is spent between 1nm to 100nm, and the diameter range of the nano-vacuum-tubes is between 1nm to 50nm, the nano-vacuum-tubes
Interior vacuum ranges are between 0.01Torr to 50Torr.
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| CN201610307101.2A CN107359241B (en) | 2016-05-10 | 2016-05-10 | Vacuum nano pipe field effect transistor and its manufacturing method |
| TW105131360A TWI589004B (en) | 2016-05-10 | 2016-09-29 | Method for preparing nano-vacuum tube field effect transistor |
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| TW200826290A (en) * | 2006-12-01 | 2008-06-16 | Univ Nat Chiao Tung | Vertical organic transistor and manufacturing method thereof |
| ITMI20130897A1 (en) * | 2013-05-31 | 2014-12-01 | St Microelectronics Srl | INTEGRATED VACUUM MICROELECTRONIC DEVICE AND ITS MANUFACTURING METHOD. |
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