CN107123672B - PolySi thin gate structure of radio frequency L DMOS and preparation method thereof - Google Patents

PolySi thin gate structure of radio frequency L DMOS and preparation method thereof Download PDF

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CN107123672B
CN107123672B CN201710111756.7A CN201710111756A CN107123672B CN 107123672 B CN107123672 B CN 107123672B CN 201710111756 A CN201710111756 A CN 201710111756A CN 107123672 B CN107123672 B CN 107123672B
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polysi
layer
sio
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doped
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CN107123672A (en
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刘洪军
赵杨杨
王佃利
应贤炜
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CETC 55 Research Institute
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode

Abstract

The invention relates to a radio frequency L DMOSThe thin polySi gate structure is used for forming a PolySi/SiO from top to bottom on the surface of a gate oxide layer of a radio frequency L DMOS device with a submicron gate2The method comprises the steps of carrying out self-aligned doping on a/PolySi sandwich gate structure, and removing the PolySi/SiO on the sandwich gate structure2Two layers to form a thin gate structure of PolySi, and has the advantages of solving the problem of incompatibility of longitudinal size reduction and L DMOS process, and adopting sandwich PolySi/SiO2The thin SiO2 layer in the middle of the sandwich gate structure can be used as a transition layer between two layers of PolySi, an automatic termination layer of the upper layer of PolySi and a protective layer of the lower layer of PolySi, the transverse and longitudinal equal proportion reduction of the L DMOS gate can be realized, and the frequency performance of the device is improved.

Description

PolySi thin gate structure of radio frequency L DMOS and preparation method thereof
Technical Field
The invention relates to a polySi thin gate structure of radio frequency L DMOS and a preparation method thereof, belonging to the technical field of semiconductor microelectronic design and manufacture.
Background
In order to continuously improve the frequency performance of L DMOS, the characteristic size of a L DMOS grid is continuously reduced from an initial micron level to a current submicron level, and the working frequency is also increased from about 1GHz to a current 3.8GHzT=gm/2πCissInput capacitance CissThe smaller, the cut-off frequency fTThe higher the frequency performance of the device, where CissWhen the L DMOS structure is realized in the manufacturing process, the longitudinal height of the gate has certain size requirement, and impurities which cause ion implantation penetrate through polysilicon and can not realize self-aligned doping when the size is lower than the certain size, for example, the longitudinal size is kept unchanged at 0.5 mu m, the transverse size of the gate is reduced from 1 mu m to 0.25 mu m, and the input capacitor CissAnd cannot be reduced to 1/4, which may not be 1/2. The non-equal proportion reduction of the capacitance severely limits the frequency of the deviceThe rate performance is improved.
Therefore, the height of the gate must be reduced to effectively reduce the area between the gate and the sidewall source field plate, thereby reducing the gate sidewall parasitic capacitance and realizing the input capacitance CissMinimizing and effectively improving the frequency performance of the L DMOS device.
Disclosure of Invention
The invention provides a PolySi thin gate structure of radio frequency L DMOS and a preparation method thereof, aiming at overcoming the limitation of a gate self-alignment technology on the gate thickness, effectively reducing the gate thickness, reducing the capacitance between a gate and a side wall source field plate and improving the frequency performance of a device.
The technical scheme is that the PolySi thin gate structure of the radio frequency L DMOS is characterized in that for a radio frequency L DMOS device with a submicron gate, from top to bottom PolySi/SiO is formed on the surface of a gate oxide layer2The method comprises the steps of carrying out self-aligned doping on a/PolySi sandwich gate structure, and removing the PolySi/SiO on the sandwich gate structure2And forming a thin polySi gate structure.
The method for preparing the polySi thin gate structure of the radio frequency L DMOS comprises the following steps:
(1) depositing lower layer doped PolySi on the surface L PCVD of the gate oxide layer;
(2) carrying out dry-oxygen thermal oxidation on the lower layer doped with PolySi to form thin SiO2A layer;
(3) on thin SiO2The layer surface L PCVD deposits the upper layer doped with PolySi;
(4) photoetching and ICP etching the upper layer doped with PolySi, and stopping at the SiO layer of the middle layer2(ii) a Dry etching of the intermediate layer SiO2And ending with the lower layer doped with PolySi; ICP etches the lower doped polySi layer, and terminates at the gate oxide layer; removing the photoresist to form PolySi/SiO2a/PolySi sandwich gate structure;
(5) carrying out conventional doping on a channel, a drift region and a source and drain of the radio frequency L DMOS by adopting a gate self-alignment technology;
(6) depositing SiO on the surface of the gate structure and the gate oxide layer2A cover layer;
(7) in SiO2Coating the surface of the covering layer by spin coatingA layer of uniform photoresist;
(8) back etching with plasma to remove the photoresist on the surface of the gate and expose SiO on the surface of the gate2A cover layer;
(9) dry etching of SiO on gate surface2A cap layer terminating at an upper layer of PolySi;
(10) dry etching the upper layer of PolySi, stopping at the SiO of the middle layer2(ii) a Removing SiO in the middle layer by isotropic wet etching2And sidewall portion residual SiO2A layer;
(11) removing all photoresist remained on the surface;
(12) photoetching and dry etching the source-drain alloy region, stopping on the surface of the silicon substrate, and removing the photoresist;
(13) sputtering a metal layer on the surface of the silicon, and annealing the high-temperature alloy to form a gate-source-drain alloy;
(14) and removing residual metal on the silicon surface without forming alloy.
The invention has the beneficial effects that:
1) solves the problem that the longitudinal size is not compatible with the L DMOS process when the size of the L DMOS grid is reduced in equal proportion,
2) adopts sandwich polySi/SiO2the/PolySi structure meets the shielding thickness requirement of self-aligned doping; thin SiO in the middle of a sandwich gate structure2A layer serving as a transition layer between two layers of PolySi, which is not only an automatic termination layer of the upper layer of PolySi but also a protective layer of the lower layer of PolySi;
3) the transverse line width of the gate can be determined by a photoetching pattern, the longitudinal size of the gate is determined by the thickness of the lower layer of PolySi, the transverse and longitudinal equal-proportion reduction of the L DMOS gate is realized, the parasitic capacitance between electrodes of L DMOS is effectively reduced, and the frequency performance of the device is improved;
4) the method is completely compatible with the conventional L DMOS process, and does not add an extra photoetching procedure.
Drawings
FIG. 1 is a structural diagram of a bottom layer doped with PolySi deposited on the surface of a gate oxide layer;
FIG. 2 is a process of doping a PolySi surface to form a thin SiO2Schematic structural diagram of (a);
FIG. 3 is a thin SiO2Depositing a structural schematic diagram of upper layer doped with PolySi on the surface;
FIG. 4 is a photolithography and etching of the upper layer doped with PolySi, ending with an intermediate layer of SiO2(ii) a Etching the intermediate layer of SiO2And ending with the lower layer doped with PolySi; etching the lower doped polySi layer to terminate on the gate oxide layer; removing the photoresist to form PolySi/SiO2A structural schematic diagram of a/PolySi sandwich gate structure;
fig. 5 is a schematic structural diagram of conventional doping of a channel, a drift region, and a source and a drain of a radio frequency L DMOS by using a gate self-alignment technique;
FIG. 6 is a process for depositing SiO on the surface of the gate structure and the gate oxide layer2The structure of the covering layer is shown schematically;
FIG. 7 is a graph showing the formation of SiO2Spin coating the surface of the covering layer to form a layer of uniform photoresist structure schematic diagram;
FIG. 8 is a process of removing the photoresist on the gate surface by plasma etch back to expose the SiO on the gate surface2The structure of the covering layer is shown schematically;
FIG. 9 is a dry etching of SiO on the gate surface2A capping layer terminating in a structural schematic of an upper layer of PolySi;
FIG. 10 is a dry etch of the upper PolySi layer, terminating at the intermediate SiO layer2(ii) a Removing SiO in the middle layer by isotropic wet etching2And sidewall portion residual SiO2A schematic of the structure of the layer;
FIG. 11 is a schematic diagram of a structure for removing all photoresist remaining on the surface;
FIG. 12 is a schematic structural view of a process of photo-etching and etching a source-drain alloy region, terminating at the surface of a silicon substrate, and removing a photoresist;
FIG. 13 is a schematic structural diagram of a gate PolySi alloy formed by sputtering a metal layer on a silicon surface and performing a high temperature alloy anneal;
FIG. 14 is a schematic diagram of a structure for removing residual metal on a silicon surface without forming an alloy;
FIG. 15 is an overall schematic view of a thin gate structure made in accordance with the present invention;
in the figure, 1 is a substrate2 is a gate oxide layer, 3 is a lower layer of PolySi, 4 is an intermediate thin SiO2Layer 5 is an upper layer of PolySi, 6 is SiO2The capping layer, 7 is photoresist, 8 is a metal layer, and 9 is a gate source drain alloy.
Detailed Description
The thin poly Si gate structure of the radio frequency L DMOS is characterized in that for a radio frequency L DMOS device with a submicron gate, from top to bottom poly Si/SiO is formed on the surface of a gate oxide layer2The method comprises the steps of carrying out self-aligned doping on a/PolySi sandwich gate structure, and removing the PolySi/SiO on the sandwich gate structure2And forming a thin polySi gate structure.
The method for preparing the polySi thin gate structure of the radio frequency L DMOS comprises the following steps:
(1) depositing lower layer doped PolySi on the surface L PCVD of the gate oxide layer;
(2) carrying out dry-oxygen thermal oxidation on the lower layer doped with PolySi to form thin SiO2A layer;
(3) on thin SiO2Surface L PCVD deposits an upper layer of doped PolySi;
(4) photoetching and ICP etching the upper layer doped with PolySi, and stopping at the SiO layer of the middle layer2(ii) a Dry etching of the intermediate layer SiO2And ending with the lower layer doped with PolySi; ICP etches the lower doped polySi layer, and terminates at the gate oxide layer; removing the photoresist to form PolySi/SiO2a/PolySi sandwich gate structure;
(5) carrying out conventional doping on a channel, a drift region and a source and drain of the radio frequency L DMOS by adopting a gate self-alignment technology;
(6) l PCVD deposited SiO on the surface of gate structure and gate oxide layer2A cover layer;
(7) in SiO2Spin-coating a layer of uniform photoresist on the surface of the covering layer;
(8) back etching with plasma to remove the photoresist on the surface of the gate and expose SiO on the surface of the gate2A cover layer;
(9) dry etching of SiO on gate surface2A cap layer terminating at an upper layer of PolySi;
(10) dry etching the upper layer of PolySi, stopping at the SiO of the middle layer2(ii) a Adopt eachWet etching to remove SiO in the middle layer2And sidewall portion residual SiO2A layer;
(11) removing all photoresist remained on the surface;
(12) photoetching and dry etching the source-drain alloy region, stopping on the surface of the silicon substrate, and removing the photoresist;
(13) sputtering a metal layer on the surface of the silicon, and annealing the high-temperature alloy to form a gate-source-drain alloy;
(14) and removing residual metal on the silicon surface without forming alloy.
The thickness of the gate oxide layer in the step (1) is 100 Å -500 Å, as shown in the attached figure 2.
The thickness of the lower layer doped with the PolySi is 2000 Å -4000 Å, and the doped PolySi is phosphorus-doped PolySi or arsenic-doped PolyS.
The thin SiO in the step (2)2The thickness is 100 Å -500 Å, as shown in FIG. 2.
The thickness of the doped PolySi in the step (3) is 2000 Å -4000 Å, and the doped PolySi is phosphorus-doped PolySi or arsenic-doped PolySi.
SiO in the step (6)2The thickness of the covering layer is 300 Å -1000 Å.
The thickness of the photoresist in the step (7) is 0.7-1.5 mu m.
The metal layer in the step (13) is cobalt, titanium, molybdenum or platinum.
The following provides a flow for preparing a thin gate structure of rf L DMOS with reference to fig. 1 to 14,
as shown in FIG. 1, 2000 Å -4000 Å of bottom-layer doped PolySi is deposited on the surface of a gate oxide layer;
as shown in FIG. 2, 100 Å -500 Å SiO is formed on the surface of doped PolySi2；
As shown in fig. 3, in thin SiO2Depositing 2000 Å -4000 Å upper layer doped PolySi on the surface;
as shown in fig. 4, the upper doped PolySi layer is etched by photolithography, terminating in the intermediate SiO layer2(ii) a Etching the intermediate layer of SiO2And ending with the lower layer doped with PolySi; etching the lower doped polySi layer, stopping on the gate oxide layer, removing the photoresist to formPolySi/SiO2a/PolySi sandwich gate structure;
as shown in fig. 5, a gate self-alignment technology is adopted to perform conventional doping of a channel, a drift region and a source and drain of the radio frequency L DMOS;
as shown in FIG. 6, 300 Å -1000 Å SiO is deposited on the surface2A cover layer;
as shown in FIG. 7, in SiO2Spin coating the surface of the covering layer to form uniform photoresist of 0.7-1.5 mu m;
as shown in fig. 8, the photoresist on the surface of the gate is removed by back etching with plasma resist, and the SiO2 covering layer on the surface of the gate is exposed;
as shown in FIG. 9, the SiO on the gate surface is dry etched2A cap layer terminating at an upper layer of PolySi;
as shown in FIG. 10, the upper layer of PolySi is dry etched, terminating in an intermediate layer of SiO2(ii) a Removing SiO in the middle layer by isotropic wet etching2And sidewall portion residual SiO2A layer;
as shown in fig. 11, removing all the photoresist remaining on the surface;
as shown in fig. 12, the source-drain alloy region is photoetched and etched, and is stopped at the surface of the silicon substrate, and the photoresist is removed;
as shown in fig. 13, a metal layer is sputtered on the silicon surface, and high temperature alloy annealing is performed to form a gate PolySi alloy;
as shown in fig. 14, the residual metal on the silicon surface that is not alloyed is removed.
The present invention will be described in detail below with reference to specific examples.
Example 1
(1) Thermally growing a 200 Å gate oxide layer on the surface of a silicon epitaxial layer, and then depositing a 3000 Å lower layer of arsenic-doped PolySi by L PCVD;
(2) thermally oxidizing the surface of the arsenic-doped PolySi to form 200 Å intermediate SiO layer2；
(3) In SiO2Surface L PCVD deposit 2000 Å upper layer arsenic-doped PolySi;
(4) photoetching and ICP etching the upper layer of the poly Si doped with arsenic, and stopping at the SiO layer of the middle layer2；CF4Etching the intermediate layer of SiO2Terminate atDoping the lower layer with arsenic PolySi; ICP etches the lower layer of the As-doped PolySi, the lower layer of the As-doped PolySi is stopped at the gate oxide layer, III liquid removes the photoresist to form PolySi/SiO2a/PolySi sandwich gate structure;
(5) the channel, the drift region and the source and drain of the radio frequency L DMOS are doped conventionally by adopting a grid self-alignment technology and an ion implantation mode;
(6) l PCVD deposition of 500 Å SiO on the surface of the gate structure and the gate oxide layer2A cover layer;
(7) in SiO2Spin coating the surface of the covering layer to form a layer of photoresist with uniform particle size of 1 mu m;
(8) back etching with plasma to remove the photoresist on the surface of the gate and expose SiO on the surface of the gate2A cover layer;
（9）CF4etching SiO on the surface of the gate2A cap layer terminating at an upper layer of PolySi;
(10) ICP etches the upper PolySi layer, and ends with SiO in the middle layer2(ii) a BHF etching of intermediate SiO layer2And sidewall portion residual SiO2A layer;
(11) removing all photoresist remained on the surface by using the solution III;
(12) lithography, CF4Etching the source-drain alloy region, stopping at the surface of the silicon substrate, and removing the photoresist by using the solution III;
(13) sputtering metal cobalt on the surface of the silicon, and annealing alloy at 450 ℃ to form gate-source-drain alloy;
(14) and removing residual cobalt on the silicon surface without forming alloy by the I solution and the III solution.
Example 2
(1) Thermally growing a 250 Å gate oxide layer on the surface of a silicon epitaxial layer, and then depositing 3500 Å lower-layer arsenic-doped PolySi layer by L PCVD;
(2) thermally oxidizing the surface of the arsenic-doped PolySi to form 250 Å intermediate SiO layer2；
(3) In SiO2Surface L PCVD deposit 2000 Å upper layer arsenic-doped PolySi;
(4) photoetching and ICP etching the upper layer of the poly Si doped with arsenic, and stopping at the SiO layer of the middle layer2；CF4Etching the intermediate layer of SiO2Terminating in the lower layer doped with arsenicPolySi; ICP etches the lower layer of the As-doped PolySi, the lower layer of the As-doped PolySi is stopped at the gate oxide layer, III liquid removes the photoresist to form PolySi/SiO2a/PolySi sandwich gate structure;
(5) the channel, the drift region and the source and drain of the radio frequency L DMOS are doped conventionally by adopting a grid self-alignment technology and an ion implantation mode;
(6) l PCVD deposition of 500 Å SiO on the surface of the gate structure and the gate oxide layer2A cover layer;
(7) in SiO2Spin coating the surface of the covering layer to form a layer of photoresist with the uniform thickness of 0.8 mu m;
(8) back etching with plasma to remove the photoresist on the surface of the gate and expose SiO on the surface of the gate2A cover layer;
（9）CF4etching SiO on the surface of the gate2A cap layer terminating at an upper layer of PolySi;
(10) ICP etches the upper PolySi layer, and ends with SiO in the middle layer2(ii) a BHF etching of intermediate SiO layer2And sidewall portion residual SiO2A layer;
(11) removing all photoresist remained on the surface by using the solution III;
(12) lithography, CF4Etching the source-drain alloy region, stopping at the surface of the silicon substrate, and removing the photoresist by using the solution III;
(13) sputtering platinum on the surface of the silicon, and annealing alloy at 600 ℃ to form gate-source-drain alloy;
(14) the aqua regia removes residual platinum on the silicon surface that has not been alloyed.

Claims (1)

1. The preparation method of the polySi thin gate structure of the radio frequency L DMOS is characterized in that for a radio frequency L DMOS device with a submicron gate, from top to bottom PolySi/SiO is formed on the surface of a gate oxide layer2The method comprises the steps of carrying out self-aligned doping on a/PolySi sandwich gate structure, and removing the PolySi/SiO on the sandwich gate structure2Two layers, forming a thin gate structure of PolySi;
the preparation method comprises the following steps:
(1) depositing lower layer doped PolySi on the surface L PCVD of the gate oxide layer;
(2) carrying out dry-oxygen thermal oxidation on the lower layer doped with PolySi to form thin SiO2A layer;
(3) on thin SiO2The layer surface L PCVD deposits the upper layer doped with PolySi;
(4) photoetching and ICP etching the upper layer doped with PolySi, and stopping at the SiO layer of the middle layer2(ii) a Dry etching of the intermediate layer SiO2And ending with the lower layer doped with PolySi; ICP etches the lower doped polySi layer, and terminates at the gate oxide layer; removing the photoresist to form PolySi/SiO2a/PolySi sandwich gate structure;
(5) carrying out conventional doping on a channel, a drift region and a source and drain of the radio frequency L DMOS by adopting a gate self-alignment technology;
(6) l PCVD deposited SiO on the surface of gate structure and gate oxide layer2A cover layer;
(7) in SiO2Spin-coating a layer of uniform photoresist on the surface of the covering layer;
(8) back etching with plasma to remove the photoresist on the surface of the gate and expose SiO on the surface of the gate2A cover layer;
(9) dry etching of SiO on gate surface2A cap layer terminating at an upper layer of doped PolySi;
(10) dry etching the upper layer doped with PolySi, and stopping at the SiO layer of the middle layer2(ii) a Removing SiO in the middle layer by isotropic wet etching2And sidewall portion residual SiO2A layer;
(11) removing all photoresist remained on the surface;
(12) photoetching and dry etching the source-drain alloy region, stopping on the surface of the silicon substrate, and removing the photoresist;
(13) sputtering a metal layer on the surface of the silicon, and annealing the high-temperature alloy to form a gate-source-drain alloy;
(14) removing residual metal on the surface of the silicon without forming alloy;
the thickness of the gate oxide layer in the step (1) is 100 Å -500 Å, the thickness of the doped PolySi is 2000 Å -4000 Å, and the doped PolySi is phosphorus-doped PolySi or arsenic-doped PolySi;
thin SiO in step (2)2The thickness is 100 Å -500 Å;
the thickness of the doped PolySi in the step (3) is 2000 Å -4000 Å, and the doped PolySi is phosphorus-doped PolySi or arsenic-doped PolySi;
SiO in step (6)2The thickness of the covering layer is 300 Å -1000 Å;
the thickness of the photoresist in the step (7) is 0.7-1.5 mu m;
the metal layer in the step (13) is cobalt, titanium, molybdenum or platinum.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104282569A (en) * 2013-07-05 2015-01-14 上海华虹宏力半导体制造有限公司 Manufacturing technological method of RFLDMOS
CN104810404A (en) * 2015-04-08 2015-07-29 中国电子科技集团公司第五十五研究所 Fine polycrystalline silicon silicide composite gate structure and preparing method thereof

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Publication number Priority date Publication date Assignee Title
US20020000580A1 (en) * 1998-02-09 2002-01-03 Koichi Okashita Scalable manufacture process for power mosfet with fully self-aligned shrinkable gate and drain
KR100840659B1 (en) * 2006-09-06 2008-06-24 동부일렉트로닉스 주식회사 Method for Manufacturing DEMOS Device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104282569A (en) * 2013-07-05 2015-01-14 上海华虹宏力半导体制造有限公司 Manufacturing technological method of RFLDMOS
CN104810404A (en) * 2015-04-08 2015-07-29 中国电子科技集团公司第五十五研究所 Fine polycrystalline silicon silicide composite gate structure and preparing method thereof

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