CN107346943A - Suitable for DCM and CCM dual-mode sync rectifier control circuit - Google Patents
Suitable for DCM and CCM dual-mode sync rectifier control circuit Download PDFInfo
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- CN107346943A CN107346943A CN201710564643.2A CN201710564643A CN107346943A CN 107346943 A CN107346943 A CN 107346943A CN 201710564643 A CN201710564643 A CN 201710564643A CN 107346943 A CN107346943 A CN 107346943A
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
- H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
- H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
- H02M7/2195—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration the switches being synchronously commutated at the same frequency of the AC input voltage
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
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Abstract
Suitable for DCM and CCM dual-mode sync rectifier control circuit, belong to technical field of power management.The present invention is simple in construction, can effectively reduce rectification conduction loss, realize the high efficiency of synchronous rectification.Wherein, the second negative level detector realizes minimum Power MOSFET；Turn-off time shroud module prevents opening by mistake for synchronous rectifier M2 from opening, and opening time shroud module prevents synchronous rectifier M2 mistake from turning off；First sampling end bears high pressure using high tension apparatus LDMOS and DEMOS drain electrode, avoids and synchronous rectifier M2 drain terminal VD is clamped with Zener, prevents synchronous rectifier M2 drain terminal VD leakage current over the ground；Above measure realizes the high efficiency of synchronous rectification jointly；Synchronization control module is introduced in addition, realizes the synchronous rectification under continuous current mode CCM.
Description
Technical field
The invention belongs to technical field of power management, more particularly to a kind of dual-mode sync suitable for DCM and CCM
Rectifier control circuit.
Background technology
As Modern High-Speed super large-scale integration size constantly reduces, power consumption constantly reduces, it is desirable to supply voltage
Also more and more lower, output current is then increasing.Low pressure, high current output environment under, traditional commutation diode conducting
Pressure drop is higher, even if using the Schottky diode of low pressure drop, can also produce more than 0.4V pressure drop, cause rectifier loss to increase
Add, power-efficient reduces.Synchronous rectification can substantially reduce rectifying part by using the MOSFET of more low on-resistance
Power consumption, improve the performance of converter, realize the high efficiency of power supply.
Synchronous rectification can be divided into voltage-type driving and current mode drive by type of drive, by the source of drive signal
Self-driven and outer driving can be divided into again.Wherein, voltage-type self-powered flowing mode is structurally simple, economical efficiently, is extensively to be closed at present
The synchronous rectification actuation techniques of note, voltage-type self-device synchronous rectification are applied to anti exciting converter Flyback applied topology such as
Shown in Fig. 1.The operation principle of the applied topology is：When primary side switch pipe M1 is opened, synchronous commutating control circuit detects together
Walk rectifying tube M2 drain electrode and source voltage difference VDS>0, synchronous rectifier M2 is closed, vice-side winding NSStore energy, system according to
By output capacitance COUTPowering load；When primary side switch pipe M1 is closed, vice-side winding NSVoltage reversal, synchronous rectification control
Drain electrode and source voltage difference V of the electric circuit inspection to synchronous rectifier M2DS<0, synchronous rectifier M2 is opened, vice-side winding NSStorage
The energy deposited is supplied to load, while supplements output capacitance COUTThe energy of loss.The detection of two zero crossings is voltage-type self-powered
The key of dynamic synchronous rectification, and it is not in practice strict detection zero crossing, but two are detected close to no-voltage
Negative threshold value, judge being turned on and off rather than using zero-crossing comparator of synchronous rectifier M2 using two negative threshold values
Reason is, can reduce VDSInfluence of the shake of voltage to accurate decision circuitry state.And select one close to zero it is negative
Threshold test point can reduce body diode D2 ON times, improve rectification efficiency.It is in addition, same when synchronous rectifier M2 is turned off
Step rectifying tube M2 drain electrode (VD ends) can cause VD voltages to produce ringing because LC vibrates, and VD ringing voltages may be made
Opened into 1) opening by mistake synchronous rectifier, reduce rectification efficiency；2) internal components of rectification chip are broken down by high-voltage.For the former,
Generally opened with one section of TON/TOFF signal to shield to turn off/open by mistake by mistake, and for the latter, traditional way is to VD with Zener
Sampling end is clamped, and by VD voltage clamps in a safety level when Zener punctures, but this scheme can lead to power supply
The Zener of breakdown is crossed to ground leakage current, causes the reduction of rectification efficiency.
The content of the invention
For above-mentioned weak point, the present invention provides a kind of dual-mode sync rectification suitable for DCM and CCM and controls electricity
Road, it is simple in construction, it can effectively reduce rectification conduction loss, realize the high efficiency of synchronous rectification.
The technical scheme is that：
Suitable for DCM and CCM dual-mode sync rectifier control circuit, including opening time shroud module, turn-off time
Shroud module, the first S/R latch, the second S/R latch, first and door, second and door, drive module, the first Zener Dz1With
Second Zener Dz2,
The synchronous commutating control circuit also includes the first negative level detector, the second negative level detector, ring detection
Device and synchronization control module,
The second negative level detector includes sampling pipe, and the sampling pipe includes the 13rd NMOS tube MN13 and the 14th
NMOS tube MN14, the first sampling end to drain as the synchronous commutating control circuit of the 13rd NMOS tube, its source electrode
The first sampled voltage is exported to the first input end of the first negative level detector；The drain electrode conduct of 14th NMOS tube
Second sampling end of the synchronous commutating control circuit, its source electrode export the second sampled voltage to the first negative level detector
The second input；
The input of the ringing detector connects the first sampling end of the synchronous commutating control circuit；First SR
The S ends of latch connect the output end of the ringing detector, and its R end connects the input of the drive module, the connection of its Q end
The input of the shut-in time shroud module and described first with the first input end of door；Described first inputs with the second of door
End connects the output end of the turn-off time shroud module, and its 3rd input connects the output of the first negative level detector
End and the input of the opening time shroud module；Described second is connected the second negative level inspection with the first input end of door
The output end of device is surveyed, its second input connects the output end of the opening time shroud module；The S of second S/R latch
End connection described first and the output end of door, the output end and the synchronization control module of its R end connection described second and door
Output end, its Q end connect the input of the drive module；
The first Zener Dz1Anode connect the second Zener Dz2Negative electrode and the synchronization control module input
End, its negative electrode meet supply voltage, the second Zener Dz2Plus earth；The output end of the drive module is whole as the synchronization
The output end of flow control circuit.
Specifically, the synchronous commutating control circuit also includes internal reference and current offset module, for producing benchmark
Voltage VREFAnd bias current.
Specifically, second negative level detection circuit also includes first resistor R1, second resistance R2,3rd resistor R3,
4th resistance R4, the first electric capacity C1, the second electric capacity C2, the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3,
Four NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 9th NMOS
Pipe MN9, the tenth NMOS tube MN10, the 11st NMOS tube MN11, the 12nd NMOS tube MN12, the 15th NMOS tube MN15, the tenth
Six NMOS tube MN16, the 17th NMOS tube MN17, the 18th NMOS tube MN18, the first PMOS MP1, the second PMOS MP2,
Three PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, the 7th PMOS MP7, the 8th PMOS
Pipe MP8, the 9th PMOS MP9, the tenth PMOS MP10, the 11st PMOS MP11, the 12nd PMOS MP12, the 13rd
PMOS MP13, the 14th PMOS MP14, the 15th PMOS MP15, the 16th PMOS MP16, the 17th PMOS
MP17, the 18th PMOS MP18, the 19th PMOS MP19 and the 20th PMOS MP20,
13rd NMOS tube MN13 and the 14th NMOS tube MN14 gate interconnection, the 13rd NMOS tube MN13 source electrode connect
Connect the 7th NMOS tube MN7, the 4th NMOS tube MN4, the 11st NMOS tube MN11 source electrode and the 17th PMOS MP17, the 12nd
NMOS tube MN12 drain electrode, the 14th NMOS tube MN14 source electrode connect the 3rd NMOS tube MN3, the 8th NMOS tube MN8 and the tenth
One end of NMOS tube MN10 source electrode, the 18th PMOS MP18 drain electrode and the 4th resistance R4, the 4th resistance R4's is another
The 11st NMOS tube MN11 of end connection drain electrode；
7th NMOS tube MN7 and the 8th NMOS tube MN8 gate interconnection simultaneously connects the 5th NMOS tube MN5 and the 12nd PMOS
Pipe MP12 drain electrode, the leakage of the 7th NMOS tube MN7 the 5th NMOS tube MN5 of drain electrode connection source electrode and the 16th PMOS MP16
Pole, the drain electrode of the 8th NMOS tube MN8 the 6th NMOS tube MN6 of drain electrode connection source electrode and the 15th PMOS MP15；
5th NMOS tube MN5 and the 6th NMOS tube MN6 gate interconnection and grid and the drain electrode for connecting the 3rd NMOS tube MN3
And the tenth PMOS MP10 drain electrode, the 13rd PMOS MP13 drain electrode connection the 6th NMOS tube MN6 drain electrode and the 9th
NMOS tube MN9 grid, its source electrode connect the 7th PMOS MP7 drain electrode, and its grid connects the 9th PMOS MP9, the tenth PMOS
Pipe MP10, the 11st PMOS MP11, the 12nd PMOS MP12 and the 14th PMOS MP14 grid and the 9th PMOS
Pipe MP9 and the second NMOS tube MN2 drain electrode；
6th PMOS MP6 drain electrode connects the 12nd PMOS MP12 source electrode, and its grid connects the first PMOS MP1,
Two PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 7th PMOS MP7 and the 8th PMOS
Pipe MP8 grid and the first PMOS MP1 drain electrode and the 9th PMOS MP9 source electrode, the second PMOS MP2 drain electrode connect
Tenth PMOS MP10 source electrode, the 3rd PMOS MP3 drain electrode connect the 11st PMOS MP11 source electrode, the 4th PMOS
MP4 drain electrode connects the 17th PMOS MP17 and the 18th PMOS MP18 source electrode, and the 5th PMOS MP5 drain electrode connects the tenth
Five PMOS MP15 and the 16th PMOS MP16 source electrode, the 8th PMOS MP8 drain electrode connect the 14th PMOS MP14's
Source electrode；
4th NMOS tube MN4 grid leak short circuit and the drain electrode for connecting the 11st PMOS MP11, the 15th NMOS tube MN15
Drain electrode meet the 9th NMOS tube MN9, the 16th NMOS tube MN16 and the 14th PMOS MP14 drain electrode and the 17th NMOS
Pipe MN17 and the 19th PMOS MP19 grid, its source electrode are followed by the 9th NMOS tube MN9 grid by the 3rd electric capacity C3；The
16 NMOS tube MN16 source electrode connection the 18th PMOS MP18 and the 16th PMOS MP16 grid simultaneously passes through the second electricity
It is grounded after holding C2；18th NMOS tube MN18 and the 20th PMOS MP20 gate interconnection connect the 17th NMOS tube MN17 and
19th PMOS MP19 drain electrode, it, which drains, also interconnects and as the output end of the second negative level detector；
First NMOS tube MN1 grid leak interconnects and connects the second NMOS tube MN2 grid and second resistance R2 one end, the
Two resistance R2 other end connection first resistor R1 one end, the first electric capacity C1 one end, the 15th PMOS MP15 and the tenth
Seven PMOS MP17 grid, the equivalent reference voltage V 1 of first resistor R1 another termination, the first electric capacity C1 another termination
Ground；The one of 3rd resistor R3 terminates equivalent reference voltage V 1, the tenth NMOS tube MN10 of another termination drain electrode；It is described equivalent
Reference voltage V 1 is by reference voltage VREFProduced by a voltage follower；Tenth NMOS tube MN10 grid connection the 11st
NMOS tube MN11, the 12nd NMOS tube MN12 grid, the 15th NMOS tube MN15 grid connect the 16th NMOS tube MN16's
Grid；
First PNMOS pipes MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS
MP5, the 6th PMOS MP6, the 7th PMOS MP7, the 8th PMOS MP8, the 19th PMOS MP19 and the 20th PMOS
MP20 source electrode connects supply voltage, the first NMOS tube MN1, the second NMOS tube MN2, the 9th NMOS tube MN9, the 12nd NMOS tube
MN12, the 17th NMOS tube MN17 and the 18th NMOS tube MN18 source ground；
The 13rd NMOS tube MN13 and the 14th NMOS tube MN14 is high pressure LDMOS.
Specifically, the first negative level detector includes the first clamp operational amplifier OP1, the 5th resistance R5, the 6th
Resistance R6, the 21st PMOS MP21, the 22nd PMOS MP22, the 23rd PMOS MP23, the 24th PMOS
Pipe MP24, the 25th PMOS MP25, the 26th PMOS MP26, the 27th PMOS MP27, the 19th NMOS tube
MN19, the 20th NMOS tube MN20, the 21st NMOS tube MN21, the 22nd NMOS tube MN22, the 23rd NMOS tube
MN23,
27th PMOS MP27 grid connects institute as the first input end of first negative level detection circuit
The source electrode of the 13rd NMOS tube MN13 in the second negative level detector is stated, the 26th PMOS MP26 grid is as described
Second input of one negative level detection circuit connects the source electrode of the 14th NMOS tube MN14 in the second negative level detector；
First clamp operational amplifier OP1 positive input connection reference voltage VREF, its negative input connection the tenth
Nine NMOS tube MN19 source electrode and by being grounded after the 5th resistance R5, its output end connect the 19th NMOS tube MN19 grid；
21st PMOS MP21 grid leak short circuit simultaneously connects the 19th NMOS tube MN19 drain electrode, the 22nd PMOS
Pipe MP22, the 23rd PMOS MP23 and the 24th PMOS MP24 grid；
20th NMOS tube MN20 grid leak short circuit and the grid and the 22nd for connecting the 21st NMOS tube MN21
PMOS MP22 drain electrode, its source electrode connect the 26th PMOS MP26 source electrode；21st NMOS tube MN21 drain electrode connects
23rd PMOS MP23 drain electrode and the 25th PMOS MP25 grid, its source electrode are followed by the by the 6th resistance R6
27 PMOS MP27 source electrode；
22nd NMOS tube MN22 grid leak short circuit and the grid and the 24th for connecting the 23rd NMOS tube MN23
PMOS MP24 drain electrode, the 23rd NMOS tube MN23 the 25th PMOS MP25 of drain electrode connection drain electrode are simultaneously used as institute
State the output end of the first negative level detection circuit；
21st PMOS MP21, the 22nd PMOS MP22, the 23rd PMOS MP23, the 24th PMOS
Pipe MP24 and the 25th PMOS MP25 source electrode connect supply voltage, the 26th PMOS MP26 and the 27th PMOS
MP27 drain electrode and the 22nd NMOS tube MN22 and the 23rd NMOS tube MN23 source ground.
Specifically, the ringing detector includes the 7th resistance R7, the 8th resistance R8, the 9th resistance R9, the tenth resistance
R10,28 PMOS MP28, the 29th PMOS MP29, the 30th PMOS MP30, the 31st PMOS MP31,
32nd PMOS MP32, the first DEMOS pipes DEMOS1, the 2nd DEMOS pipes DEMOS2, the 24th NMOS tube MN24,
25 NMOS tube MN25,
First DEMOS pipes DEMOS1 grid leak short circuit and the grid and the 28th for connecting the 2nd DEMOS pipes DEMOS2
PMOS MP28 drain electrode, its source electrode are grounded after the cascaded structure by the 7th resistance R7 and the 9th resistance R9；2nd DEMOS is managed
DEMOS2 drain electrode is followed by the first sampling end of the synchronous commutating control circuit by the 8th resistance R8, and its source electrode connects the 20th
Nine PMOS MP29 drain electrode and the 32nd PMOS MP32 grid；28th PMOS MP28 grid connection second
In 19 PMOS MP29, the 30th PMOS MP30, the 31st PMOS MP31 and first negative level detection circuit
24th PMOS MP24 grid, the 28th PMOS MP28, the 29th PMOS MP29, the 30th PMOS
MP30 and the 31st PMOS MP31 source electrode connect supply voltage,
24th NMOS tube MN24 grid leak short circuit and the grid and the 30th for connecting the 25th NMOS tube MN25
PMOS MP30 drain electrode, the 24th NMOS tube and the 25th NMOS tube MN25 source ground, the 25th drain electrode
Connect the 32nd PMOS MP32 drain electrode and as the output end of the ringing detector, the 31st PMOS MP31 leakage
Pole is followed by the second sampling end of the synchronous commutating control circuit by the tenth resistance R10.
Specifically, the synchronization control module includes the second clamp operational amplifier OP2, the 11st resistance R1, the 12nd
Resistance R12, the 13rd resistance R13, the 14th resistance R14, the 15th resistance Rpull, the 33rd PMOS MP33, the 30th
Four PMOS MP34, the 35th PMOS MP35, the 36th PMOS MP36, the 26th NMOS tube MN26, the 20th
Seven NMOS tube MN27, the 28th NMOS tube MN28 and the 29th NMOS tube MN29,
Second clamp operational amplifier OP2 positive input connection reference voltage VREF, its negative input connection second
16 NMOS tube MN26 source electrode and by being grounded after the 11st resistance R1, its output end connect the 26th NMOS tube MN26's
Grid；
33rd PMOS MP33 grid leak short circuit and the drain electrode and the 34th for connecting the 26th NMOS tube MN26
PMOS MP34 grid, the 34th PMOS MP34 drain electrode connect the 27th NMOS tube MN27 drain electrode, and the 33rd
PMOS MP33 and the 34th PMOS MP34 source electrode connect supply voltage；
35th PMOS MP35 grid leak short circuit and the grid and the 28th for connecting the 36th PMOS MP36
NMOS tube MN28 drain electrode, its source electrode are followed by power supply electricity by the 13rd resistance R13 and the 12nd resistance R12 cascaded structure
Pressure, the 36th PMOS MP36 source electrode pass through the 14th resistance R14 and the 15th resistance RpullCascaded structure be followed by electricity
Source voltage, its 29th NMOS tube MN29 of connection that drains drain electrode and as the output end of the synchronization control module, the tenth
Four resistance R14 and the 15th resistance RpullInput of the series connection point as the synchronization control module；
27th NMOS tube MN27, the 28th NMOS tube MN28 and the 29th NMOS tube MN29 gate interconnection,
Its source grounding.
Specifically, the opening time shroud module and turn-off time shroud module are detecting the rising edge of its input
A low level signal is exported during signal.
Specifically, when the synchronous commutating control circuit is used for anti exciting converter, the output voltage of the anti exciting converter
As the supply voltage of the synchronous commutating control circuit, first sampling end samples synchronous rectification in the anti exciting converter
The drain terminal voltage of pipe, second sampling end sample the source voltage terminal of synchronous rectifier in the anti exciting converter.
Beneficial effects of the present invention are：The present invention is simple in construction, can effectively reduce rectification conduction loss, realizes synchronous
The high efficiency of rectification.Wherein when for anti exciting converter, the second negative level detector realizes minimum Power MOSFET；
Turn-off time shroud module prevents opening by mistake for synchronous rectifier M2 from opening, and opening time shroud module prevents synchronous rectifier M2 mistake
Shut-off；Sampling end is using high tension apparatus LDMOS (i.e. the 13rd NMOS tube MN13 and the 14th NMOS in the second negative level detector
Pipe MN14) and DEMOS (i.e. the first DEMOS pipes DEMOS2 and the 2nd DEMOS pipe DEMOS2 in ringing detector) drain electrode hold
By high pressure, avoid and synchronous rectifier M2 drain terminal VD is clamped with Zener, prevent synchronous rectifier M2 drain terminal VD
Leakage current over the ground；Above measure realizes the high efficiency of synchronous rectification jointly；Synchronization control module is introduced in addition, is realized
Synchronous rectification under continuous current mode CCM.
Brief description of the drawings
Fig. 1 is the applied topology structure chart in the framework and embodiment of the present invention.
Fig. 2 is that circuit is operated in the signal timing diagram under discontinuous conduct mode DCM in embodiment.
Fig. 3 is that circuit is operated in the signal timing diagram under continuous current mode CCM in embodiment.
Fig. 4 is the circuit diagram of the second negative level detector NLD2 in embodiment.
The circuit that Fig. 5 is the first negative level detector NLD1 and ringing detector Ringing Detector in embodiment shows
It is intended to.
Fig. 6 is the circuit diagram of synchronization control module SYNC Controller in embodiment.
Embodiment
Below in conjunction with the accompanying drawings, technical scheme is described in detail：
Anti exciting converter is applied to the dual-mode sync rectifier control circuit proposed by the present invention suitable for DCM and CCM
It is embodiment during flyback, as shown in figure 1, wherein bold portion is the circuit topology of the present invention, it is inclined by internal reference and electric current
Module, ringing detector, the first negative level detector, the second negative level detector, the first S/R latch, the 2nd SR is put to latch
Device, turn-off time shroud module, opening time shroud module, synchronization control module, first and door, second and door, the first Zener
Pipe DZ1, the second Zener DZ2, drive module composition, the first sampling end sampling anti exciting converter in synchronous rectifier M2 drain electrode
Level VD, the second sampling end sample-synchronous rectifying tube M2 source level, the input of synchronization control module pass through inverse-excitation converting
Plug-in resistance R in deviceSYNCWith plug-in coupled capacitor CSYNCCascaded structure after connect primary side switch pipe drain electrode.In the present embodiment
Synchronous commutating control circuit powered by anti exciting converter Flyback output, internal reference and current offset module give it
Complementary modul block provides reference voltage Vref and bias current Ibias.The specific works mode of circuit in the present embodiment is described below：
If the secondary inductance electric current I before switching tube M1 unlatchingsSECZero is had descended to, system is operated in DCM (electric currents
Discontinuous mode) pattern.Under DCM patterns, when switching tube M1 is closed, synchronous rectifier M2 drain electrode level VD drastically declines, when the
One negative level detector detects exports high level when synchronous rectifier M2 drain-source voltages VDS drops to below -150mV, by
The output set of two S/R latches is high level, is opened synchronous rectifier M2 by drive module, while opening time shielding mould
Block detects the rising edge signal of the first negative level detector output, exports a low level pulse, and shielding comes from the second negative electricity
The signal of flat detector, prevent that small sample perturbations caused by synchronous rectifier M2 drain electrode level VD make when synchronous rectifier M2 from opening
Synchronous rectification M2 is turned off by mistake, in synchronous rectifier M2 open stages, secondary inductance electric current ISECSupplying power for outside.With secondary electrical
Feel Ns energy expenditure, secondary inductance electric current ISECIt is gradually reduced, when the drain voltage for detecting synchronous rectifier M2 drops to zero
When, system judges secondary inductance electric current ISECAlso zero is had descended to, synchronous rectifier M2 is closed.It is but right under actual conditions
It can not accomplish definitely accurately, if in secondary inductance electric current I in synchronous rectifier M2 drain electrode level VD zero passage detectionSEC
Synchronous rectifier M2 is also not turned off when dropping to zero, load current will by secondary inductance and conducting synchronous rectifier M2 to
Ground pours in down a chimney, and seriously reduces rectification efficiency, for this reason, it may be necessary in secondary inductance electric current ISECBy synchronous rectifier M2 before dropping to zero
Shut-off.And when turning off synchronous rectifier M2 in advance, inductive current ISECHave not degraded to zero, synchronous rectifier M2 body will be passed through
Diode D2 afterflows, because body diode D2 conduction voltage drop is bigger (generally 0.7V), therefore the conducting damage in the time
Loss-rate is larger, reduces rectification efficiency.Thus the negative threshold value test point closer to zero is advantageous to reduce body diode D2 conducting damages
Consumption.The scheme of the present embodiment is when the second negative level detector detects that synchronous rectifier M2 drain-source voltages VDS is more than -5mV
High level is exported, now opening time shroud module timing is over, and the second latch SR2 is reset to low level, passes through
Drive module turns off synchronous rectifier M2.After synchronous rectifier M2 shut-offs, it, which drains, to cause VD electric because LC vibrates
Pressure produces ringing, exports high level when ring detection module detects that VDS voltages are higher than 1.5V, judges that VD starts to shake
Bell, the first S/R latch SR1 are set to high level, and turn-off time shroud module detects the first S/R latch SR1 rising
One section of low level pulse is produced along signal, the signal from the first negative level detector NLD1 is shielded, prevents synchronous rectifier
M2, which is opened by mistake, to be opened.Signal sequence under DCM patterns is as shown in Figure 2.In the present embodiment the first negative level detector detect-
150mV and-the 5mV of the second negative level detector detection is preferred value.
If when synchro switch pipe M1 were opened, secondary inductance electric current ISECHave not degraded to zero, system enters CCM (electric currents
Continuous mode) pattern.Due to secondary inductance electric current ISECZero will not be dropped to, so cut-off signals can not be produced next in time
The individual cycle closes synchronous rectifier before arriving, therefore the synchronous rectification scheme of the self-driven pattern of in general is not suitable for CCM patterns.
In order to realize the synchronous rectification under CCM and DCM patterns simultaneously, it is synchronously whole to carry out quick closedown invention introduces synchronization control module
Flow tube M2.Concrete operating principle is：When primary side switch pipe M1 is opened, M1 drain terminal moments are pulled to low level, the low level pulse
Pass through plug-in coupled capacitor C in anti exciting converterSYNCWith plug-in resistance RSYNCQuick coupling is to synchronization control module, Synchronization Control
The input of module is the 14th resistance R14 and the 15th resistance RpullTie point be SYNC ends, when synchronization control module
The SYNC level at SYNC ends is less than VCC-2V (value is empirical value), exports a low level signal and is sent into the second S/R latch
SR2, synchronous rectifier M2 is closed.First Zener DZ1With the second Zener DZ2For being clamped to SYNC level, prevent
Too high SYNC level causes to damage to circuit.Signal sequence under CCM patterns is as shown in Figure 3.
Second negative level detector in the present embodiment is as shown in figure 4, the module is realized to synchronous rectifier grid end simultaneously
Level VD and source level VS sampling and the detection of -5mV level.The sampling pipe of second negative level detector is the 13rd NMOS
Pipe MN13 and the 14th NMOS tube MN14 sampling high-voltage LDMOSs (LDMOS), it is resistance to using its drain terminal
Characteristic is pressed to bear the high pressure at VD ends, the 13rd NMOS tube MN13 source voltage terminal is synchronous rectifier M2 drain terminal voltage VD
Sampled voltage VDSENSE, the 14th NMOS tube MN14 source voltage terminal is synchronous rectifier M2 source voltage terminal VS sampled voltage
VSSENSE, by the signal sampled and VSSENSESignal is sent into the module in itself and the first negative level detector.Second negative level
The operation principle of detector refers to patent 201710274231.5.
First negative level detector framework is as shown in Figure 5.The VD sampled by the second negative level detectorSENSESignal and
VSSENSESignal is sent into the first negative level detector, and the turn threshold of the first negative level detector is analyzed as follows：
I=VREF/R5 (1)
V-=VDSENSE+VGS27+IR6 (2)
V+=VSSENSE+VGS27 (3)
(1)-(2)：
V--V+=VDSENSE-VSSENSE+IR6 (4)
VDSENSE-VSSENSE=VD-VS (5)
Simultaneous (3), (4), (5)：
Thus the turn threshold for obtaining the first negative level detector is6th resistance R is rationally set6, the 5th
Resistance R5- 150mV the threshold values that can be needed of value.
Ring detection module using two DEMOS (DEMOS1 and DEMOS2) drain terminal voltage endurance as shown in figure 5, held
By high VD voltages, and when VD voltages are relatively low, DEMOS drain terminal voltage is less than its source voltage terminal, and LDMOS source and drain realizes work(
Can exchange, finally realize normal voltage ratio compared with.The PMOS MP8 of 11st PMOS MP11 equal proportions mirror image the 8th and the 9th
PMOS MP9 electric current, realize power supply flow into VD and VS ends electric current it is equal, reduce the error of VD and VS sampling.
R7=R8 is set, so the upset point of ringing detector is
VD=VTHARM (8)
Rationally the 9th resistance R9 value is set to obtain the turn threshold V of ring detection moduleTHARM=1.5V.
The circuit framework of synchronization control module is as shown in Figure 6.The turn threshold V of the synchronization control module circuitTH,SYNCCan
To be expressed as：
Work as VPRIWhen low level pulse arrives, signal passes through electric capacity CSYNCWith resistance RSYNCIt is coupled to synchronous detection module
SYNC ends, SYNC ends will take one electric current I away from supply voltage VCCSYNC, so having：
VSYNC=VCC-ISYNCRpull (10)
Work as ISYNCIt is enough to make VSYNC<VTH,SYNCWhen, comparator will be overturn, and synchronous rectifier M2 is closed.
Plug-in resistance RSYNCDetermined by (11) formula：
VSYNCIt is pulled to and is less than VTH,SYNCTime should at least exceed response time tMINIt just can guarantee that synchronization control module energy
Enough responses, so plug-in coupled capacitor CSYNCValue can be determined by (12) formula：
Summary, the present invention propose a kind of high efficiency DCM/CCM dual-mode sync rectifier control circuits, utilize second
Negative level detector realizes minimum Power MOSFET；Synchronous rectifier M2 mistake is prevented using turn-off time shroud module
Open, opening time shroud module prevents synchronous rectifier M2 mistake from turning off；VD sampling ends using high tension apparatus LDMOS and
High pressure is born in DEMOS drain electrode, avoids and VD ends are clamped with Zener, prevent VD ends leakage current over the ground.More than
Measure realizes the high efficiency of synchronous rectification jointly.Synchronization control module is introduced in addition, and the synchronization realized under CCM patterns is whole
Stream.
One of ordinary skill in the art can make various do not depart from originally according to these technical inspirations disclosed by the invention
The other various specific deformations and combination, these deformations and combination of invention essence are still within the scope of the present invention.
Claims (8)
1. suitable for DCM and CCM dual-mode sync rectifier control circuit, including opening time shroud module, turn-off time screen
Cover module, the first S/R latch, the second S/R latch, first with door, second with door, drive module, the first Zener (Dz1) and
Second Zener (Dz2),
Characterized in that, the synchronous commutating control circuit also includes the first negative level detector, the second negative level detector, shaken
Bell detector and synchronization control module,
The second negative level detector includes sampling pipe, and the sampling pipe includes the 13rd NMOS tube (MN13) and the 14th
NMOS tube (MN14), the drain electrode of the 13rd NMOS tube (MN13) sample as the first of the synchronous commutating control circuit
End, its source electrode export the first sampled voltage to the first input end of the first negative level detector；14th NMOS tube
(MN14) second sampling end of the drain electrode as the synchronous commutating control circuit, its source electrode the second sampled voltage of output is to described
Second input of the first negative level detector；
The input of the ringing detector connects the first sampling end of the synchronous commutating control circuit；First SR is latched
The S ends of device connect the output end of the ringing detector, and its R end connects the input of the drive module, described in the connection of its Q end
The input of shut-in time shroud module and described first with the first input end of door；Described first connects with the second input of door
Connect the output end of the turn-off time shroud module, its 3rd input connect the first negative level detector output end and
The input of the opening time shroud module；Described second is connected the second negative level detector with the first input end of door
Output end, its second input connects the output end of the opening time shroud module；The S ends of second S/R latch connect
The output end of described first and door is connect, its R end connects the described second output with the output end and the synchronization control module of door
End, its Q end connect the input of the drive module；
First Zener (the Dz1) anode connect the second Zener (Dz2) negative electrode and the synchronization control module input
End, its negative electrode meet supply voltage, the second Zener (Dz2) plus earth；The output end of the drive module is as the synchronization
The output end of rectifier control circuit.
2. the dual-mode sync rectifier control circuit according to claim 1 suitable for DCM and CCM, it is characterised in that institute
Stating synchronous commutating control circuit also includes internal reference and current offset module, for producing reference voltage (VREF) and biased electrical
Stream.
3. the dual-mode sync rectifier control circuit according to claim 2 suitable for DCM and CCM, it is characterised in that institute
Stating the second negative level detection circuit also includes first resistor (R1), second resistance (R2), 3rd resistor (R3), the 4th resistance
(R4), the first electric capacity (C1), the second electric capacity (C2), the first NMOS tube (MN1), the second NMOS tube (MN2), the 3rd NMOS tube
(MN3), the 4th NMOS tube (MN4), the 5th NMOS tube (MN5), the 6th NMOS tube (MN6), the 7th NMOS tube (MN7), the 8th
NMOS tube (MN8), the 9th NMOS tube (MN9), the tenth NMOS tube (MN10), the 11st NMOS tube (MN11), the 12nd NMOS tube
(MN12), the 15th NMOS tube (MN15), the 16th NMOS tube (MN16), the 17th NMOS tube (MN17), the 18th NMOS tube
(MN18), the first PMOS (MP1), the second PMOS (MP2), the 3rd PMOS (MP3), the 4th PMOS (MP4), the 5th
PMOS (MP5), the 6th PMOS (MP6), the 7th PMOS (MP7), the 8th PMOS (MP8), the 9th PMOS (MP9),
Tenth PMOS (MP10), the 11st PMOS (MP11), the 12nd PMOS (MP12), the 13rd PMOS (MP13),
14 PMOSs (MP14), the 15th PMOS (MP15), the 16th PMOS (MP16), the 17th PMOS (MP17),
18 PMOSs (MP18), the 19th PMOS (MP19) and the 20th PMOS (MP20),
The gate interconnection of 13rd NMOS tube (MN13) and the 14th NMOS tube (MN14), the source electrode of the 13rd NMOS tube (MN13)
Connect the 7th NMOS tube (MN7), the 4th NMOS tube (MN4), the source electrode and the 17th PMOS of the 11st NMOS tube (MN11)
(MP17), the drain electrode of the 12nd NMOS tube (MN12), the 3rd NMOS tube (MN3) of source electrode connection of the 14th NMOS tube (MN14),
8th NMOS tube (MN8) and the source electrode of the tenth NMOS tube (MN10), the drain electrode of the 18th PMOS (MP18) and the 4th resistance
(R4) one end, the other end of the 4th resistance (R4) connect the drain electrode of the 11st NMOS tube (MN11)；
The gate interconnection of 7th NMOS tube (MN7) and the 8th NMOS tube (MN8) simultaneously connects the 5th NMOS tube (MN5) and the 12nd
The drain electrode of PMOS (MP12), the drain electrode of the 7th NMOS tube (MN7) connect the source electrode and the 16th PMOS of the 5th NMOS tube (MN5)
The drain electrode of (MP16) is managed, the drain electrode of the 8th NMOS tube (MN8) connects the source electrode and the 15th PMOS of the 6th NMOS tube (MN6)
(MP15) drain electrode；
The gate interconnection of 5th NMOS tube (MN5) and the 6th NMOS tube (MN6) and grid and the leakage for connecting the 3rd NMOS tube (MN3)
Pole and the drain electrode of the tenth PMOS (MP10), the drain electrode of the 13rd PMOS (MP13) connect the leakage of the 6th NMOS tube (MN6)
Pole and the grid of the 9th NMOS tube (MN9), its source electrode connect the drain electrode of the 7th PMOS (MP7), and its grid connects the 9th PMOS
(MP9), the tenth PMOS (MP10), the 11st PMOS (MP11), the 12nd PMOS (MP12) and the 14th PMOS
(MP14) grid and the drain electrode of the 9th PMOS (MP9) and the second NMOS tube (MN2)；
The drain electrode of 6th PMOS (MP6) connects the source electrode of the 12nd PMOS (MP12), its grid connect the first PMOS (MP1),
Second PMOS (MP2), the 3rd PMOS (MP3), the 4th PMOS (MP4), the 5th PMOS (MP5), the 7th PMOS
(MP7) and the grid of the 8th PMOS (MP8) and the source electrode of the drain electrode of the first PMOS (MP1) and the 9th PMOS (MP9),
The drain electrode of second PMOS (MP2) connects the source electrode of the tenth PMOS (MP10), and the drain electrode of the 3rd PMOS (MP3) connects the 11st
The source electrode of PMOS (MP11), the drain electrode of the 4th PMOS (MP4) connect the 17th PMOS (MP17) and the 18th PMOS
(MP18) source electrode, the drain electrode of the 5th PMOS (MP5) connect the 15th PMOS (MP15) and the 16th PMOS (MP16)
Source electrode, the drain electrode of the 8th PMOS (MP8) connect the source electrode of the 14th PMOS (MP14)；
The grid leak short circuit of 4th NMOS tube (MN4) and the drain electrode for connecting the 11st PMOS (MP11), the 15th NMOS tube
(MN15) drain electrode connect the drain electrode of the 9th NMOS tube (MN9), the 16th NMOS tube (MN16) and the 14th PMOS (MP14) with
And the 17th NMOS tube (MN17) and the 19th PMOS (MP19) grid, its source electrode is followed by the 9th by the 3rd electric capacity (C3)
The grid of NMOS tube (MN9)；The source electrode of 16th NMOS tube (MN16) connects the 18th PMOS (MP18) and the 16th PMOS
Manage the grid of (MP16) and be grounded afterwards by the second electric capacity (C2)；18th NMOS tube (MN18) and the 20th PMOS (MP20)
Gate interconnection connect the drain electrode of the 17th NMOS tube (MN17) and the 19th PMOS (MP19), it, which drains, also interconnects and conduct
The output end of the second negative level detector；
The grid leak of first NMOS tube (MN1) interconnects and connects the grid of the second NMOS tube (MN2) and one end of second resistance (R2),
One end of the other end connection first resistor (R1) of second resistance (R2), one end of the first electric capacity (C1), the 15th PMOS
(MP15) and the 17th PMOS (MP17) grid, the equivalent reference voltage (V1) of another termination of first resistor (R1),
The other end ground connection of one electric capacity (C1)；The one of 3rd resistor (R3) terminates equivalent reference voltage (V1), another termination the tenth
The drain electrode of NMOS tube (MN10)；The equivalent reference voltage (V1) is by reference voltage (VREF) produced by a voltage follower；
The 11st NMOS tube (MN11) of grid connection of tenth NMOS tube (MN10), the grid of the 12nd NMOS tube (MN12), the 15th
The grid of NMOS tube (MN15) connects the grid of the 16th NMOS tube (MN16)；
First PNMOS pipes (MP1), the second PMOS (MP2), the 3rd PMOS (MP3), the 4th PMOS (MP4), the 5th PMOS
Manage (MP5), the 6th PMOS (MP6), the 7th PMOS (MP7), the 8th PMOS (MP8), the 19th PMOS (MP19) and
The source electrode of 20th PMOS (MP20) connects supply voltage, the first NMOS tube (MN1), the second NMOS tube (MN2), the 9th NMOS tube
(MN9), the source ground of the 12nd NMOS tube (MN12), the 17th NMOS tube (MN17) and the 18th NMOS tube (MN18)；
13rd NMOS tube (MN13) and the 14th NMOS tube (MN14) are high pressure LDMOS.
4. the dual-mode sync rectifier control circuit suitable for DCM and CCM according to Claims 2 or 3, its feature exist
In, the first negative level detector include the first clamp operational amplifier (OP1), the 5th resistance (R5), the 6th resistance (R6),
21st PMOS (MP21), the 22nd PMOS (MP22), the 23rd PMOS (MP23), the 24th PMOS
(MP24), the 25th PMOS (MP25), the 26th PMOS (MP26), the 27th PMOS (MP27), the 19th
NMOS tube (MN19), the 20th NMOS tube (MN20), the 21st NMOS tube (MN21), the 22nd NMOS tube (MN22),
23 NMOS tubes (MN23),
The grid of 27th PMOS (MP27) is as described in the first input end connection of first negative level detection circuit
The source electrode of 13rd NMOS tube (MN13) in second negative level detector, described in the grid of the 26th PMOS (MP26) is used as
Second input of the first negative level detection circuit connects the 14th NMOS tube (MN14) in the second negative level detector
Source electrode；
The positive input connection reference voltage (V of first clamp operational amplifier (OP1)REF), its negative input connection the tenth
The source electrode of nine NMOS tubes (MN19) is simultaneously grounded afterwards by the 5th resistance (R5), and its output end connects the 19th NMOS tube (MN19)
Grid；
The grid leak short circuit of 21st PMOS (MP21) simultaneously connects the drain electrode of the 19th NMOS tube (MN19), the 22nd PMOS
Manage the grid of (MP22), the 23rd PMOS (MP23) and the 24th PMOS (MP24)；
The grid leak short circuit of 20th NMOS tube (MN20) and the grid and the 22nd for connecting the 21st NMOS tube (MN21)
The drain electrode of PMOS (MP22), its source electrode connect the source electrode of the 26th PMOS (MP26)；21st NMOS tube (MN21)
Drain electrode connects the drain electrode of the 23rd PMOS (MP23) and the grid of the 25th PMOS (MP25), and its source electrode passes through the 6th electricity
Resistance (R6) is followed by the source electrode of the 27th PMOS (MP27)；
The grid leak short circuit of 22nd NMOS tube (MN22) and the grid and the 24th for connecting the 23rd NMOS tube (MN23)
The drain electrode of PMOS (MP24), the drain electrode of the 23rd NMOS tube (MN23) connect the drain electrode of the 25th PMOS (MP25) simultaneously
Output end as first negative level detection circuit；
21st PMOS (MP21), the 22nd PMOS (MP22), the 23rd PMOS (MP23), the 24th
The source electrode of PMOS (MP24) and the 25th PMOS (MP25) connects supply voltage, the 26th PMOS (MP26) and second
The drain electrode of 17 PMOSs (MP27) and the source electrode of the 22nd NMOS tube (MN22) and the 23rd NMOS tube (MN23) connect
Ground.
5. the dual-mode sync rectifier control circuit according to claim 4 suitable for DCM and CCM, it is characterised in that institute
Stating ringing detector includes the 7th resistance (R7), the 8th resistance (R8), the 9th resistance (R9), the tenth resistance (R10), 28
PMOS (MP28), the 29th PMOS (MP29), the 30th PMOS (MP30), the 31st PMOS (MP31),
32 PMOSs (MP32), the first DEMOS pipes (DEMOS1), the 2nd DEMOS pipes (DEMOS2), the 24th NMOS tube
(MN24), the 25th NMOS tube (MN25),
The grid leak short circuit of first DEMOS pipes (DEMOS1) and the grid and the 28th for connecting the 2nd DEMOS pipes (DEMOS2)
The drain electrode of PMOS (MP28), its source electrode after the cascaded structure of the 7th resistance (R7) and the 9th resistance (R9) by being grounded；Second
The drain electrode of DEMOS pipes (DEMOS2) is followed by the first sampling end of the synchronous commutating control circuit by the 8th resistance (R8), its
Source electrode connects the drain electrode of the 29th PMOS (MP29) and the grid of the 32nd PMOS (MP32)；28th PMOS
(MP28) grid connects the 29th PMOS (MP29), the 30th PMOS (MP30), the 31st PMOS (MP31)
The grid of the 24th PMOS (MP24) in circuit, the 28th PMOS (MP28), the are detected with first negative level
The source electrode of 29 PMOSs (MP29), the 30th PMOS (MP30) and the 31st PMOS (MP31) connects supply voltage；
The grid leak short circuit of 24th NMOS tube (MN24) and the grid and the 30th for connecting the 25th NMOS tube (MN25)
The source ground of the drain electrode of PMOS (MP30), the 24th NMOS tube and the 25th NMOS tube (MN25), the 25th
Drain electrode connects the drain electrode of the 32nd PMOS (MP32) and as the output end of the ringing detector, the 31st PMOS
(MP31) drain electrode is followed by the second sampling end of the synchronous commutating control circuit by the tenth resistance (R10).
6. the dual-mode sync rectifier control circuit suitable for DCM and CCM according to claim 2 or 5, its feature exist
In the synchronization control module includes the second clamp operational amplifier (OP2), the 11st resistance (R1), the 12nd resistance
(R12), the 13rd resistance (R13), the 14th resistance (R14), the 15th resistance (Rpull), the 33rd PMOS (MP33),
34th PMOS (MP34), the 35th PMOS (MP35), the 36th PMOS (MP36), the 26th NMOS tube
(MN26), the 27th NMOS tube (MN27), the 28th NMOS tube (MN28) and the 29th NMOS tube (MN29),
The positive input connection reference voltage (V of second clamp operational amplifier (OP2)REF), its negative input connection second
The source electrode of 16 NMOS tubes (MN26) is simultaneously grounded afterwards by the 11st resistance (R1), and its output end connects the 26th NMOS tube
(MN26) grid；
The grid leak short circuit of 33rd PMOS (MP33) and the drain electrode and the 34th for connecting the 26th NMOS tube (MN26)
The grid of PMOS (MP34), the drain electrode of the 34th PMOS (MP34) connect the drain electrode of the 27th NMOS tube (MN27), the
The source electrode of 33 PMOSs (MP33) and the 34th PMOS (MP34) connects supply voltage；
The grid leak short circuit of 35th PMOS (MP35) and the grid and the 28th for connecting the 36th PMOS (MP36)
The drain electrode of NMOS tube (MN28), its source electrode are followed by electricity by the cascaded structure of the 13rd resistance (R13) and the 12nd resistance (R12)
Source voltage, the source electrode of the 36th PMOS (MP36) pass through the 14th resistance (R14) and the 15th resistance (Rpull) series connection
Structure is followed by supply voltage, and it, which drains, connects the drain electrode of the 29th NMOS tube (MN29) and as the synchronization control module
Output end, the 14th resistance (R14) and the 15th resistance (Rpull) input of the series connection point as the synchronization control module；
The grid of 27th NMOS tube (MN27), the 28th NMOS tube (MN28) and the 29th NMOS tube (MN29) is mutual
Even, its source grounding.
7. the dual-mode sync rectifier control circuit according to claim 1 suitable for DCM and CCM, it is characterised in that institute
State opening time shroud module and turn-off time shroud module exported when detecting the rising edge signal of its input one it is low
Level signal.
8. the dual-mode sync rectifier control circuit according to claim 1 suitable for DCM and CCM, it is characterised in that institute
When stating synchronous commutating control circuit and being used for anti exciting converter, the output voltage of the anti exciting converter is as the synchronous rectification control
The supply voltage of circuit processed, first sampling end samples the drain terminal voltage of synchronous rectifier in the anti exciting converter, described
Second sampling end samples the source voltage terminal of synchronous rectifier in the anti exciting converter.
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| CN201710564643.2A CN107346943B (en) | 2017-07-12 | 2017-07-12 | Dual-mode sync rectifier control circuit suitable for DCM and CCM |
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| CN201710564643.2A CN107346943B (en) | 2017-07-12 | 2017-07-12 | Dual-mode sync rectifier control circuit suitable for DCM and CCM |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108494277A (en) * | 2018-05-07 | 2018-09-04 | 电子科技大学 | A kind of synchronous commutating control circuit improving electric efficiency |
| CN108494232A (en) * | 2018-05-07 | 2018-09-04 | 电子科技大学 | A kind of synchronous commutating control circuit for preventing electric current from pouring in down a chimney |
| CN108494276A (en) * | 2018-05-07 | 2018-09-04 | 电子科技大学 | A kind of synchronous rectification driving circuit |
| CN108566104A (en) * | 2018-05-07 | 2018-09-21 | 电子科技大学 | A kind of synchronous commutating control circuit |
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| CN109586581A (en) * | 2018-12-15 | 2019-04-05 | 华南理工大学 | Digital Realization device for full-bridge DC/DC transducer synchronous rectification |
| WO2020015391A1 (en) * | 2018-07-17 | 2020-01-23 | 东南大学 | Control method for improving output precision of switching power supply |
| CN111192917A (en) * | 2019-11-27 | 2020-05-22 | 成都芯源***有限公司 | Transverse field effect transistor |
| CN111865055A (en) * | 2020-07-27 | 2020-10-30 | 电子科技大学 | Synchronous rectification drive circuit for pulling down grid voltage of synchronous rectification tube in advance |
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| CN112910227A (en) * | 2021-03-19 | 2021-06-04 | 中国电子科技集团公司第五十八研究所 | Flyback power supply system and control method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100730090B1 (en) * | 2006-04-12 | 2007-06-19 | 삼성전기주식회사 | Flyback circuit comprising synchronous rectifier |
| CN101431297A (en) * | 2008-11-26 | 2009-05-13 | 天宝电子（惠州）有限公司 | Synchronous rectifier |
| CN104539163A (en) * | 2014-12-19 | 2015-04-22 | 广州金升阳科技有限公司 | Synchronous rectification control method for flyback converter and control module of synchronous rectification control method |
| CN105048836A (en) * | 2015-09-01 | 2015-11-11 | 中国电子科技集团公司第四十三研究所 | Switching power supply flyback synchronous rectification self-driving circuit |
-
2017
- 2017-07-12 CN CN201710564643.2A patent/CN107346943B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100730090B1 (en) * | 2006-04-12 | 2007-06-19 | 삼성전기주식회사 | Flyback circuit comprising synchronous rectifier |
| CN101431297A (en) * | 2008-11-26 | 2009-05-13 | 天宝电子（惠州）有限公司 | Synchronous rectifier |
| CN104539163A (en) * | 2014-12-19 | 2015-04-22 | 广州金升阳科技有限公司 | Synchronous rectification control method for flyback converter and control module of synchronous rectification control method |
| CN105048836A (en) * | 2015-09-01 | 2015-11-11 | 中国电子科技集团公司第四十三研究所 | Switching power supply flyback synchronous rectification self-driving circuit |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108494276B (en) * | 2018-05-07 | 2019-10-18 | 电子科技大学 | A kind of synchronous rectification driving circuit |
| CN108494232A (en) * | 2018-05-07 | 2018-09-04 | 电子科技大学 | A kind of synchronous commutating control circuit for preventing electric current from pouring in down a chimney |
| CN108494276A (en) * | 2018-05-07 | 2018-09-04 | 电子科技大学 | A kind of synchronous rectification driving circuit |
| CN108566104A (en) * | 2018-05-07 | 2018-09-21 | 电子科技大学 | A kind of synchronous commutating control circuit |
| CN108494277A (en) * | 2018-05-07 | 2018-09-04 | 电子科技大学 | A kind of synchronous commutating control circuit improving electric efficiency |
| WO2020015391A1 (en) * | 2018-07-17 | 2020-01-23 | 东南大学 | Control method for improving output precision of switching power supply |
| CN109088532B (en) * | 2018-09-14 | 2020-02-18 | 电子科技大学 | Current type segmented gate drive circuit with active clamp |
| CN109088532A (en) * | 2018-09-14 | 2018-12-25 | 电子科技大学 | A kind of current mode segmentation gate driving circuit with active clamp |
| CN109586581A (en) * | 2018-12-15 | 2019-04-05 | 华南理工大学 | Digital Realization device for full-bridge DC/DC transducer synchronous rectification |
| CN111192917A (en) * | 2019-11-27 | 2020-05-22 | 成都芯源***有限公司 | Transverse field effect transistor |
| CN111192917B (en) * | 2019-11-27 | 2023-08-18 | 成都芯源***有限公司 | Lateral field effect transistor |
| CN111865055A (en) * | 2020-07-27 | 2020-10-30 | 电子科技大学 | Synchronous rectification drive circuit for pulling down grid voltage of synchronous rectification tube in advance |
| CN111934525A (en) * | 2020-08-10 | 2020-11-13 | 电子科技大学 | Negative level detection circuit |
| CN111934525B (en) * | 2020-08-10 | 2023-04-28 | 电子科技大学 | Negative level detection circuit |
| CN112910227A (en) * | 2021-03-19 | 2021-06-04 | 中国电子科技集团公司第五十八研究所 | Flyback power supply system and control method |
| CN112910227B (en) * | 2021-03-19 | 2022-04-26 | 中国电子科技集团公司第五十八研究所 | Flyback power supply system and control method |
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