CN107316659A - Memory power down time section localization method and system power failure guard method - Google Patents
Memory power down time section localization method and system power failure guard method Download PDFInfo
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- CN107316659A CN107316659A CN201710508617.8A CN201710508617A CN107316659A CN 107316659 A CN107316659 A CN 107316659A CN 201710508617 A CN201710508617 A CN 201710508617A CN 107316659 A CN107316659 A CN 107316659A
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- power down
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
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Abstract
The invention discloses a kind of memory power down time section localization method, including：Using first time period as step-length, progressively power down is carried out to instruction process and tested, orient the programming time section programmed in memory in the instruction process；Progressively power down test is gradually carried out in programming time section, orient the power down time section of the memory, in each time positions, the power down test step-length that progressively power down test is used next time is less than the power down test step-length that last progressively power down test is used, next time progressively power down test progressively power down is tested and carried out in oriented power down time section upper once.Instruction process is gradually positioned, the test step long period of power down test is sequentially reduced in being positioned at each time, gradually to orient power down time section during memory program, can realize and memory power down time section is accurately positioned.Invention additionally discloses a kind of system power failure guard method using above-mentioned memory power down time section localization method.
Description
Technical field
The present invention relates to power down technical field of measurement and test, more particularly to a kind of memory power down time section localization method.This
Invention further relates to a kind of system power failure guard method.
Background technology
In the prior art, in the assignment test that power down time section is carried out to memory in system, whole piece instruction process is entered
Row power down is tested, if testing time step-length sets too small, whole power down can be caused to test consumed overlong time, and is tested
Time step sets larger, and the hit rate of memory power down time section can be reduced again.
Therefore, the quick and precisely positioning to memory power down time section how is realized, lacking for prior art presence is overcome
Point, just turns into those skilled in the art's technical issues that need to address.
The content of the invention
It is an object of the invention to provide a kind of memory power down time section localization method, when can realize to memory power down
Between section be accurately positioned.The present invention also provides a kind of system power failure guard method.
To achieve the above object, the present invention provides following technical scheme：
A kind of memory power down time section localization method, including：
Using first time period as step-length, to instruction process carry out progressively power down test, orient in the instruction process
The programming time section programmed in memory；
Progressively power down test is gradually carried out in programming time section, the power down time section of the memory is oriented,
In each time positions, the power down test step-length that progressively power down test is used next time is less than what last progressively power down test was used
Step-length is tested in power down, next time progressively power down test progressively oriented power down time Duan Zhongjin is tested in power down upper once
OK.
Alternatively, it is described using first time period as step-length, progressively power down is carried out to instruction process and tested, the finger is oriented
The programming time section programmed in memory during order includes：
The value in memory storage area described in instruction process is progressively read, by the memory storage area
Value be by the period of modified values and be other values period, be defined as programming time section, other values, which refer to, to be different from
It is unmodified to be worth and by the value of modified values.
Alternatively, carrying out progressively power down test includes：
It is electric on card, and receive the reading for being used to read the value in memory storage area that the memory sends and refer to
Order, in the card power down after preset time period；
Card is upper electric again, reads the value in the memory storage area.
Alternatively, also include after the value read in the memory storage area：
Judge whether read out value is unmodified value, by modified values or other values, and other values, which refer to be different from, does not repair
Revaluate and the value by modified values；
If the value read out is unmodified value, show that power down time point does not reach the programming process of the memory；
If the value read out is by modified values, show power down time point after the programming process of the memory；
If the value read out is other values, show that power down time point is in the programming process of the memory.
Alternatively, it is described that progressively power down test is gradually carried out in programming time section, orient the memory
Power down time section includes：
Using second time period as step-length, progressively power down test is carried out in programming time section, the storage is oriented
Value in device storage region is the period of other values, and other values, which refer to, is different from unmodified value and the value by modified values；
Using the 3rd period as step-length, the value in the memory storage area oriented is the time of other values
Progressively power down test is carried out in section, power down time section is oriented；
The second time period is less than the first time period, and the 3rd period is less than the second time period.
A kind of system power failure guard method, including：
When recognizing the system platform and power down occur, triggering power down protection starts and recorded；
Legacy data is write into backup area；
Write new data into target area；
Power down protection is marked to complete after the completion of power down protection；
Using above-described memory power down time section localization method, successively to power down protection beginning label process, standby
Part legacy data process, write-in new data process, power down protection complete labeling process progress power down time section and positioned.
Alternatively, to power down protection beginning label process, backup legacy data process, write-in new data process, power down protection
Complete labeling process and carry out power down time section positioning, carried out before data rewind mechanism is enabled.
As shown from the above technical solution, memory power down time section localization method provided by the present invention, first with first
Period is step-length, and carrying out progressively power down to instruction process tests, and orients the programming programmed in memory in instruction process
Period, progressively power down test then is carried out in the programming time section oriented, in each time positions, is progressively fallen next time
The power down test step-length that electrical testing is used is less than the power down test step-length that last progressively power down test is used, and progressively falls next time
Progressively test in power down time section of oriented carry out upper once by power down for electrical testing.Memory power down time Duan Ding of the present invention
Position method, is gradually positioned to instruction process, and the test step long period of power down test is sequentially reduced in being positioned at each time, is come
Power down time section during memory program is gradually oriented, can realize and memory power down time section is accurately positioned.
System power failure guard method provided by the present invention, when recognizing system platform and power down occur, triggering power down is protected
Shield starts and recorded, and legacy data is write into backup area；Then target area is write new data into, is marked after the completion of power down protection
Remember that power down protection is completed.Power down time section is carried out successively to each process by using memory power down time section localization method
Assignment test, can realize to system during each power down time section be accurately positioned.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is a kind of flow chart of memory power down time section localization method provided in an embodiment of the present invention；
Fig. 2 is a kind of flow chart of system power failure guard method provided in an embodiment of the present invention.
Embodiment
In order that those skilled in the art more fully understand the technical scheme in the present invention, below in conjunction with of the invention real
The accompanying drawing in example is applied, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described implementation
Example only a part of embodiment of the invention, rather than whole embodiments.Based on the embodiment in the present invention, this area is common
The every other embodiment that technical staff is obtained under the premise of creative work is not made, should all belong to protection of the present invention
Scope.
It refer to Fig. 1, a kind of memory power down time section localization method provided in an embodiment of the present invention, including step：
S10：Using first time period as step-length, progressively power down is carried out to instruction process and tested, the instruction process is oriented
In program in memory programming time section.
In this specific step, using first time period as step-length, the memory storage area described in instruction process is progressively read
Value in domain, by the value in the memory storage area be by the period of modified values and be other values period, really
It is set to the programming time section, other values, which refer to, is different from unmodified value and the value by modified values.
In card and system storage process of exchange, if in the presence of the programming process to memory, after programming process is first wipes
Write, accordingly, the storage duration section of value includes in memory storage area：Initial value stage, programming value stage, other values
Stage.
The initial value stage：Card receives instruction, using progress logical process.In this phase process in storage region value not by
Modification.
The programming value stage：Completed using modification data, card response data, in this phase process in storage region value by
Modification.
Other value stages：Including erase process, programming process.
Therefore in this step, the value in memory storage area is read, judges whether the value read is unmodified value, quilt
Modified values or other values, carry out positioning programming process.
In this step, carrying out the process of progressively power down test includes：Repeat following mistake by step-length of first time period
Journey：
S100：It is electric on card, and receive reading that the memory is sent, for reading the value in memory storage area
Instruction fetch, in the card power down after first time period；
S101：Card is upper electric again, reads the value in the memory storage area.
Further comprise step S102：Judge whether read out value is unmodified value, by modified values or other
Value, other values, which refer to, is different from unmodified value and the value by modified values.
The progressively power down test process more than, is by the period of modified values by the value in the memory storage area
And be the period of other values, it is defined as the programming time section.
Such as, power down test is carried out by 20ms of first time period, then carries out procedure below successively：
It is electric on card, receive and read card power down after instruction, 20ms.
It is electric on card, the value in storage region is read, result is obtained for unmodified value.
It is electric on card, receive and read card power down after instruction, 40ms.
It is electric on card, the value in storage region is read, result is obtained for unmodified value.
......
It is electric on card, receive and read card power down after instruction, 140ms.
It is electric on card, the value in storage region is read, result is obtained for other values.
It is electric on card, receive and read card power down after instruction, 160ms.
It is electric on card, the value in storage region is read, it is by modified values to obtain result.
The programming time section of card is obtained between 120ms-160ms.
S11：Progressively power down test is gradually carried out in programming time section, the power down time of the memory is oriented
Section, in each time positions, the power down test step-length that progressively power down test is used next time is less than last progressively power down test and adopted
Step-length is tested in power down, next time progressively power down test progressively power down is tested in oriented power down time section upper once
Carry out.
Wherein, carrying out the process of progressively power down test in the period oriented every time includes：Using preset time period as
Step-length repeats procedure below：
S110：It is electric on card, and receive reading that the memory is sent, for reading the value in memory storage area
Instruction fetch, in the card power down after preset time period.
Wherein, when carrying out in the period oriented progressively power down test every time, use corresponding preset time period for
Step-length.
S111：Card is upper electric again, reads the value in the memory storage area.
S112：Judge whether read out value is unmodified value, by modified values or other values, and other values, which refer to, to be different from
It is unmodified to be worth and by the value of modified values.
If the value read out is unmodified value, show that power down time point does not reach the programming process of the memory；If
The value read out is, by modified values, to show power down time point after the programming process of the memory；If being read out
It is worth for other values, shows that power down time point is in the programming process of the memory.
Progressively power down test is carried out in the period oriented every time by this method.
In a kind of embodiment, this step includes：
S110：Using second time period as step-length, progressively power down test is carried out in programming time section, is oriented described
Value in memory storage area is the period of other values, and other values, which refer to, is different from unmodified value and the value by modified values, institute
Second time period is stated less than the first time period.
Such as, reduce time precision, using second time period be 2ms as step-length, to the 120ms-160ms periods oriented
Scope carries out progressively power down and tested.Specific test process refers to the above method and describes process, orients programming time section and exists
Between 138ms-142ms.
S111：Using the 3rd period as step-length, the value in the memory storage area oriented is other values
Period in carry out progressively power down test, orient power down time section, the 3rd period be less than the second time period.
Such as, then reduce time precision, using the 3rd period be 500us as step-length, to orient 138ms-142ms when
Between segment limit carry out progressively power down test, same method obtain programming time section between 139ms-141ms.
Further, using the time precision of lowest level, such as using 10us as step-length, in the 139ms-141ms periods
In the range of carry out progressively power down test, orient power down time point.
As can be seen that the present embodiment memory power down time section localization method, is gradually positioned to instruction process, each
The test step long period of power down test is sequentially reduced in secondary positioning, gradually to orient power down time during memory program
Section, can realize and memory power down time section is accurately positioned.
Fig. 2 is refer to, the embodiment of the present invention also provides a kind of system power failure guard method, including step：
S20：When recognizing the system platform and power down occur, triggering power down protection starts and recorded；
S21：Legacy data is write into backup area；
S22：Write new data into target area；
S23：Power down protection is marked to complete after the completion of power down protection；
S24：Using memory power down time as described above section localization method, successively to power down protection beginning label mistake
Journey, backup legacy data process, write-in new data process, power down protection complete labeling process and carry out power down time section positioning.
As can be seen that the present embodiment system power failure guard method, when recognizing system platform and power down occur, power down is triggered
Protection starts and recorded, and legacy data is write into backup area；Then target area is write new data into, after the completion of power down protection
Power down protection is marked to complete.Power down time section is carried out successively to each process by using memory power down time section localization method
Assignment test, can realize to system during each power down time section be accurately positioned.
Further, it is new to power down protection beginning label process, backup legacy data process, write-in in the present embodiment method
Data procedures, power down protection complete labeling process and carry out power down time section positioning, are carried out before data rewind mechanism is enabled.
It is corresponding during system progress power down protection to have data rewind process.Data recovery in storage region can be made
To initial value or programming value, the advance that data rewind mechanism is enabled is positioned to the power down time section of each process in this method
OK, the data read when carrying out power down time section positioning in storage region thus are avoided that, data have been resumed, and cause can not
It is accurately positioned.
A kind of memory power down time section localization method provided by the present invention and system power failure guard method are entered above
Go and be discussed in detail.Specific case used herein is set forth to the principle and embodiment of the present invention, and the above is implemented
The explanation of example is only intended to the method and its core concept for helping to understand the present invention.It should be pointed out that for the general of the art
For logical technical staff, under the premise without departing from the principles of the invention, some improvement and modification can also be carried out to the present invention, this
A little improvement and modification are also fallen into the protection domain of the claims in the present invention.
Claims (7)
1. a kind of memory power down time section localization method, it is characterised in that including：
Using first time period as step-length, progressively power down is carried out to instruction process and tested, is oriented in the instruction process in storage
The programming time section programmed in device；
Progressively power down test is gradually carried out in programming time section, the power down time section of the memory is oriented, each
In secondary positioning, the power down test step-length that progressively power down test is used next time is less than the power down that last progressively power down test is used
Test step-length, next time progressively power down test progressively power down is tested and carried out in oriented power down time section upper once.
2. memory power down time section localization method according to claim 1, it is characterised in that described with first time period
For step-length, progressively power down is carried out to instruction process and tested, when orienting the programming programmed in memory in the instruction process
Between section include：
The value in memory storage area described in instruction process is progressively read, is by the value in the memory storage area
By the period of modified values and be the period of other values, it is defined as programming time section, other values, which refer to be different from, does not repair
Revaluate and the value by modified values.
3. memory power down time section localization method according to claim 1, it is characterised in that carry out progressively power down and test
Including：
It is electric on card, and the reading instruction for being used to read the value in memory storage area that the memory is sent is received,
The card power down after preset time period；
Card is upper electric again, reads the value in the memory storage area.
4. memory power down time section localization method according to claim 3, it is characterised in that described in described read
Also include after value in memory storage area：
Judge whether read out value is unmodified value, by modified values or other values, and other values, which refer to, is different from unmodified value
With by the value of modified values；
If the value read out is unmodified value, show that power down time point does not reach the programming process of the memory；
If the value read out is by modified values, show power down time point after the programming process of the memory；
If the value read out is other values, show that power down time point is in the programming process of the memory.
5. the memory power down time section localization method according to claim any one of 1-4, it is characterised in that it is described gradually
Progressively power down test is carried out in programming time section, orienting the power down time section of the memory includes：
Using second time period as step-length, progressively power down test is carried out in programming time section, the memory is oriented and deposits
Value in storage area domain is the period of other values, and other values, which refer to, is different from unmodified value and the value by modified values；
Using the 3rd period as step-length, the value in the memory storage area oriented is in the period of other values
Carry out progressively power down to test, orient power down time section；
The second time period is less than the first time period, and the 3rd period is less than the second time period.
6. a kind of system power failure guard method, it is characterised in that including：
When recognizing the system platform and power down occur, triggering power down protection starts and recorded；
Legacy data is write into backup area；
Write new data into target area；
Power down protection is marked to complete after the completion of power down protection；
Using the memory power down time section localization method described in claim any one of 1-5, start mark to power down protection successively
Journey, backup legacy data process, write-in new data process, the power down protection completion labeling process progress power down time section of recording a demerit are positioned.
7. system power failure guard method according to claim 6, it is characterised in that to power down protection beginning label process,
Backup legacy data process, write-in new data process, power down protection complete labeling process and carry out power down time section positioning, are returned in data
Roller system is carried out before enabling.
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| CN201710508617.8A CN107316659B (en) | 2017-06-28 | 2017-06-28 | Memory power-down time period positioning method and system power-down protection method |
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| CN201710508617.8A CN107316659B (en) | 2017-06-28 | 2017-06-28 | Memory power-down time period positioning method and system power-down protection method |
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