CN107293482B - Method for manufacturing gate electrode of gallium nitride high electron mobility transistor - Google Patents
Method for manufacturing gate electrode of gallium nitride high electron mobility transistor Download PDFInfo
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- CN107293482B CN107293482B CN201710448653.XA CN201710448653A CN107293482B CN 107293482 B CN107293482 B CN 107293482B CN 201710448653 A CN201710448653 A CN 201710448653A CN 107293482 B CN107293482 B CN 107293482B
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 14
- 239000011248 coating agent Substances 0.000 claims abstract description 9
- 238000000576 coating method Methods 0.000 claims abstract description 9
- 238000009616 inductively coupled plasma Methods 0.000 claims abstract description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 7
- 238000004544 sputter deposition Methods 0.000 claims abstract description 7
- 238000005566 electron beam evaporation Methods 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 238000001259 photo etching Methods 0.000 claims description 10
- 239000003292 glue Substances 0.000 claims description 9
- 230000037452 priming Effects 0.000 claims description 5
- 238000005406 washing Methods 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- 206010034960 Photophobia Diseases 0.000 claims description 4
- 208000013469 light sensitivity Diseases 0.000 claims description 4
- 229920000642 polymer Polymers 0.000 claims description 4
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 2
- 238000011049 filling Methods 0.000 abstract description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 abstract 1
- 229910052731 fluorine Inorganic materials 0.000 abstract 1
- 239000011737 fluorine Substances 0.000 abstract 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract 1
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 8
- 239000010931 gold Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a method for manufacturing a gate electrode of a gallium nitride high electron mobility transistor, which comprises the following steps: defining a gate line by adopting a stepping exposure machine, reducing the characteristic size of the gate line by adopting a shrinking process, etching a silicon nitride medium under an opening of the gate line by adopting fluorine-based gas in an ICP (inductively coupled plasma) cavity, removing photoresist after etching is finished, uniformly coating photoresist for exposure to obtain a gate cap line, sputtering metal W in a sputtering table after pretreatment, taking out the gate cap line, putting the gate cap line in an electron beam evaporation table for depositing Ni/Pt/Au, and finally forming a gate electrode by a stripping process. Compared with the traditional method for manufacturing the gate electrode by adopting electron beam evaporation metal, the method has the advantages that the side wall filling property of the gate metal can be effectively improved, the electric leakage of a device is reduced, and the reliability of the device is improved.
Description
Technical Field
The invention relates to the field of processing and manufacturing of compound semiconductors, in particular to a method for manufacturing a gate electrode of a gallium nitride high-electron-mobility transistor.
Background
The characteristic high electron mobility, high two-dimensional electron gas surface density and high breakdown electric field of the GaN High Electron Mobility Transistor (HEMT) enable the GaN high electron mobility transistor to have higher power output density, and the GaN high electron mobility transistor is regarded as the first choice technology of the next generation radio frequency/microwave power amplifier.
With the rapid increase of the demand of Field Effect Transistor (FET) high frequency application, the cut-off frequency f of the device is increasedTIt becomes increasingly important.
As an important parameter for representing the high-speed performance of the transistor, the cut-off frequency f of the deviceTThe approximate formula of (c) is:
wherein v issIs the saturation mobility rate of carriers, LgIs the device gate length. It can be seen that the gate length has a decisive influence on the cut-off frequency of the device.
Reducing the gate length of the device is the most direct method for improving the frequency performance, and generally, when the target gate length is less than 0.5 μm, a T-shaped gate structure is considered, which aims to reduce the gate length of the device without excessively increasing the gate resistance.
Due to the particularity of the gallium nitride device, a layer of Si is grown before the gate process3N4The medium is used for protecting the surface and inhibiting the surface state. In the subsequent gate process, a two-step photolithography method is generally used to fabricate the T-shaped gate: first step fine line photoetching for etching Si3N4Simultaneously defining the length dimension of the gate; the second step of photoetching adopts negative glue or reversal glue for defining a gate cap and forming a gate electrode through a stripping process.
The scheme mainly has the following defects: usually, the lines obtained by the first step of photolithography are very thin, and are all below 0.5 μm, and then Si with the depth of about 100nm is etched downwards3N4The medium has small line openings and certain depth, so that the conventional evaporation process is difficult to completely fill the groove with metal, and incomplete filling often causes potential reliability hazards of devices.
Disclosure of Invention
The invention mainly aims at the problem of incomplete gate metal filling in a gallium nitride high electron mobility transistor and provides a method for manufacturing a gate electrode of the gallium nitride high electron mobility transistor.
The technical scheme adopted by the invention is as follows: a method for manufacturing a gate electrode of a gallium nitride high electron mobility transistor comprises the following steps:
step 1: the surface of a GaN HEMT device after the source-drain electrode and isolation process is passivated with a layer with the thickness of
Si of (2)3N4Coating high-light-sensitivity positive glue on the medium, and baking for 90s by adopting a vacuum hot plate at 100 ℃;
step 2: exposing and developing by adopting a step-type photoetching machine to obtain fine lines with the minimum characteristic dimension of 0.4 mu m, and baking for 60-120s at the temperature of 110-;
and step 3: after the steps are completed, uniformly coating the shrinking glue on the GaN HEMT device, pre-baking for 60-90s at the temperature of 80-90 ℃, and post-baking for 60-90s at the temperature of 100-120 ℃; after the baking is finished, washing with ionized water to remove the excessive condensed rubber, continuously baking for 30-60s at the temperature of 110-120 ℃ to obtain grid-shaped strips with the width of 0.2-0.3 mu m, and baking the grid-shaped strips
The priming operation is finished at the speed of 20-30 s;
and 4, step 4: using CF in an inductively coupled plasma etcher4Etching of Si3N4The rate of priming is
The time is 20-30 s; cleaning with 10% HCl solution for 1-2min, and removing photoresist;
and 5: uniformly coating negative photoresist with the thickness of 2.0-2.5 mu m, and photoetching gate cap lines, wherein the width of the gate cap is 0.8-1.5 mu m;
step 6: depositing grid metal at the photoetching line, wherein the grid metal is W, Ni, Pt and Au from bottom to top in sequence, the W is manufactured by adopting a sputtering process, the thickness is 30-40nm, the Ni/Pt/Au is manufactured by adopting an electron beam evaporation process, and the thicknesses are respectively as follows: ni is 40-60nm thick, Pt is 40-60nm thick, Au is 400-600nm thick, and the stripping is carried out for 30-60min by using a methyl pyrrolidone solution at 90 ℃.
Preferably, the gate metal is a T-shaped gate, and the metal purity of the gate metal needs to reach 5N grade or better.
Preferably, the photoresist surface can react with the photoresist to form a polymer, and the unreacted portion can be removed by water washing to reduce the feature size of the lines.
Preferably, in the step 4, by controlling the angle of the high photo-sensitive positive photoresist and the etching bias power of the inductively coupled plasma etcher, Si can be controlled3N4The angle of the slot.
Different from the prior art, the invention has the beneficial effects that:
1. the invention adopts a sputtering mode to manufacture a layer of metal W before the gate metal is evaporated, which can obviously improve the prior art of gate metal to Si3N4Incomplete groove filling, and because the W adhesion capability is moderate, stripping is not influenced;
2. the W metal has a work function of 4.5eV, which is equivalent to 4.6V of Ni, has a large work function so as to form a high barrier with the surface of a semiconductor, and does not have a large influence on a Schottky barrier.
3. The gate metal has strong oxidation resistance, can avoid being oxidized when being switched between sputtering and evaporation equipment, has moderate adhesive force, and can avoid the situation of difficult peeling.
4. Etching of Si3N4The medium is made of high-light-sensitivity positive photoresist as a mask, and the selectivity is good due to the adoption of an ICP-RIE etching system.
Drawings
FIG. 1 is a schematic diagram of a wafer after being uniformly coated with a high photo-sensitive positive resist and exposed and developed;
FIG. 2 is a schematic structural diagram of polymer formed by the reaction of the reduced photoresist and the high-photosensitivity positive photoresist after the characteristic dimension is reduced;
FIG. 3 illustrates etching Si in an inductively coupled plasma etcher (ICP-RIE)3N4A schematic structural diagram of a device formed after the medium;
FIG. 4 is a block diagram after a negative photoresist is coated, and then photo-etched and developed;
FIG. 5 is a diagram of the structure of the device after the gate metal is sputtered, evaporated and stripped to form a gate electrode
Fig. 6 is a schematic diagram of a gate metal structure.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A method for manufacturing a gate electrode of a gallium nitride high electron mobility transistor comprises the following steps:
as shown in FIG. 1, the surface passivation thickness of a GaN HEMT device after the source-drain electrode and isolation process is completed is
Si of (2)3N4Coating high-light-sensitivity positive glue on the medium 2, and baking for 90s by adopting a vacuum hot plate at 100 ℃; then, a step-by-step photoetching machine is adopted for exposure and development, the substrate is baked for 60 to 120 seconds at the temperature of 110-130 ℃, and fine lines with the characteristic dimension of 0.4 to 0.7 mu m are obtained through development;
after the above steps are completed, as shown in FIG. 2, the shrinking glue is uniformly coated on the surface of the glass substrate, and the glass substrate is pre-baked at 80-90 ℃ for 60-90s, and then is post-baked at 100-120 ℃ for 60-90s, after the baking is completed; reacting with the surface of the photoresist at a certain temperature to generate a polymer 1, washing the unreacted part with water to remove, baking at 110-120 deg.C for 30-60s to obtain a grid-shaped strip with a width of 0.2-0.3 μm, and drying
The priming operation is carried out for 20-30s, so that the characteristic size of the lines can be reduced;
after the above steps are completed, CF is used in an inductively coupled plasma etcher (ICP-RIE)4Etching of Si3N4Medium, the etching rate is 20-30nm/min, the etching time is 5-8min, and the medium is cleaned for 1-2min by 10% HCl solution, and the photoresist is removed, so that a device structure shown in figure 3 is formed;
uniformly coating a negative photoresist with the thickness of 2-2.5 mu m, and photoetching a gate cap line with the width of 0.8-1.5 mu m to form a structure shown in figure 4;
after the above steps are completed, as shown in fig. 5, depositing a gate metal 4 at the line of the photolithography, where the gate metal 4 has a structure as shown in fig. 6, the gate metal 4 is a T-shaped gate, and the metal purity of the gate metal 4 needs to reach 5N level or better, and the gate metal 4 is, from bottom to top, in order from tungsten (W)41, nickel (Ni)42, platinum (Pt)43, and gold (Au)44, where W is manufactured by a sputtering process, the thickness of the gate metal is 30-40nm, and the Ni/Pt/Au is manufactured by an electron beam evaporation process, and the thicknesses are respectively: ni with a thickness of 40-60nm, Pt with a thickness of 40-60nm and Au with a thickness of 400-600nm, and stripping with methyl pyrrolidone solution for 30-60min to complete the device fabrication.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (4)
1. A method for manufacturing a gate electrode of a gallium nitride high electron mobility transistor comprises the following steps:
step 1: the surface of a GaN HEMT device after the source-drain electrode and isolation process is passivated with a layer with the thickness of
Si of (2)3N4Coating high-light-sensitivity positive glue on the medium, and baking for 90s by adopting a vacuum hot plate at 100 ℃;
step 2: exposing and developing by adopting a step-type photoetching machine to obtain fine lines with the minimum characteristic dimension of 0.4 mu m, and baking for 60-120s at the temperature of 110-;
and step 3: after the steps are completed, uniformly coating the shrinking glue on the GaN HEMT device, pre-baking for 60-90s at the temperature of 80-90 ℃, and post-baking for 60-90s at the temperature of 100-120 ℃; after the baking is finished, washing with ionized water to remove the excessive condensed rubber, continuously baking for 30-60s at the temperature of 110-120 ℃ to obtain grid-shaped strips with the width of 0.2-0.3 mu m, and baking the grid-shaped strips
The priming operation is finished at the speed of 20-30 s;
and 4, step 4: using CF in an inductively coupled plasma etcher4Etching of Si3N4The rate of priming is
The time is 20-30 s; cleaning with 10% HCl solution for 1-2min, and removing photoresist;
and 5: uniformly coating negative photoresist with the thickness of 2.0-2.5 mu m, and photoetching gate cap lines, wherein the width of the gate cap is 0.8-1.5 mu m;
step 6: depositing grid metal at the photoetching line, wherein the grid metal is W, Ni, Pt and Au from bottom to top in sequence, the W is manufactured by adopting a sputtering process, the thickness is 30-40nm, the Ni/Pt/Au is manufactured by adopting an electron beam evaporation process, and the thicknesses are respectively as follows: ni is 40-60nm thick, Pt is 40-60nm thick, Au is 400-600nm thick, and the stripping is carried out for 30-60min by using a methyl pyrrolidone solution at 90 ℃.
2. The method of claim 1, wherein: the grid metal is a T-shaped grid, and the metal purity of the grid metal needs to reach 5N level or better.
3. The method of claim 1, wherein: the shrinking glue can react with the surface of the photoresist to generate a polymer, and the unreacted part can be removed by water washing so as to reduce the characteristic dimension of the lines.
4. The method of claim 1, wherein: in the step 4, Si can be controlled by controlling the angle of the high light sensitive positive photoresist and the etching bias power of the inductively coupled plasma etching machine3N4The angle of the slot.
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| DE112018007766B4 (en) * | 2018-06-27 | 2024-01-25 | Mitsubishi Electric Corporation | Method of manufacturing a semiconductor device |
| CN110429028B (en) * | 2019-08-01 | 2021-11-19 | 福建省福联集成电路有限公司 | Transistor device enhancement type and depletion type grid integration manufacturing method and device |
| CN110581170A (en) * | 2019-08-13 | 2019-12-17 | 中山市华南理工大学现代产业技术研究院 | GaN-based MIS-HEMT device with Г type gate and preparation method thereof |
| CN112002641A (en) * | 2020-07-21 | 2020-11-27 | 中电科工程建设有限公司 | Method for manufacturing grid of GaN power device for 5G communication |
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| CN106783570A (en) * | 2016-12-28 | 2017-05-31 | 成都海威华芯科技有限公司 | A kind of preparation method of the T-shaped grid of HEMT |
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| US6395606B1 (en) * | 1999-07-21 | 2002-05-28 | Advanced Micro Devices, Inc. | MOSFET with metal in gate for reduced gate resistance |
| US7968453B2 (en) * | 2006-10-12 | 2011-06-28 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing display device, and etching apparatus |
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