CN107210240B - Interconnection structure is partially sealed in small―gap suture - Google Patents

Interconnection structure is partially sealed in small―gap suture Download PDF

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Publication number
CN107210240B
CN107210240B CN201680007974.XA CN201680007974A CN107210240B CN 107210240 B CN107210240 B CN 107210240B CN 201680007974 A CN201680007974 A CN 201680007974A CN 107210240 B CN107210240 B CN 107210240B
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interconnection piece
conductive
self assembly
host material
layer
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CN201680007974.XA
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CN107210240A (en
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R·坎卡尔
C·E·尤佐
A·R·西塔拉姆
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Vertical Circuits Inc
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Vertical Circuits Inc
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
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  • Multi-Conductor Connections (AREA)

Abstract

The present invention provides a kind of equipment for relating generally to microelectronic component.In such equipment, first substrate has first surface, wherein the first interconnection piece is located on the first surface, the second substrate has the second surface being spaced apart with the first surface, has gap between the first surface and the second surface.Second interconnection piece is located on the second surface.The lower surface of first interconnection piece and the upper surface of second interconnection piece are coupled to each other for the electric conductivity between the first substrate and the second substrate.Conductive liner circle surrounds the side wall of the first interconnection piece and the second interconnection piece, and dielectric layer is around the conductive lining ring.

Description

Interconnection structure is partially sealed in small―gap suture
Technical field
It is described below and is related to microelectronic component.More particularly, it is described below and is related to folding for packaging body lamination or tube core Interconnection structure is partially sealed in the small―gap suture of layer microelectronic component.
Background technique
Micromodule generally includes one or more IC, the tube core (" chip ") of such as one or more encapsulation Or one or more tube cores.One or more such IC may be mounted in circuit platform, such as be installed on wafer such as brilliant Circle grade encapsulates (" WLP "), printing plate (" PB "), printed wiring board (" PWB "), printed circuit board (" PCB "), printed wiring component In (" PWA "), printed circuit assembly (" PCA "), package substrate, inserter or chip carrier.In addition, an IC may be mounted at On another IC.Inserter can be IC, and inserter can be passive or active IC, and the latter one include one or more Active device, such as transistor, and the former does not include any active device.Furthermore, it is possible to the inserter as PWB is formed, I.e. no any circuit element such as capacitor, resistor or active device.In addition, inserter includes at least one through substrate Through-hole.
IC may include conducting element, such as the conducting element that can be used for being electrically interconnected with circuit platform, such as road, mark Line, track, through-hole, contact, pad (such as contact pad and landing pad), plug, node or terminal.These arrangements can promote Into for providing the electrical connection of IC function.IC can be for example, by engaging the engagement trace or terminal of this circuit platform to IC Pin or column etc. landing pad or exposed ends and with circuit platform couple.In addition, redistributing layer (" RDL ") can be IC's A part, to be conducive to the landing pad position that such as flip-chip configuration, chip stack or be more convenient or can contact.
Conventionally IC and another IC or circuit platform are interconnected, it can be in the small―gap suture with underfill layer completely Problem is brought in terms of coating interconnection structure.Incomplete protective coating may cause integrity problem, such as may with it is such mutually The corrosion for linking the exposed surface of structure is associated.
Therefore, in small―gap suture provide interconnection structure protective coating will be expectation and it is useful.
Summary of the invention
A kind of equipment relates generally to microelectronic component.In such equipment, first substrate has first surface, wherein first Interconnection piece is located on first surface, and the second substrate has the second surface being spaced apart with first surface, wherein first surface There is gap between second surface.Second interconnection piece is located on second surface.The lower surface of first interconnection piece and the second interconnection The upper surface of part is coupled to each other for the electric conductivity between first substrate and the second substrate.Conductive liner circle surrounds the first interconnection piece With the side wall of the second interconnection piece, and dielectric layer surrounds conductive lining ring.
A kind of method relates generally to form microelectronic component.The first self assembly base of the first conductive particle will be wherein suspended with The first layer of material is applied on the first side wall and lower surface of the first interconnection piece.First interconnection piece is located at the of first substrate On one surface.The second layer for being wherein suspended with the second self assembly host material of the second conductive particle is applied to the second interconnection piece Second sidewall and upper surface on.Second interconnection piece is located on the second surface of the second substrate.Remove first layer a part with The temporarily lower surface of the first interconnection piece of exposure.A part of the second layer is removed temporarily to expose the upper surface of the second interconnection piece.It will First conductive particle and the first self assembly host material PHASE SEPARATION, and by the second conductive particle and the second self assembly matrix material PHASE SEPARATION is expected, for providing the conductive lining ring for surrounding the side wall of the first interconnection piece and the second interconnection piece, and around conductive liner The dielectric layer of circle.The first interconnection piece and the second interconnection piece, second surface of diffusion bonding each other are spaced apart with first surface, There is about 5 microns or smaller gap therebetween.
Another method relates generally to form microelectronic component.In this approach, first conductive will be wherein suspended with The first layer of first self assembly host material of grain is applied on the first side wall and lower surface of the first interconnection piece.First interconnection piece On the first surface of first substrate.The second layer of the second self assembly host material of the second conductive particle will be wherein suspended with It is applied in the second sidewall and upper surface of the second interconnection piece.Second interconnection piece is located on the second surface of the second substrate.Will under The second layer on first layer and upper surface on surface is close to each other or contacts.By the first conductive particle and the first self assembly matrix Material carries out PHASE SEPARATION, and the second conductive particle and the second self assembly host material are carried out PHASE SEPARATION, for providing Around the conductive lining ring of the side wall of the first interconnection piece and the second interconnection piece, the lower surface positioned at the first interconnection piece and the second interconnection piece Upper surface between bonding layer and dielectric layer around conductive lining ring.For the first interconnection piece engaged between metal each other and Two interconnection pieces, second surface are spaced apart with first surface, have about 5 microns or smaller gap therebetween.
It is recognized that other features after considering following specific embodiments and claims.
Detailed description of the invention
Attached drawing shows the exemplary embodiment of the one or more aspects according to example devices or method.But it is attached The range that figure should not be used to limit the claims, is only used for explanation and understanding.
Fig. 1 is to depict the block diagram of the side view of exemplary conventional microelectronic device.
Fig. 2 to Fig. 5 is to depict the respective block diagram of the cross-sectional side view of exemplary microelectronic device.
Fig. 6-1 and Fig. 6-2 be depict the microelectronic component for being used to form Fig. 2 to Fig. 5 exemplary process flow it is mixed Close flow diagram.
Fig. 6-3 and Fig. 6-1 is to depict another the exemplary work for being used to form the microelectronic component of Fig. 2 to Fig. 5 together The mixture length block diagram of skill process.
Fig. 7 is the cross-sectional view of the A1-A2 of the conductive structure along Fig. 6-2 or Fig. 6-3.
Fig. 8-1 and Fig. 8-2 is to depict another illustrative processes stream for being used to form the microelectronic component of Fig. 2 to Fig. 5 The mixture length block diagram of journey.
Specific embodiment
Numerous specific details are set forth in the following description, to provide more comprehensively retouching to specific example described herein It states.However, for those skilled in the art it should be apparent that can be in the feelings of all details provided of having no reply Under condition, other one or more examples or these exemplary variations are practiced.In other cases, many institute's weeks are not described in detail The feature known, in order to avoid description exemplified here is made to become obscure.For ease of description, identical number is used in various figures Label refers to identical project；However, project can be different in alternative example.
Fig. 1 is to depict the block diagram of the side view of exemplary conventional microelectronic device 10.Microelectronic component 10 includes first Substrate 20 and the second substrate 30.Substrate 20 can have the back side or front side surface (" upper surface ") 21, and substrate 30 can have There are the back side or front side surface (" lower surface ") 31.
Such orientation specified up and down for illustrative description for surface 21 and 31.According to these modes, Such specify up and down as used herein is in order to clearly referring to the orientation of illustrative description；However, will be shown from being described below And be clear to, reversed, side or other orientations can be used.
Surface 21 and 31 can be with facing each other, and limits gap 11 between the surfaces.The gap 11 is smaller, i.e. gap 11 height is typically about 5 microns or smaller.
Interconnection piece 50 can be located on upper surface 21, and interconnection piece 40 can be located on lower surface 31.Interconnection piece is set to exist Surface "upper" is intended to include directly contacting and/or mediate contact, the latter one may include interconnection piece and phase with this surface Close one or more middle layers between surface.
Substrate 20 and 30 can be individual circuit platform, may include such as brilliant with the corresponding semiconductor in lower substrate Circle: wafer-level packaging (" WLP "), integrated circuit die, inserter tube core (" inserter "), printing plate (" PB "), printed circuit Plate (" PWB "), printed circuit board (" PCB "), printed wiring component (" PWA ")/printed circuit assembly (" PCA "), package substrate, The substrate of chip carrier and/or other forms.However, substrate 20 and 30 is generally used for forming die stacks or packaging body is folded Layer microelectronic component 10.
Equally, surface 21 and 31 can be separated from each other, and have about 5 microns or smaller gap between the surfaces 11.In some cases, such gap 11 can be about 2 microns or smaller.In other cases, such gap 11 can be situated between Between about 5 microns to 20 microns.
For routine, the "lower" surface 51 of interconnection piece 50 and the "upper" surface 41 of interconnection piece 40 are coupled to each other, this includes straight It connects coupling or is coupled indirectly, for the electric conductivity between substrate 20 and 30.For the sake of clarity rather than limitation purpose, up and down Specified is for associated interconnection piece surface, rather than for the overall orientation of microelectronic component 10.
The surface region of upper surface 41 can optionally be greater than the surface region of respective lower 51.Further, optionally, under The surface region on surface 51 can be substantially placed in the middle for the correspondence surface region of upper surface 41.According to these sides Formula, due to design tolerance and/or technique change, this surface region may not be placed in the middle relative to each other, but can each other partially Move about 10 microns or less.In embodiments, optionally, the peripheral portion 43 of upper surface 41 can not connect with lower surface 51 Touching, although lower surface 51 can above such peripheral portion 43 not right above it.Even if the diameter or width of interconnection piece 50 Degree is shown schematically as the diameter or width less than interconnection piece 40, but in other embodiments, such diameter or width It can be the diameter or width that identical or interconnection piece 50 diameter or width can be greater than interconnection piece 40.
Interconnection piece 40 and 50 may include one or more conductive materials, such as one or more metallic conductors.By In environmental condition, one of these materials or a variety of corrosion, oxidation and/or such electric conductivity and/or reliability can suffer from Other forms deterioration.Interconnection piece 40 and 50 can be any one of (" the UBM ") structure that metallizes under various salient points, packet Include soldered ball restriction pad (i.e. shallowly dished structure), electrically-conductive backing plate pad, raised pads, recess pad and/or their combination.It is various types of Interconnection piece such as copper, aluminium, gold, silver, indium, gallium, nickel, tungsten, its respective alloy, their combination and/or other UBM structures, It can be used for interconnection piece 40 and 50.For the sake of clarity, by way of example rather than limitation, it will be assumed that interconnection piece 40 and 50 is Copper-copper engagement is respectively used to form substrate-substrate conducting structure 60 copper UBM structure.
The direct engaged conductive structure 60 of these copper-copper can produce height gap 11 that is short and swelling, such as about 1.8 microns high of gap 11.However, gap 11 narrow can be used to sufficiently be passivated to prevention and/or package interconnections 40 and 50 Underfill layer 70 injection.
According to these modes, underfill layer 70 may not provide in some cases for gas-tight seal copper-copper engagement Sufficient cavity sealing ring, this can reduce the reliability of microelectronic component 10.For example, after injecting underfill layer, interconnection A part of the side wall 52 of a part and/or interconnection piece 50 of the side wall 42 of part 40 can be exposed to environmental corrosion object.In addition, infusing After entering underfill layer 70, the part not overlapped each other on surface 41 and 51 can be exposed to environmental corrosion object.However, even if note The underfill layer 70 entered is airtightly sealed really outside the chamber around the conductive structure 60 formed by interconnection piece 40 and 50 Shell, such sealing ring can also capture such intracavitary moisture, air and/or other erosions, this can lead to integrity problem.
Fig. 2 to Fig. 5 is to depict the respective block diagram of the cross-sectional side view of exemplary microelectronic device 100.In Fig. 2 to figure In 5 each microelectronic component 100, there is lining around the respective side wall 42 and 52 of interconnection piece 40 and 50 of conductive structure 160 Circle 102, and there are dielectric layers 101, such as resin layer 101 around the lining ring of conductive structure 160 102.Conductive structure 160 can To be separated from each other, that is, have spacing 161, can greater than, equal to or less than gap 11 width.Due to the microelectronics of Fig. 1 There are some identical elements between device 10 and microelectronic component 100, thus for the sake of clarity rather than limitation purpose, greatly These similar elements of not repeated description on body.
Referring to fig. 2, lining ring 102 can adhere to interconnection piece 40 and 50.More particularly, lining ring 102 can adhere to mutually The even side wall of part 40 and 50 or sidewall surfaces 42 and 52 and peripheral portion 43.Optionally, lining ring 102 can be tied along with conduction The associated surface 21 and 31 of structure 160 and adhere to other conductive surface components (for the sake of clarity rather than the purpose of limitation and It is not shown).
Resin layer 101 can adhere in the outer side wall surface 106 of each lining ring 102 matched with resin layer 101.Resin Layer 101 optionally can adhere to surface elements (in order to clearly rise along surface 21 and 31 associated with conductive structure 160 See rather than the purpose that limits and be not shown), and/or adhere to surface 21 and 31.The adherency of resin layer 101 can be used for gas Corresponding lining ring 102 is sealed, and the interconnection piece of conductive structure 160 40 and 50 is hermetically sealed between surface 21 and 31.
Therefore, not providing has the conventional hermetic chamber of underfill layer 70 (although this routine can be added optionally Seal chamber), but using the mode for directly contacting corresponding resin layer 101 with corresponding lining ring 102, airtightly sealing is each led Electric structure 160.It can thus be avoided occurring capturing showing for moisture, air and/or other erosions as conventional hermetic chamber As.
Even if being optionally used together conventional hermetic chamber with microelectronic component 100, each conductive structure 160 can also have There is the independence provided by corresponding resin layer 101 gas-tight seal.Therefore, the entirety of the conductive structure 160 of microelectronic component 100 is airtight The available promotion of property.This can reduce a possibility that corroding and increase reliability.
Lining ring 102 may include compound (" IMC ") between low-temperature metal.The example for the low temperature IMC that can be used includes Cu- Sn, Pb-Sn and Cu-Al-Ni etc.." low temperature " IMC is referred generally to, (such as usually big at temperature relevant to solder joint is provided At about 260 degrees Celsius or lower temperature) IMC of flowing or reflux.Therefore, for such reflux, it can be used and generally compare IMC Liquidus temperature be higher by most about 40 degrees Celsius of temperature.
Lining ring 102 can contribute to maintain the electrical conductance between associated multipair interconnection piece 40 and 50, this is because lining Such IMC of circle 102 can be formed on the side wall 42 and 52 of this interconnection piece, and can optionally be formed in interconnection piece 50 Upper surface 51 outer peripheral portion 43 on.Outer peripheral portion 43 can extend entirely around the side wall 52 of intersection, and therefore lining ring 102 can extend further around the outer peripheral portion 43 of the upper surface 51 of interconnection piece 50.
The microelectronic component 100 of Fig. 2 and Fig. 3 can be it is identical, the difference is that in the microelectronic component 100 of Fig. 3 In, diffusion bonding layer 103 can be formed between the interconnection piece 40 and 50 for conductive structure 160.The lower surface of interconnection piece 50 51 and the upper surface 41 of interconnection piece 40 can be coupled to each other, so as to conductive with diffusion bonding layer 103.In this embodiment, mutually Even part 40 and 50, which can substantially show, is an integral structure.
The microelectronic component 100 of Fig. 3 and Fig. 4 can be it is identical, the difference is that in the microelectronic component 100 of Fig. 4 In, diffusion barrier layer 116 can be formed.
Referring to fig. 4, lining ring 102 can contribute to maintain the electrical conductance between associated multipair interconnection piece 40 and 50, this Be due to lining ring 102 metal or metallic compound can around this interconnection piece the flowing of side wall 42 and 52/flow back and be attached to The side wall, and optionally may be on the outer peripheral portion 43 of upper surface 51 of interconnection piece 50.However, this metalloid can be with It is the material of any one of interconnection piece 40 and 50 or both or the diffuser of component, diffusion can change conductive structure 160 resistivity.
In order to mitigate the case where metal of lining ring 102 is diffused into any one of interconnection piece 40 and 50 or both, Ke Yiyan The side wall 42 and 52 of conductive structure 160 and the formation diffusion barrier layer 116 on peripheral portion 43.Generally, diffusion barrier layer 116 can mitigate diffusion between interconnection piece 40 and 50 and lining ring 102.For example, lasso 102 can be mainly Sn, and And the diffusion barrier layer 116 of predominantly Ni can be formed.In other embodiments, this or another metal can be used mainly In lining ring 102, and this or another material is mainly useful diffusion barrier layer 116." main " refers generally at least 50%.
The microelectronic component 100 of Fig. 3 and Fig. 5 can be it is identical, the difference is that in the microelectronic component 100 of Fig. 5 In, the diffusion bonding layer 103 in Fig. 3 is substituted by intermetallic compounds layer 104.
Referring to Fig. 5, lining ring 102 can contribute to maintain the electrical conductance between associated multipair interconnection piece 40 and 50, this Be due to lining ring 102 metal or metallic compound can around this interconnection piece the flowing of side wall 42 and 52/flow back and be attached to The side wall, and optionally may be on the outer peripheral portion 43 of upper surface 51 of interconnection piece 50.In addition, forming lining ring It, can there is a situation where form corresponding intermetallic compounds layer 104 during 102.
Intermetallic compounds layer 104 can be formed between the lower surface 51 of interconnection piece 50 and 40 and upper surface 41.Metal Between compound layer 104 can be formed by material identical with lining ring 102.According to these modes, intermetallic compounds layer 104 and corresponding Lining ring 102 can be integral structure.Intermetallic compounds layer 104 can be by the lower surface 51 of interconnection piece 50 and 40 and opposite Upper surface 41 be coupled to each other for the electric conductivity between substrate 20 and 30.
Fig. 6-1 and Fig. 6-2 is the exemplary process flow 140 for describing the microelectronic component 100 for being used to form Fig. 2 to Fig. 5 Mixture length block diagram.With reference to Fig. 1 to Fig. 6-2, process flow 140 is further described.Process flow 140 can be used for Justify 120 and the wafer-level packaging carried out in combinations circle 130 including substrate 30 in combinations using including substrate 20 (“WLP”)。
As described herein, these wafers 120 and 130 can be coupled to each other, to obtain packaging body lamination (" POP ") microelectronics Device 100.Between the encapsulation of such POP microelectronic component 100, as described herein, can be used be located at it is such in combinations Established interconnection piece 50 and 40 on the substrate 20 and 30 of circle 120 and 130, to form hermetically sealed interconnection conductive structures 160。
At 141, it will can wherein be suspended with the first layer of the first self assembly host material 125 of the first conductive particle 122 121 are applied on the first side wall 52 and "lower" surface 51 of the first interconnection piece 50.At 142, it will can wherein be suspended with second and lead The second layer 131 of second self assembly host material 135 of electric particle 132 is applied to 42 He of second sidewall of the second interconnection piece 40 On "upper" surface 41.
Self assembly host material 125 and 135 can be same or different, such as identical with these materials or not Same chemical composition.The example of self assembly host material 125 and 135 includes solder joint encapsulation adhesives, such as SMT256 or SMT266 or other suitable materials.
Conductive particle 122 and 132 can be the identical or different mixture of identical or different type conductive particle.It is this Conductive particle 122 and/or 132 may include the nano particle for self assembly.It is, for example, possible to use Sn particle and Cu, Ni and/ Or the combination of In nano particle or alloy.Generally, In particle can be used for being formed as a part of IMC at low temperature and securely connect It closes, and obtained IMC can have high-melting-point.For the sake of clarity, by way of example rather than limitation, it will be assumed that formed CuSn IMC, especially Cu3Sn IMC, although in other embodiments, can also be formed including the other kinds of of PbSn IMC。
At 143, the top of first layer 121 can be removed temporarily to expose the lower surface 51 of the first interconnection piece 50.144 Place can remove the top of the second layer 131 temporarily to expose the upper surface 41 of the second interconnection piece 40.At 143 and 144, removal Such top can be by executing to operating 133 in 120 and 130 progress respective planesization of combinations circle.In this embodiment In, self assembly host material 125 and 135 can be restricted to the side wall 42 of interconnection piece 40 and 50 by this planarization or polishing operation With 52, for the sake of clarity rather than the purpose of limitation, it is assumed that interconnection piece is Cu salient point.However, the interconnection structure of other forms and/ Or other materials can also be used for interconnection piece 40 and 50.
In other embodiments, outer layer 121 and 131 can be made of chemical deposition or electrolytic deposition material layer. In one example, copper post (such as interconnection piece 40 and 50) can be coated with one layer of nickel or nickel alloy, and such nickel or nickel close Gold can be coated with tin or indium or its alloy.It can be for example by using planarization or other polishing technologies, coming before assembly Remove unwanted material at the top of interconnection piece 40 and 50.
At 145, the upper surface 41 of the lower surface 51 of the first interconnection piece 50 and the second interconnection piece 40 can optionally each other Diffusion bonding is for making the electric conductivity between substrate 20 and substrate 30.The diffusion bonding can be in the respective table on surface 41 and 51 Optional diffusion bond layer 103 is formed between the region of face.Such diffusion bonding is such as used for the diffusion of Cu-Cu in this example Engagement, can carry out at low temperature, i.e., the reflux temperature lower than Sn at a temperature of carry out, and this diffusion bonding can be It is carried out before PHASE SEPARATION at 146.
At 146, the first conductive particle 122 and the first self assembly host material 125 can be subjected to PHASE SEPARATION, and can Second conductive particle 132 and the second self assembly host material 135 are subjected to PHASE SEPARATION.Self assembly host material 125 and 135 Lining ring 102 and resin layer 101 can be obtained in such PHASE SEPARATION.According to these modes, the first interconnection piece 40 and second can be surrounded The side wall 42 and 52 of interconnection piece 50 is outwardly formed lining ring 102, and can form resin layer 101 around lining ring 102.
PHASE SEPARATION at 146 may include the heating operation at 147, and by heating such self assembly host material Self assembly or autoregistration operation at 148 and 149 caused by 125 and 135.At 147, to the first self assembly host material 125 and second self assembly host material 135 carry out heating can be formed with IMC (be in this example the lining of such as Cu3Sn) Circle 102, wherein lining ring 102 includes 122 He of the first conductive particle from the first self assembly host material 125 in such IMC The second conductive particle 132 from the second self assembly host material 135.At 148, such IMC of lining ring 102 can be adhered to The side wall 42 and 52 of interconnection piece 40 and 50 and the peripheral portion 43 of upper surface 41.It generally, can be in this side wall 42 and 52 It is upper to form thin and stable IMC layers of Cu-Sn, to obtain lining ring 102.In addition, lining ring 102 may include in 40 He of interconnection piece Such IMC is formed between 50.According to these modes, a part of copper of diffusion bonding layer 103 can be disappeared when forming such IMC Consumption.In addition, a part of copper associated with peripheral portion 43 can be consumed when forming such IMC.In embodiments, herein When class forms Cu3Sn IMC lining ring 102, all Sn can be consumed.However, can generally be formed for lining ring 102 Cu3Sn IMC, wherein Cu3SnIMC is attached to side wall 42 and 52 and for example extends outwardly away from side wall radially outward.
At 149, the formation of lining ring 102 can promote the PHASE SEPARATION or fractional condensation of autoregistration or self assembly.At 149, The polymerization of the polymer and the second self assembly host material 135 of the first self assembly host material 125 for levitated conductive particle Object can be segregated with lining ring 102, such as formation IMC ring 102.In fact, when lining ring 102 adheres to side wall 42 and 52 and is formed as When IMC, the polymer of self assembly host material 125 and 135 is pushed outwards from lining ring 102.These polymer can combine to be formed 3D polymer mesh, to obtain the resin layer 101 around lining ring 102 to the periphery.
Resin layer 101 can also adhere to the surface of substrate 20 and 30, other than adhering to lining ring 102 with airtightly Seal conductive structure 160.Therefore, because the surface of substrate 20 and 30 because conductive structure 160 there are due to can be separated from each other About 5 microns of gap, thus resin layer 101 can for conductive structure 160 provide it is gas-tight seal, without apply underfilling Layer.
In conjunction with Fig. 6-1, Fig. 6-3 be depict be used to form the microelectronic component 100 of Fig. 2 to Fig. 5 another is exemplary The mixture length block diagram of process flow 140.With reference to Fig. 1 to Fig. 6-3, another such process flow 140 is further described. Equally, process flow 140 be used for include substrate 20 combinations circle 120 and including substrate 30 combinations circle 130 And carry out WLP.
Because most of explanation of the process flow 140 of Fig. 6-1 and Fig. 6-2 all with the process flow of Fig. 6-1 and Fig. 6-3 140 be identical, thus for the sake of clarity rather than limitation purpose, generally only difference is described.According to these sides Formula, operation 141 to 145 is as described above, therefore does not repeat its description.However, in the process flow 140 of Fig. 6-3, PHASE SEPARATION at 156 includes forming barrier layer 116.Such barrier layer 116 can be relative to the one or more of lining ring 102 The diffusion barrier layer 116 of material.
At 156, the first conductive particle 122 and the first self assembly host material 125 can be subjected to PHASE SEPARATION, and can Second conductive particle 132 and the second self assembly host material 135 are subjected to PHASE SEPARATION.Self assembly host material 125 and 135 This PHASE SEPARATION can form barrier layer 116, lining ring 102 and resin layer 101.According to these modes, barrier layer 116 can be The outside of the side wall 42 and 52 of one interconnection piece 40 and the second interconnection piece 50 is formed.Lining ring 102 can surround barrier layer 116 to shape At, and resin layer 101 can be outwardly formed around lining ring 102.
PHASE SEPARATION at 156 may include the heating operation at 157, and by heating this self assembly host material Self assembly or autoregistration operation caused by 125 and 135 at 158-1,158-2 and 159.At 157, to the first self assembly base Material 125 and the second self assembly host material 135, which carry out heating, can form barrier layer 116 and lining ring 102.In this example, Barrier layer 116 can be the barrier layer Ni；However, in other embodiments, other materials can also be used for barrier layer 116, including Such as copper alloy, nickel alloy, cobalt and cobalt alloy, Ti, Ta, Pd, TiN, TaN, tungsten and tungsten alloy.
The formation on barrier layer 116 can substantially limit to form any lining ring 102 as IMC, in such as aforementioned exemplary Cu3Sn.On the contrary, in this example, the first conductive particle 122 from the first self assembly host material 125 and from second from The second conductive particle 132 for assembling host material 135 may include Ni and Sn.Therefore, generally Ni conductive particle can be formed Barrier layer 116, and Sn conductive particle can form ring 102, this is because can generally prevent Sn from passing through diffusion barrier layer 116 form IMC with the Cu from interconnection piece 40 and 50.
At 158-1, such diffusion barrier layer 116 can adhere to the side wall 42 and 52 and upper table of interconnection piece 40 and 50 The peripheral portion 43 in face 41.Generally, in this example, Ni thin layer can be formed on this side wall 42 and 52, to obtain Diffusion barrier layer 116.
At 158-2, lining ring 102 can adhere to the side surface on barrier layer 116 with autoregistration.Generally, in the example In, at 158-2, it can be outwardly formed Sn on the side surface on barrier layer 116, to provide lining ring around barrier layer 116 102.According to these modes, a part of copper of interconnection piece 40 and 50 can be consumed before forming barrier layer 116 completely.Optionally Ground, the conductive particle of suspension can be used for being formed barrier layer, and form IMC.In addition, one associated with peripheral portion 43 Divide copper that can be consumed when forming this IMC.
In embodiments, lining ring 102 is substantially formed by Sn, and wherein Sn is adhered to the side surface on barrier layer 116 and all It such as extends radially out far from the side surface.The autoregistration on the barrier layer 116 at 158-1 or self assembling type PHASE SEPARATION are divided It is solidifying, it can equally promote the autoregistration of lining ring 102 or self assembling type PHASE SEPARATION or fractional condensation at 158-2.
Similarly, in outside downstream effect, the autoregistration or self assembling type PHASE SEPARATION of the lining ring 102 at 158-2 Or fractional condensation is formed, and autoregistration at 159 or self assembling type PHASE SEPARATION or fractional condensation can be promoted.At 159, it to be used for levitated conductive The polymer of first self assembly host material 125 of particle and the polymer of the second self assembly host material 135 can segregate simultaneously Form lining ring 102.Effectively, when lasso 102 adheres on barrier layer 116, the polymerization of self assembly host material 125 and 135 Object is pushed outwards from lining ring 102.These polymer can combine to form 3D polymer mesh, to obtain to the periphery around lining ring 102 resin layer 101.
Equally, resin layer 101 can also adhere to the surface of substrate 20 and 30, other than adhering to lining ring 102 with gas Thickly seal conductive structure 160.Therefore, because the surface of substrate 20 and 30 because conductive structure 160 there are due to can be to each other Separate such as about 5.0 microns of gap, thus resin layer 101 can for conductive structure 160 provide it is gas-tight seal, without applying Add underfill layer.
Fig. 7 is the cross-sectional view of the A1-A2 of the conductive structure 160 along Fig. 6-2 or Fig. 6-3.Overlook substrate 30, interconnection piece 40 A part of upper surface can be associated with the respective surfaces region of interconnection piece 50, as shown in dotted line rounded square.Although figure In schematically show rounded square, but the shape or another shape, such as square can be used in interconnection piece 40 and/or 50 Shape, circle and/or ellipse etc..
Barrier layer 116 is optionally disposed in the side wall perimeter periphery of interconnection piece 40.Lining ring 102 can be located at the side wall of interconnection piece 40 Or optional 116 perimeter of barrier layer.Finally, resin layer 101 can be located at the side wall perimeter periphery of lining ring 102, to provide gas Sealing.It will be appreciated that though needs are gas-tight seal, but it is this it is gas-tight seal be not that can realize in each case. However, even if carrying out part sealing using resin layer 101 can also be improved reliability.In some embodiments, it seals or sets Rouge layer 101 may include the conductive material with corrosion-resistant surface.
Fig. 8-1 and Fig. 8-2 is another illustrative processes stream for describing the microelectronic component 100 for being used to form Fig. 2 to Fig. 5 The mixture length figure of journey 140.With reference to Fig. 1 to Fig. 8-2, another such process flow 140 is further described.Equally, work Skill process 140 is used for including carrying out in combinations circle 120 and including substrate 30 in combinations circle 130 for substrate 20 WLP。
Because most of explanation of the process flow 140 of Fig. 8-1 and Fig. 8-2 all with the process flow of Fig. 6-1 and Fig. 6-2 140 be identical, thus for the sake of clarity rather than limitation purpose, generally only difference is described.According to these sides Formula, operation 141 and 142 is as described above, therefore does not repeat its description.However, in the technique stream of Fig. 8-1 and Fig. 8-2 In journey 140, operation 143 and 144 is not executed, thus the surface 41 and 51 of interconnection piece 40 and 50 has been covered each by layer 131 and 121.
At 181, by the surface of the second layer 131 on the surface and upper surface 41 of the first layer 121 on lower surface 51 that This comes close to or in contact with.
182, the first conductive particle 122 and the first self assembly host material 125 can carry out to PHASE SEPARATION, and by the Two conductive particles 132 and the second self assembly host material 135 carry out PHASE SEPARATION, to provide around the first interconnection piece and second mutually The even upper surface 41 of the lining ring 102 of side wall 42 and 52 of part and the lower surface 51 of the first interconnection piece 50 and the second interconnection piece 40 Between bonding layer 104.Such PHASE SEPARATION at 182 can also be used to provide resin layer 101 around lining ring 102, as before It is described.
PHASE SEPARATION at 182 may include the heating operation at the pressing operation and 184 at 183, and as described above It is operated by caused by this self assembly host material 125 and 135 of heating 148 and 149 self assembly or autoregistration.183 Place, can be pressed into the second layer for the surface area portion associated with the lower surface 51 of the first interconnection piece 50 in first layer 121 On surface area portion associated with the upper surface 41 of the second interconnection piece 40 in 131.This pressing operation can effectively compel Squeeze out some materials of layer 121 and 131 between surface 41 and 51.
At 184, heating to the first self assembly host material 125 and the second self assembly host material 135 can be with shape It (is in this example the lining ring 102 of such as Cu3Sn), wherein lining ring 102 includes coming from first in such IMC at IMC The first part of first conductive particle 122 of self assembly host material 125 and from the second self assembly host material 135 second The first part of conductive particle 132.This heating at 184 can be the operation after reflux, wherein coming from the first self assembly base Effective solder of material 125 and the second self assembly host material 135 makes surface 41,42,51,52 and 43 optional wettings.
In addition, heating to the first self assembly host material 125 and the second self assembly host material 135 can at 184 The bonding layer 104 with such IMC is formed, which includes the first conductive particle from the first self assembly host material 125 The second part of 122 second part and the second conductive particle 132 from the second self assembly host material 135.In the implementation In mode, due to not formed optional Cu-Cu diffusion bonding layer as described above, can be formed at the top on surface 41 has The backflow fittings of thin Sn lid 117, wherein generally all remaining Sn are consumed to form Cu3Sn IMC lining ring 102.
At 148, such IMC of lining ring 102 can adhere to side wall 42 and 52 and the upper surface of interconnection piece 40 and 50 41 peripheral portion 43.Generally, IMC layers of thin and stable Cu-Sn can be formed on this side wall 42 and 52, thus To lining ring 102.In addition, lining ring 102 may include forming such IMC between interconnection piece 40 and 50.According to these modes, diffusion A part of copper of bonding layer 103 can be consumed when forming such IMC.In addition, a part of copper associated with peripheral portion 43 It can be consumed when forming such IMC.In embodiments, when forming Cu3Sn IMC lining ring 102 in this way, all Sn It is consumed.However, can generally form Cu3Sn IMC for lining ring 102, wherein Cu3Sn IMC is attached to side wall 42 and 52 And such as side wall is extended outwardly away from radially outward.
In addition, resin layer 101 other than adhering to lining ring 102, can also adhere on the surface of substrate 20 and 30, with Packaging conductive structure 160, so that the corrodible component for this conductive structure 160 provides protective layer.Therefore, because 20 He of substrate 30 surface because conductive structure 160 there are due to can be separated from each other about 5 microns of gap, so resin layer 101 can be with There is provided for conductive structure 160 it is gas-tight seal, without apply underfill layer.In some embodiments, substrate 20 and 30 It is at least two adjacent conductive structures 160 for including interconnection piece 40 and 50 and being formed that gap between surface, which can be equal to or less than, Between spacing.In some other embodiment, this gap between such substrate 20 and 30 surface can be equal to or Greater than for including interconnection piece 40 and 50 and formed at least two adjacent conductive structures 160 between spacing.
Although foregoing describe one or more exemplary implementation schemes of one or more aspects according to the present invention, It is that can design in the case where not departing from the scope of the invention determined by following the claims and equivalent according to this hair Other and other embodiments of bright one or more aspects.Claim listings step is not meant to that any step is suitable Sequence.Trade mark is that its owner owns respectively.

Claims (20)

1. a kind of microelectronic component, comprising:
First substrate, the first substrate have first surface；
First interconnection piece, first interconnection piece are located on the first surface；
The second substrate, the second substrate has the second surface being spaced apart with the first surface, wherein in first table There is gap between face and the second surface；
Second interconnection piece, second interconnection piece are located on the second surface；
The upper surface of the lower surface of first interconnection piece and second interconnection piece, the lower surface of first interconnection piece and institute The upper surface for stating the second interconnection piece is coupled to each other for the electric conductivity between the first substrate and the second substrate；
Conductive lining ring, the conductive liner circle surround the side wall of first interconnection piece and second interconnection piece, the conductive liner Circle has the conductive material from self assembly host material；With
Dielectric layer, the dielectric layer is around the conductive lining ring.
2. microelectronic component according to claim 1, in which:
First interconnection piece and second interconnection piece respectively include metallization structure；And
The gap is 5 microns or smaller.
3. microelectronic component according to claim 1, in which:
First interconnection piece and second interconnection piece respectively include metallization structure；And
The gap is equal to or less than with first interconnection piece and second interconnection corresponding with first interconnection piece Spacing between at least two adjacent conductive structures of part, first interconnection piece and second interconnection piece be coupled to each other with Electric conductivity between the first substrate and the second substrate.
4. microelectronic component according to claim 1, in which:
First interconnection piece and second interconnection piece respectively include metallization structure；And
The gap is equal to or more than with first interconnection piece and second interconnection corresponding with first interconnection piece Spacing between at least two adjacent conductive structures of part, first interconnection piece and second interconnection piece be coupled to each other with The electric conductivity between the first substrate and the second substrate.
5. microelectronic component according to claim 1, wherein the dielectric layer adheres to the first surface, described second Surface and the conductive lining ring are for airtightly sealing the conductive liner between the first surface and the second surface Circle, first interconnection piece and second interconnection piece；And
The dielectric layer has the polymer mesh of the polymer from the self assembly host material.
6. microelectronic component according to claim 1, further includes:
Diffusion bonding layer, the diffusion bonding layer is between first interconnection piece and second interconnection piece；
Wherein the lower surface of first interconnection piece and the upper surface of second interconnection piece are viscous by the diffusion Layer is closed to be coupled to each other for electric conductivity.
7. microelectronic component according to claim 1, further includes:
Intermetallic compounds layer, the intermetallic compounds layer is between first interconnection piece and second interconnection piece；
The lower surface of first interconnection piece and the upper surface of second interconnection piece utilize the intermetallic Nitride layer is coupled to each other for electric conductivity.
8. microelectronic component according to claim 1, wherein the conductive liner circle includes intermetallic compound.
9. microelectronic component according to claim 7, wherein the intermetallic compound of the conductive liner circle surrounds institute State the side wall of the first interconnection piece and second interconnection piece.
10. microelectronic component according to claim 1 further includes being located at first interconnection piece and second interconnection piece The side wall and the conductive lining ring between diffusion barrier layer.
11. microelectronic component according to claim 1, wherein the first substrate and the second substrate respectively include half Conductor tube core and inserter respectively include the first semiconductor element and the second semiconductor element.
12. a kind of method for forming microelectronic component, comprising:
The first layer for being wherein suspended with the first self assembly host material of the first conductive particle is applied to the of the first interconnection piece In one side wall and lower surface；
First interconnection piece is located on the first surface of first substrate；
The second layer for being wherein suspended with the second self assembly host material of the second conductive particle is applied to the of the second interconnection piece On two side walls and upper surface；
Second interconnection piece is located on the second surface of the second substrate；
A part of the first layer is removed temporarily to expose the lower surface of first interconnection piece；
A part of the second layer is removed temporarily to expose the upper surface of second interconnection piece；And
First conductive particle and the first self assembly host material are subjected to PHASE SEPARATION, and conductive by described second Particle and the second self assembly host material carry out PHASE SEPARATION, to provide around first interconnection piece and described second mutually The even conductive lining ring of the side wall of part and the dielectric layer around the conductive lining ring；
Wherein for first interconnection piece of diffusion bonding each other and second interconnection piece, the second surface and described the One surface is spaced apart 5 microns or smaller gap.
13. further including according to the method for claim 12, by the lower surface of first interconnection piece and described second The upper surface of interconnection piece each other diffusion bonding with for the electric conductivity between the first substrate and the second substrate, it After carry out the PHASE SEPARATION.
14. according to the method for claim 13, wherein mutually by the lower surface of first interconnection piece and described second Even diffusion bonding includes being formed to expand between the lower surface and the corresponding upper surface each other for the upper surface of part Dissipate bonding layer.
15. according to the method for claim 12, wherein the PHASE SEPARATION includes:
The first self assembly host material and the second self assembly host material are heated to be formed with intermetallic compound Conductive lining ring, the intermetallic compound include first conductive particle from the first self assembly host material and Second conductive particle from the second self assembly host material；
The intermetallic compound autoregistration is adhered to the side wall of first interconnection piece and second interconnection piece On；And
By the first self assembly host material and the second self assembly host material and the intermetallic compound autoregistration Ground fractional condensation provides the dielectric layer for surrounding the conductive lining ring as polymer mesh.
16. according to the method for claim 12, wherein the PHASE SEPARATION include by first conductive particle with it is described The separation of first self assembly host material, and second conductive particle is separated with the second self assembly host material, with The barrier layer for surrounding the side wall of first interconnection piece and second interconnection piece, the conduction around the barrier layer are provided Lining ring and the dielectric layer around the conductive lining ring.
17. according to the method for claim 16, wherein the PHASE SEPARATION includes:
The first self assembly host material and the second self assembly host material are heated to form the barrier layer and described Conductive lining ring；
The barrier layer autoregistration is adhered on the side wall of first interconnection piece and second interconnection piece；
The conductive lining ring autoregistration is adhered to the side surface on the barrier layer；And
The first self assembly host material and the second self assembly host material and the conductive lining ring autoregistration are divided The solidifying dielectric layer provided as polymer mesh around the conductive lining ring.
18. according to the method for claim 12, in which:
The part of the removal first layer includes planarizing the lower surface to temporarily expose the lower surface；And And
The part of the removal second layer includes making the top surface plane so as to temporarily expose the upper surface.
19. a kind of method for forming microelectronic component, comprising:
The first layer for being wherein suspended with the first self assembly host material of the first conductive particle is applied to the of the first interconnection piece In one side wall and lower surface；
First interconnection piece is located on the first surface of first substrate；
The second layer for being wherein suspended with the second self assembly host material of the second conductive particle is applied to the of the second interconnection piece On two side walls and upper surface；
Second interconnection piece is located on the second surface of the second substrate；
By the second layer on the first layer and the upper surface on the lower surface it is close to each other or contact；
First conductive particle and the first self assembly host material are subjected to PHASE SEPARATION, and conductive by described second Particle and the second self assembly host material carry out PHASE SEPARATION, to provide around first interconnection piece and described second mutually Connect the conductive lining ring of the side wall of part, positioned at the lower surface of first interconnection piece and the upper table of second interconnection piece Bonding layer between face and the dielectric layer around the conductive lining ring；
Wherein for first interconnection piece and second interconnection piece that are engaged between metal each other, the second surface with it is described First surface is spaced apart 5 microns or smaller gap.
20. according to the method for claim 19, wherein the PHASE SEPARATION includes:
A part associated with the lower surface of first interconnection piece in the first layer is pressed into described second In a part associated with the upper surface of second interconnection piece in layer；
The first self assembly host material and the second self assembly host material are heated to be formed:
The conductive lining ring with intermetallic compound, the intermetallic compound includes coming from the first self assembly matrix The first part of first conductive particle of material and described second conductive from the second self assembly host material The first part of grain；With
The bonding layer with the intermetallic compound, the intermetallic compound include coming from the first self assembly base The second part of first conductive particle of material and described second conductive from the second self assembly host material The second part of particle；
The intermetallic compound autoregistration is adhered to the side wall of first interconnection piece and second interconnection piece On；And
By the first self assembly host material and the second self assembly host material and the intermetallic compound autoregistration Ground fractional condensation is used as polymer mesh, to provide the dielectric layer around the conductive lining ring.
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Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9331043B1 (en) * 2015-01-30 2016-05-03 Invensas Corporation Localized sealing of interconnect structures in small gaps
US10886250B2 (en) * 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
TWI822659B (en) 2016-10-27 2023-11-21 美商艾德亞半導體科技有限責任公司 Structures and methods for low temperature bonding
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
TWI738947B (en) 2017-02-09 2021-09-11 美商英帆薩斯邦德科技有限公司 Bonded structures and method of forming the same
US10508030B2 (en) 2017-03-21 2019-12-17 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
US10923408B2 (en) 2017-12-22 2021-02-16 Invensas Bonding Technologies, Inc. Cavity packages
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
CN110164782A (en) * 2018-02-13 2019-08-23 财团法人工业技术研究院 Encapsulating structure and the method for component connection
TWI709213B (en) * 2018-02-13 2020-11-01 財團法人工業技術研究院 Package structure and method for conecting components
US11004757B2 (en) * 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
US10383225B1 (en) * 2018-08-10 2019-08-13 Seagate Technology Llc Interposer with offset-stacked traces
US11715895B2 (en) 2020-07-09 2023-08-01 Seagate Technology Llc Methods for making electrical connectors with an electrical interposer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101002313A (en) * 2004-11-25 2007-07-18 罗姆股份有限公司 Semiconductor device
CN101874296A (en) * 2007-09-28 2010-10-27 泰塞拉公司 Flip chip interconnection with double post
CN102891130A (en) * 2011-07-21 2013-01-23 矽品精密工业股份有限公司 Semiconductor package and fabrication method thereof

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3506393B2 (en) * 1993-03-11 2004-03-15 株式会社東芝 Liquid crystal display device and its manufacturing method, printer and its manufacturing method
JP3964911B2 (en) 2004-09-03 2007-08-22 松下電器産業株式会社 Manufacturing method of substrate with bumps
TWI273667B (en) * 2005-08-30 2007-02-11 Via Tech Inc Chip package and bump connecting structure thereof
JP2008071812A (en) * 2006-09-12 2008-03-27 Fujikura Ltd Board connection structure
US20080284041A1 (en) * 2007-05-18 2008-11-20 Samsung Electronics Co., Ltd. Semiconductor package with through silicon via and related method of fabrication
US7820543B2 (en) * 2007-05-29 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced copper posts for wafer level chip scale packaging
US20080308932A1 (en) * 2007-06-12 2008-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package structures
US8263434B2 (en) * 2009-07-31 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
CN102959708B (en) * 2010-06-29 2016-05-04 柯立芝照明有限公司 There is the electronic installation of flexible substrate
US20130256913A1 (en) * 2012-03-30 2013-10-03 Bryan Black Die stacking with coupled electrical interconnects to align proximity interconnects
US9331043B1 (en) * 2015-01-30 2016-05-03 Invensas Corporation Localized sealing of interconnect structures in small gaps

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101002313A (en) * 2004-11-25 2007-07-18 罗姆股份有限公司 Semiconductor device
CN101874296A (en) * 2007-09-28 2010-10-27 泰塞拉公司 Flip chip interconnection with double post
CN102891130A (en) * 2011-07-21 2013-01-23 矽品精密工业股份有限公司 Semiconductor package and fabrication method thereof

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