CN114388376A

CN114388376A - Semiconductor substrate

Info

Publication number: CN114388376A
Application number: CN202111458990.XA
Authority: CN
Inventors: 陈昭丞; 张皇贤
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2021-12-02
Filing date: 2021-12-02
Publication date: 2022-04-22

Abstract

The present invention provides a semiconductor substrate comprising: an interconnect, the interconnect comprising: a first metal layer on a surface of the semiconductor substrate; a second metal layer located on the first metal layer; and the adhesion layer is positioned between the first metal layer and the second metal layer and is in direct contact with the second metal layer. The invention aims to provide a semiconductor substrate, which at least improves the yield of the semiconductor substrate.

Description

Semiconductor substrate

Technical Field

Embodiments of the invention relate to semiconductor substrates.

Background

In the Chip last (Chip last) process, a copper pillar (Cu pillar) and an Under Bump Metal (UBM) are mainly used as a connector (interconnector) between an electronic device and a redistribution layer (RDL), however, since the copper pillar needs to use a solder (e.g., SnAg) as a bonding material in order to bond a medium with a lower melting point, an intermetallic compound (IMC) is generated between Cu and the solder after Reflow (Reflow), which is unfavorable for electrical performance, although a barrier (barrier) layer (e.g., Ni) may be formed between SnAg and Cu to limit IMC diffusion, but as the bump size is smaller (e.g., less than 10 μm), the amount of SnAg must also be reduced, so that IMC (Ni) generated by the underlying SnAg and Ni layer is relatively reduced₃Sn₄) The volume of SnAg is greatly occupied, and the subsequent joint surface has air gaps (Void) and embrittlement problems.

Disclosure of Invention

In view of the problems in the related art, an object of the present invention is to provide a semiconductor substrate, so as to at least improve the yield of the semiconductor substrate.

To achieve the above object, the present invention provides a semiconductor substrate comprising: an interconnect, the interconnect comprising: a first metal layer on a surface of the semiconductor substrate; a second metal layer located on the first metal layer; and the adhesion layer is positioned between the first metal layer and the second metal layer and is in direct contact with the second metal layer.

In some embodiments, the adhesion layer has a conductivity greater than a conductivity of the second metal layer.

In some embodiments, the roughness of the interface of the adhesion layer with the second metal layer is greater than the roughness of the interface of the adhesion layer with the first metal layer.

In some embodiments, the adhesion layer has a plurality of protrusions formed on an upper surface thereof, and the second metal layer covers the plurality of protrusions.

In some embodiments, the adhesion layer is a non-metallic material.

In some embodiments, the second metal layer encapsulates an upper portion of the sidewall of the adhesion layer.

In some embodiments, the interconnect further comprises: and the intermetallic compound (IMC) wraps the lower part of the side wall of the adhesion layer, and is in contact with the first metal layer and the second metal layer.

In some embodiments, the adhesion layer includes a plurality of pillars extending in the longitudinal direction, and the intermetallic compound is located between adjacent pillars.

In some embodiments, further comprising: and the third metal layer is positioned between the first metal layer and the adhesion layer, and the material of the third metal layer is different from that of the first metal layer and that of the second metal layer.

In some embodiments, the adhesion layer is graphite or graphene.

Another aspect of an embodiment of the present application provides a semiconductor substrate, including: an interconnect, the interconnect comprising: a first metal layer on a surface of the semiconductor substrate; the second metal layer is positioned above the first metal layer; and a non-metal layer between and electrically connecting the first metal layer and the second metal layer, wherein an intermetallic compound (IMC) is not present between the first metal layer and the second metal layer.

In some embodiments, the non-metallic layer has a thermal conductivity greater than the first and second metallic layers.

In some embodiments, the non-metallic layer has a greater conductivity than the second metallic layer.

In some embodiments, the first metal layer is a bump, and the lateral dimension of the non-metal layer is constant from top to bottom.

In some embodiments, further comprising: and an Under Bump Metallurgy (UBM) between the pad of the semiconductor substrate and the first metal layer.

In some embodiments, the first metal layer is a via and the non-metal layer increases in lateral dimension from top to bottom.

In some embodiments, the lower surface of the first metal layer contacts the redistribution layer of the semiconductor substrate.

In some embodiments, the first metal layer and the second metal layer are not in contact with each other.

In some embodiments, the second metal layer is a solder ball.

In some embodiments, when the semiconductor substrate is inverted over another semiconductor substrate, the second metal layers of the two are in contact with each other and no air gap exists therebetween.

Drawings

Fig. 1 to 8 show schematic views of a package according to an embodiment of the prior art.

Fig. 9A to 33 show schematic views of a semiconductor substrate and a process of forming the same according to an embodiment of the present application.

Detailed Description

In order to better understand the spirit of the embodiments of the present application, the following further description is given in conjunction with some preferred embodiments of the present application.

Embodiments of the present application will be described in detail below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.

As used herein, the terms "substantially", "substantially" and "about" are used to describe and illustrate minor variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation that is less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, two numerical values are considered to be "substantially" identical if the difference between the two numerical values is less than or equal to ± 10% (e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%) of the mean of the values.

In this specification, unless specified or limited otherwise, relative terms such as: terms of "central," "longitudinal," "lateral," "front," "rear," "right," "left," "inner," "outer," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described in the discussion or as shown in the drawing figures. These relative terms are for convenience of description only and do not require that the present application be constructed or operated in a particular orientation.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.

Moreover, for convenience in description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.

Referring to fig. 1, in a Wafer Level Chip Scale Packaging (WLCSP) 10, a controlled collapse Chip connection (C4) bump (C4 bump) is typically used, as shown in electron microscope image a. As Bump Pitch (Bump Pitch) decreases, copper pillar bumps (Cu pillar bumps) are often used in 2.5D integrated circuits (2.5D ICs), fan-out multi-chip modules (fan-out multi-chips modules), as shown in sem image b. When the bump pitch is reduced to 10 to 40 μm, defects are generated in an underfill layer (underfill) of a product, and thus a Thermo Compression Bonding (TCB) process, a Thermo-Compression capillary underfill (TCCUF), a Thermo-Compression non-conductive film (TCNCF), and a Thermo-Compression non-conductive paste (TCNCP) are extended. When the bump pitch is reduced to below 10 μm, an intermetallic compound (IMC) problem may occur, and the embodiments of the present application may enable a copper pillar bump (Cu pillar bump) to be applied to a package in which the bump pitch is reduced to below 10 μm.

In 3-dimensional integrated circuit (3D IC) packages, the solder interconnect pitch is scaled down to 10 μm. However, one of the biggest challenges for such fine pitch welding (solder joint) is intermetallic compound (IMC). During assembly or reliability testing, most or even all solder is easily converted to IMC, resulting in solder failure or cracking due to volume shrinkage. FIGS. 2A to 2B are electron micrographs of the package with solder pitch below 10 μm, and referring to FIG. 2A, it can be seen that IMC (Cu) is formed between bump (Cu)20 and solder (SnAg)22₆Sn₃) Fig. 2B shows the failure of the two bumps 20 to join together 24. FIGS. 3A-3D illustrate reliable burn-in testing of packages with solder spacing below 10 μm, with temperature stabilizationFig. 3A to 3D are solder views of the bump 20 at 150 c for test periods of 0 hour, 168 hours, 1008 hours, 2016 hours, respectively, in which the solder joint is cracked (Crack) in fig. 3D.

Referring to fig. 4, the outline becomes rounded after reflow of the solder 2 and an IMC 24 is formed between the bump 20 and the solder 22 after reflow, and precisely, the IMC 24 is formed by a reaction of a portion of the material of the bump 20 and a portion of the material of the solder 22. In some embodiments bumps 20 are copper, solder 22 is SnAg, and IMC 24 is Cu₆Sn₃。

Referring to fig. 5, when the two packages are joined, one of the packages is inverted over the other so that their solders 22 face each other.

Referring to fig. 6, the solder 22 of fig. 4 becomes the IMC 24 after undergoing a Thermo Compression Bonding (TCB) process/Diffusion Bonding (Diffusion Bond) process. The failure rate of the two solders 22 to be bonded to each other is greater than 80%.

Referring to fig. 7, the prior art has formed a barrier layer 70 between the solder 22 and the bump 20. In some embodiments barrier layer 70 is a Ni layer. Fig. 7 shows two solders 22 bonded to each other.

Referring to fig. 8, in a Reliability Test (Reliability Test), a second IMC 80 is formed between the barrier layer 70 and the solder 22. In some embodiments, the second IMC 80 is Ni₃Sn₄. In some embodiments, all of the barrier layers 70 of fig. 7 form a second IMC 80 with the solder 22 in the step of fig. 8. When the solder 22 reacts with the barrier layer 70, the volume of the solder 22 is reduced (by about 11.3%), causing cracks/air gaps to also develop in the middle of the solder 22. The reduction in volume of the solder 22 is not controllable and cracks/air gaps can occur in the prior art, and if the barrier layer 70 is not added, the solder 22 can be converted to Cu before/at the TCB process₆Sn₅(in this case, the volume is reduced by 5%) or Cu₃Sn (in this case, the volume is reduced by 7.4%). Mean-time-to-fail (MTTF) of prior art devices in Electromigration (EM) testing is low (<1000hrs)。

The semiconductor substrate and the method of forming the same of the present application will be described in detail below with reference to the accompanying drawings.

Referring to fig. 9A, in some embodiments, a semiconductor substrate 90 of the present application includes a carrier substrate 92, a redistribution layer 94 on the carrier substrate 92, a first metal layer 900 on the redistribution layer 94, an adhesion layer 901 on the first metal layer 900, and a second metal layer 902 on the adhesion layer 901, the first metal layer 900 being surrounded by the first dielectric layer 96, the first metal layer 900, the adhesion layer 901, and the second metal layer 902 making up a connection. In some embodiments, first metal layer 900 is a copper via, adhesion layer 901 is Graphite (Graphite), and second metal layer 902 is solder. In some embodiments, the first dielectric layer 96 is a Polyamide (PA) material that functions as a passivation layer. In some embodiments, redistribution layer 94 is a fan-out redistribution layer and includes multiple layers. In some embodiments, the lateral dimension of the attachment layer 901 increases from top to bottom.

Referring to fig. 9B, in some embodiments, the semiconductor substrate 100 of the present application includes a wafer 102, a pad 104 on the wafer 102, an Under Bump Metallurgy (UBM)106 on the pad 104, a first metal layer 1000 on the Under Bump Metallurgy (UBM)106, an adhesion layer 1001 on the first metal layer 1000, a second metal layer 1002 on the adhesion layer 1001, and a passivation layer 108 between the UBM106 and the wafer 102, wherein the first metal layer 1000, the adhesion layer 1001, and the second metal layer 1002 constitute a connection. In some embodiments, the second metal layer 1002 wraps around the upper portion of the sidewall of the adhesion layer 1001, and the first metal layer 1000 does not contact the second metal layer 1002. In some embodiments, the materials of the first metal layer 1000, the adhesion layer 1001 and the second metal layer 1002 are the same as the first metal layer 900, the adhesion layer 901 and the second metal layer 902, respectively. In some embodiments, the first metal layer 1000 is a copper pillar (pilar)/copper bump (bump). In some embodiments, the lateral dimension of the adhesion layer 1001 is constant from top to bottom. In some embodiments, the pitch of the first metal layer 1000 is 1 μm to 100 μm and the diameter is 1 μm to 40 μm. In some embodiments, adhesion layer 901 has a thickness of 5 to 1000 angstroms and a diameter of 5 to 20 μm. When the thickness of the adhesion layer 901 is 5 to 1000 angstroms, the conductivity is higher than that of the existing Ni layer, which contributes to the improvement of the electrical performance of the structure. The connector shown in fig. 9A and 9B of the present application can be used not only for a semiconductor substrate but also for a semiconductor chip, a die, and a wiring layer. When structures having the connectors of the present application (such as the substrates shown in fig. 9A and/or 9B) are joined two-by-two, no cracks/air gaps, as in the prior art, are created between the solders.

Fig. 10 to 23 show a process of forming the semiconductor substrate 90 of fig. 9A. Referring to fig. 10, a release layer 109 is provided on the first carrier 105. The first carrier 105 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The first carrier 105 may be a wafer (circular wafer/square wafer) such that a plurality of package structures may be formed simultaneously on the first carrier 105. The release layer 109 may be formed of a polymer-based material that may be removed with the first carrier 105 from an overlying structure to be formed in a subsequent step. In some embodiments, the release layer 109 is an epoxy-based thermal release material that loses its adhesion upon heating, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer 109 may be an Ultraviolet (UV) glue that loses its adhesion when exposed to UV light. The release layer 109 may be dispensed in liquid form and cured, may be a laminated film laminated on the first carrier 105, or may be similar. The top surface of the release layer 109 may be horizontal and may have a high degree of planarity.

Referring to fig. 11, an adhesion layer 901 is formed on the release layer 109. In some embodiments, the adhesion layer 901 is a graphite thin film. In some embodiments, the adhesion layer 901 is Graphene (Graphene) deposited by using a Plasma-Enhanced Chemical Vapor Deposition (PECVD) process, so that the roughness of the upper surface is greater than that of the lower surface, thereby improving the adhesion and butt effects between the second metal layer 902 and the subsequent metal layer to prevent bonding failure. In some embodiments, adhesion layer 901 has a thickness of 5 angstroms to 1000 angstroms and a diameter greater than 10 μm.

Referring to fig. 12, a first seed layer 120 is sputter deposited on the adhesion layer 901. In some embodiments, the first seed layer 120 is copper.

Referring to fig. 13, a first dielectric layer 96 is formed on the first seed layer 120, the first dielectric layer 96 having an opening 130 therein exposing the first seed layer 120.

Referring to fig. 14, a first metal layer 900 is formed in the opening 130. In some embodiments, the first metal layer 900 is formed by an electroplating process.

Referring to fig. 15, a redistribution layer 94 is formed on the first metal layer 900.

Referring to fig. 16, the structure of fig. 15 is inverted on a second carrier 160. In some embodiments, the second carrier 160 is similar to the first carrier 105.

Referring to fig. 17, the first carrier 105, the release layer 109 is removed.

Referring to fig. 18, a patterned first mask layer 180 is formed on the adhesion layer 901, the first mask layer 180 being aligned with the first metal layer 900. In some embodiments, the first mask layer 180 is a Photoresist (PR).

Referring to fig. 19, the adhesion layer 901 is patterned (e.g., by a plasma dry etch process).

Referring to fig. 20, the first mask layer 180 is removed/stripped.

Referring to fig. 21, a patterned second mask layer 210 is formed at a position not covered with the adhesion layer 901. In some embodiments, the second mask layer 210 is a Photoresist (PR).

Referring to fig. 22, a second metal layer 902 is formed (e.g., by an electroplating process) on the adhesion layer 901.

Referring to fig. 23, the second mask layer 210 is removed, and the first seed layer 120 not covered by the second metal layer 902 is removed. After performing the reflow process, the second metal layer 902 is transformed into the rounded shape shown in fig. 9A.

Fig. 24-29 illustrate a formation process of the embodiment shown in fig. 9B. Referring to fig. 24, a pad 104 is formed on a wafer 102, and a passivation layer 108 covers an edge of the pad 104. A second seed layer 240 is sputter deposited over the pad 104 and passivation layer 108. In some embodiments, the second seed layer 240 is similar to the first seed layer 120.

Referring to fig. 25, a third mask layer 250 is formed on the second seed layer 240, the third mask layer 250 having a second opening 252 therein. In some embodiments, the third mask layer 250 is a Photoresist (PR).

Referring to fig. 26, a first metal layer 1000 is formed in the second opening 252. In some embodiments, the first metal layer 1000 is formed by an electroplating process.

Referring to fig. 27, an adhesion layer 1001 is formed on a first metal layer 1000. In some embodiments, the adhesion layer 1001 is formed by forming Graphene Oxide (GO) 270 on the first metal layer 1000, and then soaking in a solution to perform an electrochemical reduction reaction, with the Graphene Oxide 270 serving as a cathode, to reduce the Graphene Oxide 270 into Reduced Graphene Oxide (rGO) 272. In some embodiments, adhesion layer 1001 is 5 angstroms to 1000 angstroms thick and greater than 10 μm in diameter.

Referring to fig. 28, a second metal layer 1002 is formed on the adhesion layer 1001.

Referring to fig. 29, the third mask layer 250 is removed and the second seed layer 240 not covered by the second metal layer 1002 is removed. After performing the reflow process, the second metal layer 1002 is transformed into a rounded shape as shown in fig. 9B.

Fig. 30 to 33 show other embodiments of the semiconductor substrate of the present application. Referring to fig. 30, in some embodiments, unlike fig. 9A, a plurality of protrusions are formed on an upper surface of an adhesion layer 901, and a second metal layer 902 covers the plurality of protrusions. The plurality of protrusions increases the contact area between the second metal layer 902 and the adhesion layer 901, so that the second metal layer 902 adheres to the adhesion layer 901 more firmly.

Referring to fig. 31, in some embodiments, unlike fig. 9B, a first metal layer 1000 is in contact with a second metal layer 1002 at sidewalls of an adhesion layer 1001 and reacts with each other to form IMCs (Cu)₆Sn₃)310。

Referring to fig. 32, in some embodiments, unlike fig. 31, the attachment layer 1001 includes a plurality of posts/protrusions extending in a longitudinal direction, with IMCs 310 also being located between adjacent posts/protrusions.

Referring to fig. 33, in some embodiments, unlike fig. 9B, the third metal layer 330 is located between the first metal layer 1000 and the adhesion layer 1001, the material of the third metal layer 330 is different from the first metal layer 1000 and the second metal layer 1002, the third metal layer 330 does not generate IMC with the first metal layer 1000, and may enhance the adhesion between the adhesion layer 1001 and the first metal layer 1000, and in some embodiments, the third metal layer 330 may be a Ni, Au, Ti, Ta layer, or the like.

Graphite is an excellent barrier material due to its "network and multi-layer graphene" structure, copper cannot diffuse into the solder, and there is no reaction between copper and graphite, solder and graphite. Graphite (Graphene) film is a diffusion barrier with excellent properties, chemical inertness and low resistivity (resistivity unit is mu omega-cm: Graphene, 1-15; copper, 1.7; silver, 1.59; Sn-3.5Ag, 11.5; Cu)₃Sn，8.3；Cu₆Sn₅17.5), high thermal conductivity (thermal conductivity of graphene is 5300W/mK, thermal conductivity of copper is 401W/mK, and thermal conductivity of solder is 67W/mK). The product of the embodiment of the application can pass reliability test: maintaining at an isothermal temperature of 150 ℃ to 180 ℃ for 500hrs to 1000 hrs; performing concentrated reflux (Mass reflux) at a maximum temperature of 245 deg.C, repeating for 5-10 times; electromigration (EM) test, the current is 300mA to 900mA, and the temperature is 130 ℃ to 150 ℃. Embodiments of the present application improve fine pitch (less than 10 μm) solder bonding process temperature performance and reliability: solder Bonding has a low failure rate after Thermo Compression Bonding (TCB) process: (<1%); low crack/air gap defect rate after isothermal aging test: (<1%); has higher MTTF (in EM test)>2000 hours). Embodiments of the present application extend the now mature TCB process to fine pitch solder (less than 10 μm) bonding, are low cost, and have no additional IMC generation in assembly and reliability testing, excellent reliability performance and environmental stress tolerance, and the products of embodiments of the present application have ultra-high product lifetimes.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor substrate, comprising:

an interconnect, the interconnect comprising:

a first metal layer on a surface of the semiconductor substrate;

a second metal layer located on the first metal layer;

an adhesion layer between the first metal layer and the second metal layer, the adhesion layer in direct contact with the second metal layer.

2. The semiconductor substrate of claim 1, wherein the adhesion layer has a conductivity greater than a conductivity of the second metal layer.

3. The semiconductor substrate according to claim 1, wherein a roughness of a contact surface of the adhesion layer with the second metal layer is larger than a roughness of a contact surface of the adhesion layer with the first metal layer.

4. The semiconductor substrate according to claim 3, wherein a plurality of protrusions are formed on an upper surface of the adhesion layer, and the second metal layer covers the plurality of protrusions.

5. The semiconductor substrate of claim 1, wherein the adhesion layer is a non-metallic material.

6. The semiconductor substrate according to claim 1, further comprising:

and the third metal layer is positioned between the first metal layer and the adhesion layer, and the material of the third metal layer is different from that of the first metal layer and that of the second metal layer.

7. The semiconductor substrate of claim 1, wherein the adhesion layer is graphite or graphene.

8. A semiconductor substrate, comprising:

an interconnect, the interconnect comprising:

a first metal layer on a surface of the semiconductor substrate;

a second metal layer located above the first metal layer;

a non-metal layer between and electrically connecting the first metal layer and the second metal layer, an intermetallic compound (IMC) being absent between the first metal layer and the second metal layer.

9. The semiconductor substrate according to claim 8, wherein the nonmetal layer has a thermal conductivity greater than the first metal layer and the second metal layer.

10. The semiconductor substrate of claim 8, wherein the non-metal layer has a greater electrical conductivity than the second metal layer.