CN107154722A - A kind of automatic switch-over circuit of PWM and PFM applied to switching regulator - Google Patents
A kind of automatic switch-over circuit of PWM and PFM applied to switching regulator Download PDFInfo
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- CN107154722A CN107154722A CN201710546983.2A CN201710546983A CN107154722A CN 107154722 A CN107154722 A CN 107154722A CN 201710546983 A CN201710546983 A CN 201710546983A CN 107154722 A CN107154722 A CN 107154722A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0012—Control circuits using digital or numerical techniques
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention discloses a kind of automatic switch-over circuit of PWM and PFM applied to switching regulator, including PFM judge modules, minimum ON time control module, first OR-NOT circuit, second OR-NOT circuit, 3rd OR-NOT circuit, four nor gate circuit, 5th OR-NOT circuit, hex inverter, 7th and gate circuit, first OR-NOT circuit, second OR-NOT circuit, 3rd OR-NOT circuit, four nor gate circuit, 5th OR-NOT circuit is two input nor gates, traditional pwm signal is produced PFM signals by the present invention by digital logical operation, avoid the matching sex chromosome mosaicism of PWM module parameter and PFM module parameters in design, fundamentally solve the catastrophe point that PWM and PFM automatic switchovers are brought, realize that PWM and PFM are seamlessly transitted.
Description
Technical field
The present invention relates to a kind of PWM and PFM switching circuit, more particularly to a kind of PWM applied to switching regulator
With PFM automatic switch-over circuit.
Background technology
Prior art when switching regulator is designed, PWM and PFM automatic switching functions by the PWM of independent design and
PFM control modules, produce the critical switching points of PWM/PFM of an emulation mode, by judging working state of system and switching point
Relation, come realize PWM/PFM automatically switch.Because regulator switch signal inevitably shake and interference, PWM/PFM faces
The discrete and mismatch Conditions of a small range are necessarily presented in boundary's switching point, because judging the uncertainty of point, cause output voltage line
There is the line for the cluster cluster that multiple cycle conductings are shown as in mutational range, test with load and the change of input and output voltage in ripple
Ripple, causes output voltage ripple amplitude to increase, and light-load efficiency is also reduced by, it is impossible to reach that preferable PWM and PFM are seamlessly transitted.
The content of the invention
Present invention solves the technical problem that being to provide a kind of one kind for realizing that PWM and PFM are seamlessly transitted is applied to switching regulator
The PWM and PFM of voltage-stablizer automatic switch-over circuit.
The technical solution adopted for the present invention to solve the technical problems is：A kind of PWM applied to switching regulator and
PFM automatic switch-over circuit, including PFM judge modules, minimum ON time control module, the first OR-NOT circuit, second or
Not circuit, the 3rd OR-NOT circuit, four nor gate circuit, the 5th OR-NOT circuit, hex inverter, the 7th and door electricity
Road, first OR-NOT circuit, the second OR-NOT circuit, the 3rd OR-NOT circuit, four nor gate circuit, the 5th nor gate
Circuit is two input nor gates；
The output end of the minimum ON time control module of input connection of first OR-NOT circuit, second or
Another input of not circuit is to connect external PWM signal；
The first input end of the PFM judge modules is connected with the output end of the first OR-NOT circuit, PFM judge modules
Second input is connected with the input of hex inverter；
The input of second OR-NOT circuit connects the output end of PFM judge modules and the input of hex inverter respectively
End；
The input of 3rd OR-NOT circuit connects the output end and the first OR-NOT circuit of the second OR-NOT circuit respectively
Output end；
The input of four nor gate circuit connects the output end and the 5th OR-NOT circuit of the 3rd OR-NOT circuit respectively
Output end；
The input of 5th OR-NOT circuit connects the output end and the 7th of four nor gate circuit with gate circuit respectively
Output end；
Switch voltage-stabilizing oscillator signal of the input of hex inverter to connect outside；
7th is connected the output end of the first OR-NOT circuit and the output of hex inverter respectively with the input of gate circuit
End；
The PFM judge modules function is as follows：When first input end level is logical zero, output end level is logic 1,
When first input end level is logic 1, when the second input receives switch voltage-stabilizing oscillator signal and is in rising edge, output
End level is logical zero；
The minimum ON time control module function is as follows：When input level is logical zero, output end signal level
For logical zero, when input level is logic 1, output end level is logic 1, and the level after a fixed delay time
Overturn as logical zero.
It is further：The minimum ON time control module includes the 8th phase inverter, the 9th phase inverter, resistance, electricity
Appearance, the tenth nor gate, the input of the 8th phase inverter are connected with the output end of the 5th phase inverter, the input of the 9th phase inverter
End is connected with the output end of the 8th phase inverter, and the output end of the 9th phase inverter and one end of resistance are connected, the tenth nor gate
Input be connected respectively with the other end of resistance and the output end of the 8th phase inverter, the output end of the tenth nor gate and the
The input connection of one nor gate, the positive pole of the electric capacity and the other end of resistance are connected, and the negative pole of electric capacity is connected with region.
The beneficial effects of the invention are as follows：Traditional pwm signal is produced PFM signals by the present invention by digital logical operation,
The matching sex chromosome mosaicism of PWM module parameter and PFM module parameters in design is avoided, PWM is fundamentally solved and PFM is automatic
Switch the catastrophe point brought, realize that PWM and PFM are seamlessly transitted.
Brief description of the drawings
Fig. 1 is PWM/PFM automatic switchover schematic diagrams.
Fig. 2 is minimum ON time control module schematic diagram.
Fig. 3 is that PWM and PFM work schedules illustrate figure.
Marked in figure：PFM judge modules 1, minimum ON time control module 2, the first OR-NOT circuit 3, second or
Not circuit 4, the 3rd OR-NOT circuit 5, four nor gate circuit 6, the 5th OR-NOT circuit 7, hex inverter the 8, the 7th with
Gate circuit 9, the 8th phase inverter 10, the 9th phase inverter 11, resistance 12, electric capacity 13, the tenth nor gate 14.
Embodiment
The present invention is further described with reference to the accompanying drawings and detailed description.
The automatic switch-over circuit of PWM and PFM applied to switching regulator as shown in Figure 1 to Figure 3 a kind of, including
PFM judge modules 1, minimum ON time control module 2, the first OR-NOT circuit 3, the second OR-NOT circuit 4, the 3rd nor gate
Circuit 5, four nor gate circuit 6, the 5th OR-NOT circuit 7, hex inverter the 8, the 7th and gate circuit 9, described first or non-
Gate circuit 3, the second OR-NOT circuit 4, the 3rd OR-NOT circuit 5, four nor gate circuit 6, the 5th OR-NOT circuit 7 are two
Input nor gate；
The output end of the minimum ON time control module 2 of input connection of first OR-NOT circuit 3, second
Another input of OR-NOT circuit 4 is to connect external PWM signal；
The first input end of the PFM judge modules 1 is connected with the output end of the first OR-NOT circuit 3, PFM judge modules
1 the second input is connected with the input of hex inverter 8；
The input of second OR-NOT circuit 4 connect respectively PFM judge modules 1 output end and hex inverter 8 it is defeated
Enter end；
The input of 3rd OR-NOT circuit 5 connects the output end and the first nor gate electricity of the second OR-NOT circuit 4 respectively
The output end on road 3；
The input of four nor gate circuit 6 connects the output end and the 5th nor gate electricity of the 3rd OR-NOT circuit 5 respectively
The output end on road 7；
The input of 5th OR-NOT circuit 7 connects the output end and the 7th and gate circuit 9 of four nor gate circuit 6 respectively
Output end；
Switch voltage-stabilizing oscillator signal of the input of hex inverter 8 to connect outside；
7th with the input of gate circuit 9 be connected respectively the first OR-NOT circuit 3 output end and hex inverter 8 it is defeated
Go out end；
The function of PFM judge modules 1 is as follows：When first input end level is logical zero, output end level is logic 1,
When first input end level is logic 1, when the second input receives switch voltage-stabilizing oscillator signal and is in rising edge, output
End level is logical zero, and the PFM judge modules 1 are common triggers circuit；
The minimum function of ON time control module 2 is as follows：When input level is logical zero, output end signal electricity
Put down as logical zero, when input level is logic 1, output end level is logic 1, and electric after a fixed delay time
Flat upset is logical zero.
Each gate circuit in foregoing circuit can be built by traditional circuit can also be used the Digital Logic editor such as CPLD
Device is built, and above two method is the common method for building logic circuit, is just repeated no more herein.
Describe for convenience, if the output end of the first OR-NOT circuit 3 is Section Point, the output end of PFM judge modules 1
For the 3rd node, the output end of the second OR-NOT circuit 4 is fourth node, and the 3rd nor gate output end is the 5th node, the 4th
Nor gate output end is the 6th node, and the 5th nor gate output end is the 7th node, the output of minimum ON time control module 2
Hold as first node.
Operationally, it is outer in PWM and PFM switching circuits in this PWM and the outside framework of PFM switching circuits and this area
Portion's framework is identical, and another input of the second OR-NOT circuit 4 is believed to connect the standard PWM of external switch formula voltage-stablizer
Number, pwm signal is controlled by external feedback voltage, and it is logical zero that the upset of the 7th node is can trigger during PWM rising edges, and the 3rd node connects
External perimysium reference PFM control modules are connect, the PFM control modules are completely the same to the controlling behavior and common PFM of circuit remaining module,
The outside main power tube of 7th node connection, hex inverter 8 connects outside osc signal, i.e. switching regulator oscillator signal,
The rising edge triggering power tube of osc signal is opened, and when the 7th node exports logic 1, driving main power tube is opened, when Section seven
During point output logical zero, main power tube is closed, and when the 3rd node exports logic 1, represents that PFM control modules are in working condition
In, when the 3rd node exports logical zero, represent that PFM control modules are in holding state, OCS signals are set to logical zero, and this
In circuit, pwm signal is not controlled by PFM signals.
Coordinate Fig. 3 working timing figure, the PWM/PFM switching principles shown in Fig. 1 are as described below：
When PWM is logic 1, Section Point signal is logical zero, and the 3rd node signal is logic 1, and fourth node signal is
Logical zero, the 5th node signal is logical zero, and the 6th node and the 7th node signal are logic 1 so that power tube is opened, most
In the presence of small ON time control module 2, the opening time is TON_MIN, triggers the upset of the 7th node to patrol in PWM rising edges
0 is collected, main power tube is closed, PFM signals maintain logic 1, until temporarily next cycle OSC rising edges are just detected again.
When PWM is logical zero, Section Point signal is logic 1, and the 3rd node signal is at logical zero, PFM control modules
In holding state, fourth node is 1, and the 5th node is 0, and the 6th node is 1, and the 7th node is 0, and main power, which is in, closes shape
State, after main power tube is closed, has cut off input power to the bang path of power output, with persistently disappearing for load in system
Consumption, the output voltage of voltage-stablizer will be reduced constantly, export feedback voltage continuous decrease, and it is logic 1 to force pwm signal upset, the
Two node signals are reset to logical zero, and the 3rd node signal is set to logic 1, and the upset of the 7th node is logic 1, and main power tube is opened
Open, system logic hereafter can be to repeat to deduce with reference to the accompanying drawings 1 Suo Shi, and this circuit is according to minimum conducting under light condition
The PFM of time TON_MIN work, with load down, ON time maintains TON_MIN constant, and working frequency is gradually stepped up
And eventually equal to PWM fixed frequencies, afterwards as load is further aggravated, ON time will gradually increase, into PWM mode,
Whole transition Interval System works in monocycle pattern, reaches preferable PWM/PFM switchings.
Traditional pwm signal is produced PFM signals by the present invention by digital logical operation, it is to avoid PWM module parameter and
The matching sex chromosome mosaicism of PFM module parameters in design, fundamentally solves the catastrophe point that PWM and PFM automatic switchovers are brought, real
Existing PWM and PFM is seamlessly transitted.
On the basis of the above, the minimum ON time control module 2 include the 8th phase inverter 10, the 9th phase inverter 11,
Resistance 12, electric capacity 13, the tenth nor gate 14, the input of the 8th phase inverter 10 are connected with the output end of the 5th phase inverter,
The input of 9th phase inverter 11 is connected with the output end of the 8th phase inverter 10, output end and the resistance 12 of the 9th phase inverter 11
One end is connected, and the input of the tenth nor gate 14 connects with the other end of resistance 12 and the output end of the 8th phase inverter 10 respectively
Connect, the output end of the tenth nor gate 14 is connected with the input of the first nor gate, positive pole and the resistance 12 of the electric capacity 13
Other end connection, the negative pole of electric capacity 13 is connected with region, according to the value of resistance 12 and electric capacity 13 decision TON_MIN specific arteries and veins
The charging interval of width, i.e. electric capacity is TON_MIN specific pulsewidth.
Particular embodiments described above, has been carried out further in detail to the purpose of the present invention, technical scheme and beneficial effect
Describe in detail it is bright, should be understood that the foregoing is only the present invention specific embodiment, be not intended to limit the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvements done etc., should be included in the guarantor of the present invention
Within the scope of shield.
Claims (2)
1. the automatic switch-over circuit of PWM and PFM applied to switching regulator a kind of, it is characterised in that：Judge mould including PFM
Block (1), minimum ON time control module (2), the first OR-NOT circuit (3), the second OR-NOT circuit (4), the 3rd nor gate
Circuit (5), four nor gate circuit (6), the 5th OR-NOT circuit (7), hex inverter (8), the 7th and gate circuit (9), institute
State the first OR-NOT circuit (3), the second OR-NOT circuit (4), the 3rd OR-NOT circuit (5), four nor gate circuit (6),
Five OR-NOT circuits (7) are two input nor gates；
The output end of the minimum ON time control module (2) of input connection of first OR-NOT circuit (3), second
Another input of OR-NOT circuit (4) is to connect external PWM signal；
The first input end of the PFM judge modules (1) is connected with the output end of the first OR-NOT circuit (3), PFM judge modules
(1) the second input is connected with the input of hex inverter (8)；
The input of second OR-NOT circuit (4) connects the output end and hex inverter (8) of PFM judge modules (1) respectively
Input；
The input of 3rd OR-NOT circuit (5) connects the output end and the first nor gate electricity of the second OR-NOT circuit (4) respectively
The output end on road (3)；
The input of four nor gate circuit (6) connects the output end and the 5th nor gate electricity of the 3rd OR-NOT circuit (5) respectively
The output end on road (7)；
The input of 5th OR-NOT circuit (7) connects the output end and the 7th and gate circuit of four nor gate circuit (6) respectively
(9) output end；
Switch voltage-stabilizing oscillator signal of the input of hex inverter (8) to connect outside；
7th is connected the output end and hex inverter (8) of the first OR-NOT circuit (3) with the input of gate circuit (9) respectively
Output end；
PFM judge modules (1) function is as follows：When first input end level is logical zero, output end level is logic 1, when
When first input end level is logic 1, when the second input receives switch voltage-stabilizing oscillator signal and is in rising edge, output end
Level is logical zero；
Minimum ON time control module (2) function is as follows：When input level is logical zero, output end signal level
For logical zero, when input level is logic 1, output end level is logic 1, and the level after a fixed delay time
Overturn as logical zero.
2. a kind of PWM and PFM applied to switching regulator as claimed in claim 1 automatic switch-over circuit, its feature
It is：The minimum ON time control module (2) includes the 8th phase inverter (10), the 9th phase inverter (11), resistance (12), electricity
Hold (13), the tenth nor gate (14), the input of the 8th phase inverter (10) is connected with the output end of the 5th phase inverter, the 9th
The input of phase inverter (11) is connected with the output end of the 8th phase inverter (10), the output end and resistance of the 9th phase inverter (11)
(12) one end connection, the other end and the 8th phase inverter of the input of the tenth nor gate (14) respectively with resistance (12)
(10) output end connection, the output end of the tenth nor gate (14) is connected with the input of the first nor gate, the electric capacity
(13) positive pole is connected with the other end of resistance (12), and the negative pole of electric capacity (13) is connected with region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710546983.2A CN107154722B (en) | 2017-07-06 | 2017-07-06 | Automatic switching circuit applied to PWM and PFM of switching type voltage stabilizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710546983.2A CN107154722B (en) | 2017-07-06 | 2017-07-06 | Automatic switching circuit applied to PWM and PFM of switching type voltage stabilizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107154722A true CN107154722A (en) | 2017-09-12 |
| CN107154722B CN107154722B (en) | 2023-09-26 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710546983.2A Active CN107154722B (en) | 2017-07-06 | 2017-07-06 | Automatic switching circuit applied to PWM and PFM of switching type voltage stabilizer |
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| CN (1) | CN107154722B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109600129A (en) * | 2017-09-30 | 2019-04-09 | 深圳市海思半导体有限公司 | Delay cell and delay line |
| CN111030448A (en) * | 2019-12-30 | 2020-04-17 | 上海南芯半导体科技有限公司 | Light-load frequency reduction circuit of charge pump based on voltage difference control |
| CN114884493A (en) * | 2022-07-13 | 2022-08-09 | 广东汇芯半导体有限公司 | PWM signal decoder and single-input high-voltage integrated circuit using same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106787719A (en) * | 2016-12-05 | 2017-05-31 | 深圳信息职业技术学院 | A kind of voltage-dropping type DC DC converters of the double mode automatic switchovers of PWM/PFM |
| CN207184309U (en) * | 2017-07-06 | 2018-04-03 | 无锡麟力科技有限公司 | Automatic switch-over circuit applied to the PWM and PFM of switching regulator |
-
2017
- 2017-07-06 CN CN201710546983.2A patent/CN107154722B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106787719A (en) * | 2016-12-05 | 2017-05-31 | 深圳信息职业技术学院 | A kind of voltage-dropping type DC DC converters of the double mode automatic switchovers of PWM/PFM |
| CN207184309U (en) * | 2017-07-06 | 2018-04-03 | 无锡麟力科技有限公司 | Automatic switch-over circuit applied to the PWM and PFM of switching regulator |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109600129A (en) * | 2017-09-30 | 2019-04-09 | 深圳市海思半导体有限公司 | Delay cell and delay line |
| CN109600129B (en) * | 2017-09-30 | 2023-11-03 | 深圳市海思半导体有限公司 | Delay unit and delay line circuit |
| CN111030448A (en) * | 2019-12-30 | 2020-04-17 | 上海南芯半导体科技有限公司 | Light-load frequency reduction circuit of charge pump based on voltage difference control |
| CN111030448B (en) * | 2019-12-30 | 2020-12-29 | 上海南芯半导体科技有限公司 | Light-load frequency reduction circuit of charge pump based on voltage difference control |
| CN114884493A (en) * | 2022-07-13 | 2022-08-09 | 广东汇芯半导体有限公司 | PWM signal decoder and single-input high-voltage integrated circuit using same |
| CN114884493B (en) * | 2022-07-13 | 2022-09-20 | 广东汇芯半导体有限公司 | PWM signal decoder and single-input high-voltage integrated circuit using same |
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| Publication number | Publication date |
|---|---|
| CN107154722B (en) | 2023-09-26 |
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