CN107154378A - 绝缘层上顶层硅衬底及其制造方法 - Google Patents

绝缘层上顶层硅衬底及其制造方法 Download PDF

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CN107154378A
CN107154378A CN201610120565.2A CN201610120565A CN107154378A CN 107154378 A CN107154378 A CN 107154378A CN 201610120565 A CN201610120565 A CN 201610120565A CN 107154378 A CN107154378 A CN 107154378A
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insulating barrier
semiconductor substrate
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top layer
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肖德元
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Zing Semiconductor Corp
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Priority to TW105118832A priority patent/TWI592987B/zh
Priority to US15/258,899 priority patent/US20170256440A1/en
Priority to JP2016186873A priority patent/JP2017157814A/ja
Priority to DE102017100054.2A priority patent/DE102017100054A1/de
Priority to US15/415,609 priority patent/US10014210B2/en
Priority to KR1020170023836A priority patent/KR20170103651A/ko
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Abstract

本发明提供一种绝缘层上顶层硅衬底的制造方法，包括：提供一第一半导体衬底；在该第一半导体衬底的顶面形成一第一绝缘层；对该第一半导体衬底进行离子束注入，以便在距离该第一绝缘层的顶面的预定深度处形成一重氢与氢气掺杂层；提供一第二半导体衬底；在该第二半导体衬底的顶面形成一第二绝缘层；将该第一半导体衬底面对面地接合于该第二半导体衬底；对该第一半导体衬底以及该第二半导体衬底进行退火；以及将部分的第一半导体衬底与该第二半导体衬底分离，以便在该第二半导体衬底上形成一掺杂有重氢与氢气的半导体层。

Description

绝缘层上顶层硅衬底及其制造方法
技术领域
本发明有关于一种绝缘层上顶层硅衬底及其制造方法。
背景技术
近年来，已经有业界利用绝缘材料表面形成单晶半导体层的绝缘层上顶层硅(SOI)衬底来代替使用体硅晶圆于半导体集成电路的制造之中。因为使用SOI衬底的优点在于可以减少晶体管的漏极与衬底之间的寄生电容，藉此提高半导体集成电路的效能。
关于半导体器件的制造方法，例如美国公告专利第5374564号是由离子注入法对硅晶圆进行氢离子注入，并在预定深度处形成离子注入层。接下来，将植入有氢离子的硅晶圆与另一片硅晶圆接合，且于两片硅晶圆之间插置有氧化硅膜。之后，经过热处理，以离子注入层作为***面，且在植入有氢离子的硅晶圆以薄膜状分离。藉此可在接合的硅晶圆之上形成单晶硅层。例如美国公告专利第5872387号是由在重氢环境下对于已经生长好栅极氧化物的衬底进行退火，以便消除栅极氧化物与衬底之间的悬挂键(dangling bond)。然而此方法必须在很高的重氢环境气压进行，因而导致制造成本的提高。
因此，目前有需要一种改良的绝缘层上顶层硅衬底的制造方法，至少可改善上述的缺失。
发明内容
本发明提供一种绝缘层上顶层硅衬底及其制造方法，可以减少晶体管的漏极与衬底之间的寄生电容，以及降低制造成本。
依据本发明一实施例，提供一种绝缘层上顶层硅衬底的制造方法，包括：提供一第一半导体衬底；在该第一半导体衬底的顶面形成一第一绝缘层；对该第一半导体衬底进行离子束注入，以便在距离该第一绝缘层的顶面的预定深度处形成一重氢与氢气掺杂层；提供一第二半导体衬底；在该第二半导体衬底的顶面形成一第二绝缘层；将该第一半导体衬底面对面地接合于该第二半导体衬底；对该第一半导体衬底以及该第二半导体衬底进行退火；以及将部分的第一半导体衬底与该第二半导体衬底分离，以便在该第二半导体衬底之上形成一掺杂有重氢与氢气的半导体层。
所述的绝缘层上顶层硅衬底的制造方法，其中该第一半导体衬底包含IV族元素、SiGe、III-V族化合物、III族-氮化合物或II-V族化合物。
所述的绝缘层上顶层硅衬底的制造方法，其中该预定深度介于0.01um至5um。
所述的绝缘层上顶层硅衬底的制造方法，其中该离子束的注入能量介于1keV至200keV，而该离子束的掺杂剂量介于1016(离子个数/cm2)至2×1017(离子个数/cm2)。
所述的绝缘层上顶层硅衬底的制造方法，其中该第二半导体衬底包含IV族元素、SiGe、III-V族化合物、III族-氮化合物或II-V族化合物。
所述的绝缘层上顶层硅衬底的制造方法，其中该第一半导体衬底以及该第二半导体于介于摄氏200度～400度进行接合。
所述的绝缘层上顶层硅衬底的制造方法，其中该第一半导体衬底以及该第二半导体衬底进行接合的步骤更包括：润湿该第一绝缘层以及该第二绝缘层；将润湿后的该第一绝缘层与该第二绝缘层相互接触；以及施压于相互接触的该第一绝缘层以及该第二绝缘层，使得该第一绝缘层接合于该第二绝缘层上。
所述的绝缘层上顶层硅衬底的制造方法，其中该退火步骤更包括：先加热该第一半导体衬底以及该第二半导体衬底至摄氏600度～900度；接着冷却该第一半导体衬底以及该第二半导体衬底至摄氏400度～600度。
所述的绝缘层上顶层硅衬底的制造方法，其中冷却该第一半导体衬底以及该第二半导体衬底的时间介于30分钟～120分钟。
所述的绝缘层上顶层硅衬底的制造方法，其中该掺杂有重氢与氢气的半导体层的厚度介于50埃～50000埃。
所述的绝缘层上顶层硅衬底的制造方法，更包括该第一半导体衬底分离于该第二半导体衬底之后，再度加热该第二半导体衬底至摄氏10000度。
所述的绝缘层上顶层硅衬底的制造方法，其中加热该第二半导体衬底的时间介于30分钟～8小时。
依据本发明一实施例，提供一种绝缘层上顶层硅衬底，包括：一半导体衬底；一绝缘层，该绝缘层接合于该半导体衬底的顶面；以及一掺杂有重氢与氢气的半导体层，该掺杂有重氢与氢气的半导体层接合于该绝缘层的顶面。
所述的绝缘层上顶层硅衬底，其中该半导体衬底包含有IV族元素、SiGe、III-V族化合物、III族-氮化合物或II-V族化合物。
所述的绝缘层上顶层硅衬底，其中该掺杂有重氢与氢气的半导体层的厚度介于50埃～50000埃。
附图说明
图1为本发明提供的绝缘层上顶层硅衬底的制造方法的流程图。
图2A-2H为制造绝缘层上顶层硅衬底的剖视图。
具体实施方式
下面结合说明书附图和优选实施例对本发明作进一步的描述，但本发明的实施方式不限于此。
参阅图1，为提供一实施例的绝缘层上顶层硅衬底的制造方法，包括下列步骤：
S101：提供一第一半导体衬底
S102：在第一半导体衬底的顶面形成一第一绝缘层；
S103：以重氢与氢气为来源气体，对第一半导体衬底注入重氢与氢气离子束，以便在距离第一绝缘层的顶面的预定深度处形成一重氢与氢气掺杂层；
S104：提供一第二半导体衬底；
S105：在第二半导体衬底的顶面形成一第二绝缘层；
S106：将第一半导体衬底面对面地接合于该第二半导体衬底；
S107：对相互接合的第一半导体衬底与第二半导体衬底进行退火；
S108：将部分的第一半导体衬底与该第二半导体衬底分离；以及
S109：在第二半导体衬底上形成一掺杂有重氢与氢气的半导体层。
S110：回收利用分离后的第一半导体衬底。
为了更具体地阐述图1的绝缘层上顶层硅衬底的制造方法，请参照图2A-2G，为提供本发明一实施例所提供的制造绝缘层上顶层硅衬底的剖视图。
首先，参照图2A，制备一第一半导体衬底100，其中第一半导体衬底100的材料可包含IV族元素、SiGe、III-V族元素、III族-氮化合物或II-V族化合物。在本实施例中，第一半导体衬底100使用单晶硅。在其他实施例中，当第一半导体衬底100的材料为SiGe时，Ge的重量百分比介于5％～90％。
接下来，参照图2B，于该第一半导体衬底100的顶面102形成一第一绝缘层104，其中第一绝缘层104的材料可包含SiO2、SiN或AlN。在本实施例中，第一绝缘层104使用SiO2，且其厚度大约介于0.1nm～500nm。
接着，参照图2C，以重氢与氢气作为来源气体，透过电场作用而产生来源气体的等离子体，并从等离子体中取出包含在等离子体中的离子来予以生成来源气体的离子束，对第一半导体衬底100照射重氢与氢气离子束108，以便于距离第一绝缘层104的顶面110的预定深度H处形成一重氢与氢气掺杂层112，该预定深度H可藉由重氢与氢气离子束108的加速能量以及入射角来控制，至于加速能量可藉由注入能量以及掺杂剂量来控制。在本实施例中，预定深度H介于0.1um～5um，注入能量介于1keV～200keV，而氢离子束的掺杂剂量介于1016(离子个数/cm2)～2x1017(离子个数/cm2)。
下面，参照图2D，制备一第二半导体衬底200，其中第二半导体衬底200的材料可包含IV族元素、SiGe、III-V族化合物、III族-氮化合物或II-V族化合物。在本实施例中，第二半导体衬底200的材料为单晶硅。
接下来，参照图2E，于该第二半导体衬底200的顶面202形成一第二绝缘层204，其中该第二绝缘层204可包含SiO2、SiN或AlN。在本实施例中，第二绝缘层204使用SiO2，且其厚度大约介于0.05nm至10nm。
接着，参照图2F，将第一半导体衬底100面对面地接合(bonding)于第二半导体衬底200。在本实施例中，采用亲水性接合(hydrophilic bonding)的方式，接合时的温度介于摄氏200度～400度，其中接合的详细步骤更包括：首先湿润第一绝缘层104与第二绝缘层204；接着将湿润后的第一绝缘层104与第二绝缘层204相互接触；以及最后施压于第一绝缘层104与第二绝缘层204，使得第一绝缘层104与第二绝缘层204紧密地相互接合。
下面，参照图2G，对相互接合的第一半导体衬底100以及该第二半导体衬底200进行退火(annealing)，而退火的详细步骤包括：首先加热该第一半导体衬底100与第二半导体衬底200至摄氏600度～900度；接着，冷却第一半导体衬底100与第二半导体衬底200至摄氏400度～600度，而冷却时间大约30分钟～120分钟。经过退火后，原本相连的重氢与氢气掺杂层112会***为复数个相互间隔的重氢与氢气掺杂气泡区块300(Bubble formation)。
接着，参照图2H，将部分的第一半导体衬底100与该第二半导体衬底200分离，以便形成一包含有该些重氢与氢气掺杂气泡区块300的半导体层400于相互接合的第一绝缘层104与第二绝缘层204上。
值得一提的，分离后的第一半导体衬底100，更可进一步进行化学机械研磨(CMP)与清洗(clean)，使得分离后的第一半导体衬底100得以回收利用，达到节省成本的效果。至于接合有半导体层400的第二半导体衬底200可进行再度加热至摄氏10000度，而再度加热时间介于30分钟～8小时。
由于悬挂键(dangling bond)含有极高的活性，容易形成陷阱中心(trap center)，造成电子空穴对的再度结合，因而降低半导体器件对于热载流子效应的恢复力。藉由本发明所提供的绝缘层上顶层硅衬底来制造半导体器件，除了可以减少晶体管的漏极与衬底之间的寄生电容之外。将来于绝缘层上顶层硅衬底生长栅极氧化物时，掺杂于衬底内的重氢原子会向外扩散至栅极氧化物与该衬底之间的接口与半导体原子共价键结(covalently bound)，以便消除悬挂键而有效率地提升半导体器件对于热载流子效应(hot carrier effect)载流子的恢复力(resilience)。再者，由于不需要很高的重氢气压，制造成本大大降低。
以上所揭露的仅为本发明的优选实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明申请专利范围所作的等同变化，仍属本发明所涵盖的范围。

Claims (15)

1.一种绝缘层上顶层硅衬底的制造方法，包括：
提供一第一半导体衬底；
在该第一半导体衬底的顶面形成一第一绝缘层；
对该第一半导体衬底进行离子束注入，以便在距离该第一绝缘层的顶面的预定深度处形成一重氢与氢气掺杂层；
提供一第二半导体衬底；
在该第二半导体衬底的顶面形成一第二绝缘层；
将该第一半导体衬底面对面地接合于该第二半导体衬底；
对该第一半导体衬底以及该第二半导体衬底进行退火；以及
将部分的第一半导体衬底与该第二半导体衬底分离，以便在该第二半导体衬底上形成一掺杂有重氢与氢气的半导体层。
2.如权利要求1所述的绝缘层上顶层硅衬底的制造方法，其特征在于，该第一半导体衬底包含IV族元素、SiGe、III-V族化合物、III族-氮化合物或II-V族化合物。
3.如权利要求1所述的绝缘层上顶层硅衬底的制造方法，其特征在于，该预定深度介于0.1um至5um。
4.如权利要求1所述的绝缘层上顶层硅衬底的制造方法，其特征在于，该离子束的注入能量介于1keV至200keV，而该离子束之掺杂剂量介于1016(离子个数/cm2)至2x1017(离子个数/cm2)。
5.如权利要求1所述的绝缘层上顶层硅衬底的制造方法，其特征在于，该第二半导体衬底包含IV族元素、SiGe、III-V族化合物、III族-氮化合物或II-V族化合物。
6.如权利要求1所述的绝缘层上顶层硅衬底的制造方法，其特征在于，该第一半导体衬底以及该第二半导体衬底在介于摄氏200度～400度面对面地进行接合。
7.如权利要求1所述的绝缘层上顶层硅衬底的制造方法，其特征在于，该第一半导体衬底以及该第二半导体衬底面对面地接合的步骤更包括：润湿该第一绝缘层以及该第二绝缘层；将润湿后的该第一绝缘层与该第二绝缘层相互接触；以及施压于相互接触的该第一绝缘层以及该第二绝缘层，使得该第一绝缘层接合于该第二绝缘层上。
8.如权利要求1所述的绝缘层上顶层硅衬底的制造方法，其特征在于，该退火步骤更包括：先加热该第一半导体衬底以及该第二半导体衬底至摄氏600度～900度；接着冷却该第一半导体衬底以及该第二半导体衬底至摄氏400度～600度。
9.如权利要求8所述的绝缘层上顶层硅衬底的制造方法，其特征在于，冷却该第一半导体衬底以及该第二半导体衬底的时间介于30分钟～120分钟。
10.如权利要求1所述的绝缘层上顶层硅衬底的制造方法，其特征在于，该掺杂有重氢的半导体层的厚度介于50埃～50000埃。
11.如权利要求1所述的绝缘层上顶层硅衬底的制造方法，其特征在于，更包括该第一半导体衬底分离于该第二半导体衬底之后，再度加热该第二半导体衬底至摄氏10000度。
12.如权利要求11所述的绝缘层上顶层硅衬底的制造方法，其特征在于，再度加热该第二半导体衬底之时间介于30分钟～8小时。
13.一种绝缘层上顶层硅衬底，包括：
一半导体衬底；
一绝缘层，该绝缘层接合于该半导体衬底的顶面；以及
一掺杂有重氢与氢气的半导体层，该掺杂有重氢与氢气的半导体层接合于该绝缘层的顶面。
14.如权利要求13所述的绝缘层上顶层硅衬底，其特征在于，该半导体衬底包含有IV族元素、SiGe、III-V族化合物、III族-氮化合物或II-V族化合物。
15.如权利要求13所述的绝缘层上顶层硅衬底，其特征在于，该掺杂有重氢与氢气的半导体层的厚度介于50埃～50000埃。
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