CN107133185B - Method and mainboard for realizing hot plug function of PCIE (peripheral component interface express) equipment through BIOS (basic input output System) - Google Patents
Method and mainboard for realizing hot plug function of PCIE (peripheral component interface express) equipment through BIOS (basic input output System) Download PDFInfo
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- CN107133185B CN107133185B CN201710258176.0A CN201710258176A CN107133185B CN 107133185 B CN107133185 B CN 107133185B CN 201710258176 A CN201710258176 A CN 201710258176A CN 107133185 B CN107133185 B CN 107133185B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4081—Live connection to bus, e.g. hot-plugging
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- G—PHYSICS
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- G06F2213/0026—PCI express
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Abstract
The invention provides a method and a mainboard for realizing the hot plug function of PCIE equipment through BIOS, wherein the method realizes the hot plug function of the PCIE equipment in Non-ACPI environment through simple hardware circuit and BIOS program design, makes up the function loss in the environment and basically does not increase the hardware cost. And the single GPIO is connected with the light emitting diode to finish communication with an operator, so that misoperation is avoided. In the aspect of memory resources, resources do not need to be reserved in advance, and after the equipment is inserted, the resources are acquired and allocated to the equipment, so that the utilization rate of the memory resources is increased. In the resource allocation process, the resources cannot be reallocated to other equipment, the use of the other equipment is interrupted, the influence of plugging and unplugging equipment on the system is reduced to the maximum extent, and when the detection equipment is inserted in a hot mode, double-in-place pin angle detection is adopted, and button prompting is not needed.
Description
Technical Field
The invention belongs to the technical field of computers, and particularly relates to a method and a mainboard for realizing a hot plug function of PCIE (peripheral component interface express) equipment through a BIOS (basic input output System).
Background
In the mainboard field, the current mainstream peripheral equipment comprises USB interface equipment, SATA interface equipment, PCIE interface equipment and the like, no matter in the mainboard starting process or under various different types of systems, the USB and SATA interface equipment can be subjected to hot plug-in and hot plug-out at will, the plug-and-play function is realized, and the user operation is very convenient. However, the main motherboard in the market is not designed with the function of hot plugging of PCIE devices, and the PCIE devices need to be plugged and replaced only in a state where the motherboard is turned off. In the prior art, the hot plug function of the PCIE device can be already realized through hardware design, BIOS program design, and operating system support. In hardware, a hot plug controller, a power indicator, a prompt button and the like are required to be added, and a card slot power supply switching logic circuit and a board card resetting logic circuit are required to be designed; the firmware BIOS is to provide software support; the operating system needs to provide functional components required for supporting the hot plug of the PCIE device, including user operation interface software, a hot plug service program, a standard hot plug system driver, and a device driver, and the hardware cost in the process of implementing the whole function is increased, and the implementation is also complicated, so that the main stream motherboard does not implement the hot plug function of the PCIE device.
At present, a main stream mainboard does not realize a hot plug function of a PCIE device, and the function can be realized through the cooperation of hardware, a BIOS and an operating system, but even if the function is realized, the hot plug operation can only be completed under an ACPI operating system, the hot plug operation cannot be performed in a BIOS running phase during a boot process, a Non-ACPI system (for example, a DOS system) cannot perform the hot plug operation, on one hand, the hot plug function of the PCIE device is missing under these Non-ACPI environments and cannot meet an operation requirement, on the other hand, an operator may mistakenly consider that all environments support the hot plug function of the PCIE device, and the hot plug operation is performed before entering the ACPI operating system, resulting in a false operation.
Disclosure of Invention
Aiming at the technical problems, the invention discloses a method and a mainboard for realizing the hot plug function of PCIE equipment through BIOS, which can effectively support the hot plug function of the PCIE equipment under the Non-ACPI environment, make up the function loss under the Non-ACPI environment and meet the requirements of operators; and the hardware circuit is simple in design, the cost of the mainboard cannot be increased, and the development and debugging time cannot be increased.
In contrast, the technical scheme adopted by the invention is as follows:
a method for realizing hot plug function of PCIE equipment through BIOS, the mainboard includes PCH and BIOS basic input and output module connected with it; the PCH comprises GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6 and GPIO7, and the GPIO1, the GPIO2 and the GPIO3 are electrically connected with the PCIE slot respectively; the GPIO1 is connected with a 3.3V auxiliary power supply through a resistor R1, and the GPIO1 is simultaneously grounded through a resistor R2; the GPIO2 is connected with a 3.3V power supply through a resistor R5, and the GPIO2 is simultaneously grounded through a resistor R6; the GPIO3 is connected with a 12V power supply through a resistor R7, and the GPIO3 is simultaneously grounded through a resistor R8; the GPIO4 is electrically connected with a hot plug detection signal PRSNT1# of the PCIE slot; GPIO5 is connected with hot plug detection signal PRSNT2#, and GPIO6 is connected with emitting diode and is grounded through resistance R3, and GPIO7 is connected with the 3.3V power through resistance R4, and is grounded through the button.
As a further improvement of the present invention, the BIOS basic input/output module sets GPIO1, GPIO2, GPIO3, GPIO6, GPIO7 to be GPIO output functions; the BIOS basic input/output module sets GPIO4 and GPIO5 as GPIO input functions.
As a further improvement of the present invention, in a hot-plug stage of a PCIE device, the BIOS basic input output module is controlled by the following steps:
step S101, running a BIOS program, carrying out GPIO initialization, setting GPIO1, GPIO2, GPIO3 and GPIO6 as GPIO output functions, outputting low level, turning off a PCIE slot power supply, and turning off a light emitting diode;
step S102, setting GPIO4, GPIO5 and GPIO7 as input functions, turning on GPIO4 and GPIO7 to trigger SMI interrupt function, and then enabling the BIOS program to enter Non-ACPI environment;
including BIOS run procedures after GPIO initialization, DOS systems, etc.
Step S103, in a Non-ACPI environment, if a PCIE device is inserted into a PCIE slot, pulling down a GPIO5 without triggering an interrupt program, and pulling down a GPIO4 to trigger an SMI interrupt program;
step S104, the interrupt program firstly checks whether the GPIO5 is at low level, if not, the interrupt program does not process the low level, which indicates that the GPIO is pulled down due to poor contact of the device or other reasons; if the GPIO5 is low, it indicates that GPIO4 and GPIO5 are both pulled low and that there is a device inserted into the slot and the contact is good; the SMI interrupt program sets the GPIO6 to be square wave output, and the light emitting diode flickers to remind an operator that the equipment cannot be pulled out;
step S105, setting GPIO1, GPIO2 and GPIO3 as high-level output, opening a 3.3V auxiliary power supply, a 3.3V power supply and a 12V power supply of a PCIE slot, then reading a parent bridge of the slot device, distributing Bus number resources for the device, and waiting for the end of the PCIE device and the parent bridge link tracing; and after the link tracing is finished, allocating memory resources and IO resources for the PCIE equipment, and allocating interrupts for the equipment.
As a further improvement of the present invention, in step S105, after the link tracing is finished, it is checked whether there is enough resource in the MMIO resources to allocate to the PCIE device, if there is resource, according to the base address calculation, memory resource and IO resource are allocated to the PCIE device, and the allocation of the device is interrupted; if no resource exists, firstly modifying a top register of a TOLM low memory, reducing the value, increasing the size of MMIO, then setting an MMIO rule register to explain the size of MMIO, modifying an MTRR (memory type range register) register, setting a newly-added MMIO as a non-bufferable type, then updating an E820 table to explain the current use conditions of all types of memory, then redistributing the memory, IO and interrupt resources, and after the resources are distributed, opening switches of the memory and the IO resources to enable the resources to be in a usable state.
As a further improvement of the present invention, step S106 is further included, which sets GPIO6 to be a high level output, so that the light emitting diode is normally on, indicating that the device can operate normally.
As a further improvement of the present invention, in a hot-plug stage of a PCIE device, the BIOS basic input/output module is controlled by the following steps:
step S201, initializing GPIO1, GPIO2, GPIO3 and GPIO6 to output low level, and extinguishing the light emitting diode; then GPIO4, GPIO5 and GPIO7 are set as input functions, GPIO4 and GPIO7 are turned on to trigger an SMI interrupt function, and then a BIOS program enters a Non-ACPI environment; including BIOS run procedures after GPIO initialization, DOS systems, etc.
Step S202, the GPIO7 inputs high level all the time, if the operator has the requirement of pulling out the PCIE equipment, the operator firstly presses down the key to make the GPIO7 generate low level to trigger the SMI interrupt program;
step S204, the BIOS program prohibits the memory and IO space through the command register of the device, prohibits the link with the PCIE device in the parent bridge, sets GPIO1, GPIO2, and GPIO3 to output low levels, turns off the power supply of the PCIE slot, and releases the memory, IO, and interrupt resources required by the PCIE device.
The released memory resources are not used by the system, still retain MMIO attributes, and are convenient to preferentially allocate the resources when the device is inserted again.
As a further improvement of the present invention, step S203 is further included, during starting of the SMI interrupt program, the GPIO6 is first set to output a square wave, so that the light emitting diode flashes to remind an operator that the device cannot be pulled out.
As a further improvement of the present invention, step S205 is further included, which sets GPIO6 to low level to make the led go out, indicating that the device can be safely removed.
As a further improvement of the invention, the GPIO4, the GPIO5 and the GPIO6 are connected with a 3.3V power supply.
The invention also discloses a mainboard for realizing the hot plug of the PCIE equipment in the BIOS stage, which adopts the method for realizing the hot plug function of the PCIE equipment through the BIOS.
Compared with the prior art, the invention has the beneficial effects that:
by adopting the technical scheme of the invention, the hot plug function of the PCIE equipment in the Non-ACPI environment is realized, the loss of the function in the environment is made up, and the hardware cost is not increased basically. The single GPIO is connected with the light emitting diode, so that communication with an operator is completed, and misoperation is avoided. In the aspect of memory resources, resources do not need to be reserved in advance, and after the equipment is inserted, the resources are acquired and allocated to the equipment, so that the utilization rate of the memory resources is increased. In the resource allocation process, the resources cannot be reallocated to other equipment, the use of the other equipment is interrupted, the influence of plugging and unplugging equipment on the system is reduced to the maximum extent, and when the detection equipment is inserted in a hot mode, double-in-place pin angle detection is adopted, and button prompting is not needed.
Drawings
Fig. 1 is a schematic diagram of a hardware connection structure according to an embodiment of the present invention.
Fig. 2 is a flowchart of a method for hot plug of a PCIE device according to an embodiment of the present invention.
Fig. 3 is a flowchart of a method when a PCIE device is hot-unplugged according to an embodiment of the present invention.
Detailed Description
Preferred embodiments of the present invention are described in further detail below.
A method for realizing hot plug function of PCIE equipment through BIOS comprises a hardware circuit design part and a BIOS program design part.
The hardware circuit design part is as follows:
as shown in fig. 1, in hardware, it is mainly the design of the lines between the GPIOs of the PCH and the PCIE slot. GPIO1, GPIO2, and GPIO3 of PCH are all set to GPIO output functions, GPIO1 connects 3.3V auxiliary power (3.3 VAux) to the PCIE slot through R1 and R2 resistors, GPIO2 connects 3.3V power to the PCIE slot through resistors R5 and R6, GPIO3 connects 12V power to the PCIE slot through resistors R7 and R8, GPIO4 and GPIO5 are set to GPIO input functions, GPIO4 is connected to hot plug detect signal PRSNT1#, GPIO5 is connected to hot plug detect signal PRSNT2#, GPIO6 is set to GPIO output functions, GPIO light emitting diodes are connected to ground through resistor R3, GPIO7 is set to GPIO input functions, 3.3V power connection resistor R4, resistor R4 is connected to both 7 and key ground.
The following is a PCIE device hot-plug operation.
An operator inserts PCIE equipment into a PCIE slot in a hot mode, signals PRSNT1# and PRSNT2# are pulled down at the same time, low level signals are input into a PCH through GPIO4 and GPIO5 to generate SMI interruption, a BIOS interruption program is operated, the BIOS program sets a photodiode to be in a flashing state to remind the operator of not pulling out the PCIE equipment at the moment, then the BIOS sets GPIO1, GPIO2 and GPIO3 to be high level output, a 12V power supply, a 3.3V power supply and a 3.3V auxiliary power supply power for the PCIE slot, the BIOS waits for the initialization of the equipment to be completed, after the initialization is completed, the BIOS sets a light emitting diode to be in a normally-on state to remind the operator of the fact that the PCIE equipment has been initialized to be completed, and the PC. Here, the insertion state of the device is judged by simultaneously pulling down two signals, namely PRSNT1# and PRSNT2#, so that the situation that a single signal is pulled down and the access state of the device is misreported due to poor contact or other misoperation of the PCIE device is prevented.
The following is the PCIE device hot removal operation.
An operator presses a key to generate a low level signal, the low level signal is input into the PCH through the GPIO7 to generate an SMI interrupt, a BIOS interrupt program is operated, the BIOS program sets the photodiode to be in a flashing state to remind the operator, the PCIE equipment is not pulled out at the moment until the BIOS program completes related setting, GPIO1\2\3 is set to be output low level, the power supply of the slot is closed, the memory, IO and interrupt resources required by the equipment are released, and finally, the GPIO6 is set to be low level to extinguish the light emitting diode, which indicates that the equipment can be safely removed at the moment.
The BIOS programming part is as follows:
designing a hot plug program of the PCIE equipment:
as shown in fig. 2, the BIOS program starts to run, and first, GPIO initialization is performed, GPIO1\2\3\6 is set as a GPIO output function, a low level is output, the PCIE slot power is turned off, the light emitting diode is turned off, GPIO4\5\7 is set as an input function, GPIO4\7 is turned on to trigger an SMI interrupt function, and then the BIOS program enters a Non-ACPI environment, including a BIOS running process, a DOS system, and the like after GPIO initialization. In the Non-ACPI environment, if a PCIE device is inserted into a slot, the GPIO5 will be pulled low, but the interrupt routine will not be triggered, and the GPIO4 will be pulled low, triggering the SMI interrupt routine. The interrupt program firstly checks whether the GPIO5 is low level, if not, the interrupt program does not process the low level, which indicates that the GPIO is pulled down due to poor contact of the device or other reasons, and if the interrupt program is low level, which indicates that all GPIOs 4\5 are pulled down, a device is inserted into the slot and the contact is good. The interrupt program sets GPIO6 as square wave output to make the LED flash to remind the operator that the device can not be pulled out, then sets GPIO1\2\3 as high level output, turns on the 3.3V auxiliary power supply, the 3.3V power supply and the 12V power supply of the PCIE slot, then reads the parent bridge of the slot device, allocates Bus number resources for the device, waits for the PCIE device and the parent bridge linking ending, checks whether enough resources are allocated to the PCIE device in the MMIO resources after the linking ends, if resources exist, allocates memory resources and IO resources for the device according to the base address calculation, allocates interrupt for the device, if no resources exist, firstly modifies TOMMIO (low memory top register), reduces the value, increases the size of MMIO, then sets up MMIO (memory type range register) register to explain the size of MMIO, modifies MTRR (memory type range register) register, sets up the newly added MMIO as non-bufferable type, and then updating the E820 table to show the current use conditions of all types of the memories, then reallocating the memories, the IOs and the interrupt resources, and after the resources are allocated, opening switches of the memories and the IO resources to enable the resources to be in a usable state. Finally, the GPIO6 is set to a high level output to keep the led on, indicating that the device is functioning properly.
Designing a hot-plug program of the PCIE equipment:
like the hot plug-in program, as shown in fig. 3, the GPIO1\2\3\6 is initialized to be set to output low-point level, the light emitting diode is turned off, then the GPIO4\5\7 is set as an input function, the GPIO4\7 is turned on to trigger an SMI interrupt function, and then the BIOS program enters a Non-ACPI environment, including a BIOS running process, a DOS system and the like after the GPIO is initialized. The GPIO7 always inputs a high level, and if an operator needs to pull out a PCIE device, the prompt button is first pressed, so that the GPIO7 generates a low level, which triggers an SMI interrupt routine. In an interrupt program, firstly, the GPIO6 is set to output square waves, so that the light emitting diode flickers to remind an operator that the device cannot be pulled out, then the program prohibits the memory and IO space through a command register of the device, then the linkage with the device is prohibited in a parent bridge, the GPIO1\2\3 is set to output low level, a power supply of a slot is closed, the memory, the IO and interrupt resources required by the device are released, and finally the GPIO6 is set to low level to extinguish the light emitting diode, which indicates that the device can be safely removed at this time. The released memory resources are not used by the system, still retain MMIO attributes, and are convenient to preferentially allocate the resources when the device is inserted again.
The method can effectively support the hot plug function of the PCIE equipment in the Non-ACPI environment through simple hardware circuit design and BIOS program design, makes up the function loss in the Non-ACPI environment and meets the requirements of operators. And the hardware circuit is simple in design, the cost of the mainboard cannot be increased, and the development and debugging time cannot be increased.
The invention relates to the technical term explanation of English abbreviation:
BIOS (basic Input Output System): the basic input and output system is mainly used for initializing and detecting various hardware devices in the starting process of a computer.
Pch (platform Controller hub): intel corporation integrated south bridge.
PCIE (PCI-Express): a high-speed serial bus interface technology standard.
GPIO (general Purpose Input output): general purpose input/output.
ACPI (advanced Configuration and Power Management interface): advanced configuration and power management interfaces, operating system applications manage all power management interfaces, Non-ACPI environment, i.e. environment that does not support the ACPI standard.
Usb (universal Serial bus): a universal serial bus.
Sata (serial Advanced Technology attachment): serial ATA interface specification.
Dos (disk Operating system): a disk operating system.
SMI (System Management interrupt): a system management interrupt.
MMIO (Memory mapping I/O): memory mapped I/O.
TOLM (Top of Low memory): low memory top.
Mtrr (memory Type Range registers): a memory type range register.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (7)
1. The method for realizing the hot plug function of the PCIE equipment through the BIOS is characterized in that: the mainboard comprises a PCH and a BIOS basic input and output module connected with the PCH; the PCH comprises GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6 and GPIO7, and the GPIO1, the GPIO2 and the GPIO3 are electrically connected with the PCIE slot respectively; the GPIO1 is connected with a 3.3V auxiliary power supply through a resistor R1, and the GPIO1 is simultaneously grounded through a resistor R2; the GPIO2 is connected with a 3.3V power supply through a resistor R5, and the GPIO2 is simultaneously grounded through a resistor R6; the GPIO3 is connected with a 12V power supply through a resistor R7, and the GPIO3 is simultaneously grounded through a resistor R8; the GPIO4 is electrically connected with a hot plug detection signal PRSNT1# of the PCIE slot; GPIO5 is electrically connected with hot plug detection signal PRSNT2#, GPIO6 is connected with the LED and then grounded through resistor R3, GPIO7 is connected with 3.3V power supply through resistor R4 and grounded through keys;
the BIOS basic input and output module sets GPIO1, GPIO2, GPIO3, GPIO6 and GPIO7 as GPIO output functions; the BIOS basic input/output module sets GPIO4 and GPIO5 as GPIO input functions;
in a hot-plug stage of the PCIE device, the BIOS basic input output module performs control by using the following steps:
step S101, running a BIOS program, carrying out GPIO initialization, setting GPIO1, GPIO2, GPIO3 and GPIO6 as GPIO output functions, outputting low level, turning off a PCIE slot power supply, and turning off a light emitting diode;
step S102, setting GPIO4, GPIO5 and GPIO7 as input functions, turning on GPIO4 and GPIO7 to trigger SMI interrupt function, and then enabling the BIOS program to enter Non-ACPI environment;
step S103, in a Non-ACPI environment, if a PCIE device is inserted into a PCIE slot, pulling down a GPIO5 without triggering an interrupt program, and pulling down a GPIO4 to trigger an SMI interrupt program;
step S104, the interrupt program firstly checks whether the GPIO5 is at low level, if not, the interrupt program does not process; if GPIO5 is low, it indicates that a device is plugged into the slot and makes good contact; the SMI interrupt program sets the GPIO6 to be square wave output, and the light emitting diode flickers to remind an operator that the equipment cannot be pulled out;
step S105, setting GPIO1, GPIO2 and GPIO3 as high-level output, opening a 3.3V auxiliary power supply, a 3.3V power supply and a 12V power supply of a PCIE slot, then reading a parent bridge of the slot device, distributing Bus number resources for the device, and waiting for the end of the PCIE device and the parent bridge link tracing; after link tracing is finished, allocating memory resources and IO resources for PCIE equipment, and allocating interruption for the equipment;
in a hot-plug stage of the PCIE device, the BIOS basic input/output module performs control by using the following steps:
step S201, initializing GPIO1, GPIO2, GPIO3 and GPIO6 to output low level, and extinguishing the light emitting diode; then GPIO4, GPIO5 and GPIO7 are set as input functions, GPIO4 and GPIO7 are turned on to trigger an SMI interrupt function, and then a BIOS program enters a Non-ACPI environment;
step S202, the GPIO7 inputs high level all the time, if the operator has the requirement of pulling out the PCIE equipment, the operator firstly presses down the key to make the GPIO7 generate low level to trigger the SMI interrupt program;
step S204, the BIOS program prohibits the memory and IO space through the command register of the device, prohibits the link with the PCIE device in the parent bridge, sets GPIO1, GPIO2, and GPIO3 to output low levels, turns off the power supply of the PCIE slot, and releases the memory, IO, and interrupt resources required by the PCIE device.
2. The method of claim 1, wherein the method further comprises: in step S105, after link tracing is finished, checking whether there is enough resource in MMIO resources to allocate to PCIE devices, if there is resource, calculating according to a base address, allocating memory resource and IO resource to PCIE devices, and allocating interrupts to devices; if no resource exists, firstly modifying a top register of a TOLM low memory, reducing the value, increasing the size of MMIO, then setting an MMIO rule register to explain the size of MMIO, modifying an MTRR register, setting a newly-added MMIO as a non-bufferable type, then updating an E820 table to explain the use conditions of all types of the current memory, then redistributing the memory, IO and interrupting the resource, and after the resource is distributed, opening switches of the memory and the IO resource to enable the resource to be in a usable state.
3. The method of claim 2, wherein the method further comprises: step S106 is further included to set GPIO6 to high output to make the led light normally on, indicating that the device is working properly.
4. The method of claim 1, wherein the method further comprises: and step S203, in the starting of the SMI interrupt program, the GPIO6 is firstly set to output square waves, so that the light emitting diode flickers to remind an operator that the equipment cannot be pulled out.
5. The method of claim 4, wherein the method comprises:
step S205 is also included to set GPIO6 low to turn off the leds, indicating that the device can be safely removed.
6. The method of claim 1, wherein the method further comprises: the GPIO4, the GPIO5 and the GPIO6 are connected with a 3.3V power supply.
7. A mainboard for realizing hot plug of PCIE equipment in BIOS stage is characterized in that: the method for realizing the hot plug function of the PCIE equipment through the BIOS in any one of claims 1 to 6 is adopted.
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| CN107678997B (en) * | 2017-09-27 | 2021-06-29 | 郑州云海信息技术有限公司 | Hot plug method, system, device and readable storage medium of PCIE (peripheral component interface express) card |
| CN107957968A (en) * | 2018-01-19 | 2018-04-24 | 郑州云海信息技术有限公司 | A kind of hot plug treating method and apparatus |
| CN108170621A (en) * | 2018-01-19 | 2018-06-15 | 郑州云海信息技术有限公司 | A kind of hot plug treating method and apparatus |
| CN110581869B (en) * | 2018-06-07 | 2022-04-08 | 中兴通讯股份有限公司 | Resource allocation method, TLP packet processing method, equipment and storage medium |
| CN109324991B (en) * | 2018-09-21 | 2021-12-03 | 郑州云海信息技术有限公司 | Hot plug device, method, medium and system of PCIE (peripheral component interface express) equipment |
| CN109358906A (en) * | 2018-09-26 | 2019-02-19 | 郑州云海信息技术有限公司 | It is a kind of to enable the method and system that BIOS serial ports redirects by setting BMC OEM order |
| CN109669905B (en) * | 2018-12-17 | 2023-05-12 | 广东浪潮大数据研究有限公司 | PCIE equipment heat removal method, system and related device |
| CN110399217B (en) * | 2019-06-27 | 2022-02-18 | 苏州浪潮智能科技有限公司 | Memory resource allocation method, device and equipment |
| CN113032148B (en) * | 2021-03-24 | 2023-07-18 | 山东英信计算机技术有限公司 | MMIO resource setting method and related device |
| CN114050714B (en) * | 2022-01-13 | 2022-04-22 | 苏州浪潮智能科技有限公司 | Method, circuit, device and medium for protecting PCIE (peripheral component interface express) card power supply |
| CN117971504B (en) * | 2024-03-29 | 2024-07-02 | 井芯微电子技术(天津)有限公司 | Fault switching Bus resource allocation method, system and device |
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2017
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