CN107123599A - Vacuum annealing method based on two-dimentional telluride gallium material FET - Google Patents
Vacuum annealing method based on two-dimentional telluride gallium material FET Download PDFInfo
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- CN107123599A CN107123599A CN201710235701.7A CN201710235701A CN107123599A CN 107123599 A CN107123599 A CN 107123599A CN 201710235701 A CN201710235701 A CN 201710235701A CN 107123599 A CN107123599 A CN 107123599A
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- 239000000463 material Substances 0.000 title claims abstract description 59
- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000000137 annealing Methods 0.000 title claims abstract description 23
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 title claims abstract description 8
- 229910052733 gallium Inorganic materials 0.000 title claims abstract description 8
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 title claims abstract description 8
- 238000005516 engineering process Methods 0.000 claims abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 33
- 239000002390 adhesive tape Substances 0.000 claims description 31
- 239000004205 dimethyl polysiloxane Substances 0.000 claims description 25
- 235000013870 dimethyl polysiloxane Nutrition 0.000 claims description 25
- CXQXSVUQTKDNFP-UHFFFAOYSA-N octamethyltrisiloxane Chemical compound C[Si](C)(C)O[Si](C)(C)O[Si](C)(C)C CXQXSVUQTKDNFP-UHFFFAOYSA-N 0.000 claims description 25
- 238000004987 plasma desorption mass spectroscopy Methods 0.000 claims description 25
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 claims description 25
- 239000000377 silicon dioxide Substances 0.000 claims description 17
- 241000446313 Lamella Species 0.000 claims description 10
- 238000007789 sealing Methods 0.000 claims description 10
- 238000000926 separation method Methods 0.000 claims description 8
- 229910052681 coesite Inorganic materials 0.000 claims description 6
- 229910052906 cristobalite Inorganic materials 0.000 claims description 6
- 229910052682 stishovite Inorganic materials 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 229910052905 tridymite Inorganic materials 0.000 claims description 6
- 229920000742 Cotton Polymers 0.000 claims description 5
- 238000004026 adhesive bonding Methods 0.000 claims description 5
- 238000003776 cleavage reaction Methods 0.000 claims description 5
- 238000005088 metallography Methods 0.000 claims description 5
- 230000007017 scission Effects 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 9
- 239000002184 metal Substances 0.000 abstract description 9
- 238000010276 construction Methods 0.000 abstract description 3
- 239000007789 gas Substances 0.000 abstract description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 abstract description 2
- 238000010521 absorption reaction Methods 0.000 abstract description 2
- 230000007850 degeneration Effects 0.000 abstract description 2
- 230000000704 physical effect Effects 0.000 abstract description 2
- 238000002360 preparation method Methods 0.000 abstract description 2
- 208000036829 Device dislocation Diseases 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000011513 prestressed concrete Substances 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/477—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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Abstract
The invention discloses a kind of vacuum annealing method based on two-dimentional telluride gallium material FET, the low technical problem of the mobility based on two-dimentional GaTe materials FET for solving existing method preparation.Technical scheme is on the basis of existing two-dimentional GaTe FETs construction technology, to introduce high vacuum annealing process (10‑ 5Pa).Because Gas Molecular Density is extremely low under high vacuum environment, absorption is promoted to be spread on channel material surface and channel material and oxygen molecule, the hydrone of metal electrode interface into environment, the scattering of the degeneration and surface adsorbed molecules of the intrinsic physical property of channel material caused by chemisorbed to carrier is effectively prevented, the mobility of two-dimentional GaTe FETs is effectively improved.After tested, the mobility based on two-dimentional GaTe materials FET for preparing of the present invention by background technology 0.2cm2V‑1s‑1Improve to 3.4 4.5cm2V‑1s‑1。
Description
Technical field
The present invention relates to a kind of method for annealing based on two-dimentional telluride gallium (GaTe) material devices, more particularly to one kind is based on
The vacuum annealing method of two-dimentional telluride gallium material FET.
Background technology
" Liu F, Shimotani H, Shang H, the et al.High-sensitivity photodetectors of document 1
based on multilayer GaTe flakes[J].ACS Nano,2014,8(1):752-760. " disclose one kind and be based on
The method that two-dimentional GaTe materials prepared by micromechanics stripping method construct FET, this method is based on block GaTe materials, uses
Think high adhesive tape and prepare two dimension GaTe materials, transfer them to SiO2After/Si substrate surfaces, then photoetching and hot evaporation method is used to enter
It is prepared by row electrode.Device mobility is 0.2cm in the air reported in the document2V-1s-1。
Although the document is successfully prepared the FET based on two-dimentional GaTe materials, but its device mobility is relatively low, still
The preparation requirement of high mobility two dimension GaTe FETs can not be met.
The content of the invention
In order to overcome the shortcomings of that the mobility based on two-dimentional GaTe materials FET prepared by existing method is low, the present invention
A kind of vacuum annealing method based on two-dimentional telluride gallium material FET is provided.This method is in existing two-dimentional GaTe FETs
On the basis of construction technology, after device constructs end, supplement introduces high vacuum annealing process (10-5Pa, 150 DEG C -200 DEG C),
The gas molecule adsorbed between channel material surface and channel material and metal electrode is removed, dissipating for surface adsorbed molecules is reduced
The effect of penetrating, promotes effectively contacting between channel material and electrode, can improve the mobility of device.
The technical solution adopted for the present invention to solve the technical problems：It is a kind of based on two-dimentional telluride gallium material FET
Vacuum annealing method, is characterized in comprising the following steps：
Step 1: using traditional photoetching-metallization-stripping technology, in clean 10mm × 10mm 300nm SiO2/
Si substrate surfaces prepare the grid, source electrode and drain electrode of FET, and wherein grid, source electrode and the material of drain electrode is 5nm Ti/
30nm Au, channel width is 2 μm -10 μm.
Step 2: choosing the GaTe materials of the smooth corrugationless in surface, and along natural cleavage plane GaTe materials are separated into many
Block.
Step 3: the use of think high adhesive tape to tear off one piece of thickness from GaTe block materials surface being 6-8 μm of GaTe thin slices.
Step 4: the high adhesive tape of think of with GaTe thin slices is repeatedly bonded into separation, until tape surface is no longer bright, success
The GaTe lamellas of hundreds of nanometers intensive of thickness of attachment.In order to protect GaTe material even curfaces, GaTe tables should be made during stripping
Face is fully contacted with thinking high tape surface.Think when high adhesive tape is separated, it is necessary to which one direction is slowly carried out.
Step 5: by the high adhesive tape gluing of think of with GaTe lamellas on the PDMS film surface that thickness is 0.5 ± 0.03mm,
And the high tape surface of think of is uniformly pressed with cotton swab makes the high adhesive tape of think of fully be fitted with PDMS.High adhesive tape and PDMS points will be thought rapidly again
From.
Step 6: using metallography microscope sem observation PDMS surfaces, choose two-dimentional GaTe materials in uniform thickness and taken pictures,
And write down position of the two-dimentional GaTe materials on PDMS surfaces.
Step 7: by the two-dimentional GaTe materials of mark by snapping into 300nm SiO to quasi- transfer platform2/ Si surfaces
Between source electrode and drain electrode.
Step 8: being put into the two-dimentional GaTe FETs that finish are constructed in the silica crucible that internal diameter is 15 ± 1mm, and make
10 will be evacuated to vacuum pump assembly in silica crucible-5Pa magnitudes, and silica crucible mouthful is baked into real sealing with oxyhydrogen flame.
100-140 minutes are incubated Step 9: the silica crucible after sealing is placed in 150 DEG C of -200 DEG C of cycle annealing stoves,
Then cooled down in atmosphere, complete annealing process.
The beneficial effects of the invention are as follows：This method is introduced on the basis of existing two-dimentional GaTe FETs construction technology
High vacuum annealing process (10-5Pa, 150 DEG C -200 DEG C).Because Gas Molecular Density is extremely low under high vacuum environment, promote absorption
Spread on channel material surface and channel material and oxygen molecule, the hydrone of metal electrode interface into environment, effectively
The scattering of the degeneration and surface adsorbed molecules of the intrinsic physical property of channel material caused by chemisorbed to carrier is prevented, can
The mobility of two-dimentional GaTe FETs is effectively improved, and holding stage accelerates the progress of this process；On the other hand move back
Fire environment temperature is higher, promotes the counterdiffusion between the metallic atom in metal electrode and two dimension GaTe materials, makes metal electricity
Pole forms with two dimension GaTe edge of materials and more effectively contacted, and can significantly reduce the contact gesture between material and metal electrode
Build.After tested, the mobility based on two-dimentional GaTe materials FET for preparing of the present invention by background technology 0.2cm2V-1s-1
Improve to 3.4-4.5cm2V-1s-1, success rate is 60%-90%.
The present invention is elaborated with reference to the accompanying drawings and detailed description.
Brief description of the drawings
Fig. 1 is the temperature control line chart of two dimension GaTe FET annealing process in the inventive method embodiment 2.
Fig. 2 is the output characteristics and transfer characteristic curve figure of two dimension GaTe FETs in the inventive method embodiment 2.
Embodiment
Following examples reference picture 1-2.
Embodiment 1：
The first step, using traditional photoetching-metallization-stripping technology, in clean 10mm × 10mm 300nm SiO2/
Si substrate surfaces prepare the grid, source electrode, drain electrode of FET, and wherein electrode material is 5nm Ti/30nm Au, channel width
For 2 μm, number of electrodes is 10.
Second step, the high-quality GaTe bodies material for choosing the smooth corrugationless in bulk surface, and along natural cleavage plane by its point
From for polylith.
3rd step, using think high adhesive tape from top layer light, damage less GaTe block materials surface and tear off one piece of thickness
About 6 μm of GaTe thin slices.
4th step, the high adhesive tape of think of with GaTe thin slices repeatedly bonded into separation, until tape surface is no longer bright, success
Adhere to the GaTe lamellas of hundreds of nanometers more intensive of thickness.In order to protect GaTe body material even curfaces, it should make during stripping
GaTe surfaces are fully contacted with tape surface.In adhesive tape separation process, one direction slowly to carry out.
5th step, by the adhesive tape gluing with GaTe lamellas thickness be 0.5 ± 0.03mm PDMS film surface, be used in combination
Gently uniformly the high tape surface of pressing think of makes the high adhesive tape of think of fully be fitted with PDMS to cotton swab.High adhesive tape and PDMS points will be thought rapidly again
From.
6th step, using metallography microscope sem observation PDMS surfaces, choose thinner thickness and uniform two dimension GaTe materials enter
Row is taken pictures, and writes down its approximate location on PDMS surfaces.
7th step, by the two-dimentional GaTe materials of mark by lightly snapping into 300nm SiO to quasi- transfer platform2/Si
Between the source on surface, leakage metal electrode.
8th step, the operation for repeating the 5th step to the 7th step, until completing the structure of remaining nine two dimension GaTe FETs
Build.
9th step, the two-dimentional GaTe FETs that finish will be constructed it is put into rapidly in the silica crucible that internal diameter is 15 ± 1mm,
And pressure in crucible is evacuated to 5 × 10 using vacuum pump assembly-5Pa, and mouth of pot is baked into real sealing with oxyhydrogen flame.
Tenth step, the crucible after sealing is placed in 150 DEG C of cycle annealing stoves and is incubated 100 minutes, then entered in atmosphere
Row cooling, completes annealing process.
The test result for the two-dimentional GaTe FETs that the present embodiment is constructed shows that 6 being capable of normal work, device migration
Rate is up to 3.9cm2V-1s-1, success rate is 60%.
Embodiment 2：
The first step, using traditional photoetching-metallization-stripping technology, in clean 10mm × 10mm 300nm SiO2/
Si substrate surfaces prepare the grid, source electrode, drain electrode of FET, and wherein electrode material is 5nm Ti/30nm Au, channel width
For 5 μm, number of electrodes is 10.
Second step, the high-quality GaTe bodies material for choosing the smooth corrugationless in bulk surface, and along natural cleavage plane by its point
From for polylith.
3rd step, using think high adhesive tape from top layer light, damage less GaTe block materials surface and tear off one piece of thickness
About 8 μm of GaTe thin slices.
4th step, the high adhesive tape of think of with GaTe thin slices repeatedly bonded into separation, until tape surface is no longer bright, success
Adhere to the GaTe lamellas of hundreds of nanometers more intensive of thickness.In order to protect GaTe body material even curfaces, it should make during stripping
GaTe surfaces are fully contacted with tape surface.In adhesive tape separation process, one direction slowly to carry out.
5th step, by the adhesive tape gluing with GaTe lamellas thickness be 0.5 ± 0.03mm PDMS film surface, be used in combination
Gently uniformly the high tape surface of pressing think of makes the high adhesive tape of think of fully be fitted with PDMS to cotton swab.High adhesive tape and PDMS points will be thought rapidly again
From.
6th step, using metallography microscope sem observation PDMS surfaces, choose thinner thickness and uniform two dimension GaTe materials enter
Row is taken pictures, and writes down its approximate location on PDMS surfaces.
7th step, by the two-dimentional GaTe materials of mark by lightly snapping into 300nm SiO to quasi- transfer platform2/Si
Between the source on surface, leakage metal electrode.
8th step, the operation for repeating the 5th step to the 7th step, until completing the structure of remaining nine two dimension GaTe FETs
Build.
9th step, the two-dimentional GaTe FETs that finish will be constructed it is put into rapidly in the silica crucible that internal diameter is 15 ± 1mm,
And pressure in crucible is evacuated to 5 × 10 using vacuum pump assembly-5Pa, and mouth of pot is baked into real sealing with oxyhydrogen flame.
Tenth step, the crucible after sealing is placed in 200 DEG C of cycle annealing stoves and is incubated 120 minutes, then entered in atmosphere
Row cooling, completes annealing process.
The test result for the two-dimentional GaTe FETs that the present embodiment is constructed shows that 9 being capable of normal work, device migration
Rate is up to 4.5cm2V-1s-1, success rate is 90%.
By Fig. 1 it can be seen that, soaking time be 2 hours.
By Fig. 2 it can be seen that, annealing post tensioned unbonded prestressed concrete voltage has very strong regulating power to source-drain current.
Embodiment 3：
The first step, using traditional photoetching-metallization-stripping technology, in clean 10mm × 10mm 300nm SiO2/
Si substrate surfaces prepare the grid, source electrode, drain electrode of FET, and wherein electrode material is 5nm Ti/30nm Au, channel width
For 10 μm, number of electrodes is 10.
Second step, the high-quality GaTe bodies material for choosing the smooth corrugationless in bulk surface, and along natural cleavage plane by its point
From for polylith.
3rd step, using think high adhesive tape from top layer light, damage less GaTe block materials surface and tear off one piece of thickness
About 7 μm of GaTe thin slices.
4th step, the high adhesive tape of think of with GaTe thin slices repeatedly bonded into separation, until tape surface is no longer bright, success
Adhere to the GaTe lamellas of hundreds of nanometers more intensive of thickness.In order to protect GaTe body material even curfaces, it should make during stripping
GaTe surfaces are fully contacted with tape surface.In adhesive tape separation process, one direction slowly to carry out.
5th step, by the adhesive tape gluing with GaTe lamellas thickness be 0.5 ± 0.03mm PDMS film surface, be used in combination
Gently uniformly the high tape surface of pressing think of makes the high adhesive tape of think of fully be fitted with PDMS to cotton swab.High adhesive tape and PDMS points will be thought rapidly again
From.
6th step, using metallography microscope sem observation PDMS surfaces, choose thinner thickness and uniform two dimension GaTe materials enter
Row is taken pictures, and writes down its approximate location on PDMS surfaces.
7th step, by the two-dimentional GaTe materials of mark by lightly snapping into 300nm SiO to quasi- transfer platform2/Si
Between the source on surface, leakage metal electrode.
8th step, the operation for repeating the 5th step to the 7th step, until completing constructing for remaining nine GaTe FET.
9th step, the two-dimentional GaTe FETs that finish will be constructed it is put into rapidly in the silica crucible that internal diameter is 15 ± 1mm,
And pressure in crucible is evacuated to 3 × 10 using vacuum pump assembly-5Pa, and mouth of pot is baked into real sealing with oxyhydrogen flame.
Tenth step, the crucible after sealing is placed in 180 DEG C of cycle annealing stoves and is incubated 140 minutes, then entered in atmosphere
Row cooling, completes annealing process.
The test result for the two-dimentional GaTe FETs that the present embodiment is constructed shows that 8 being capable of normal work, device migration
Rate is up to 3.4cm2V-1s-1, success rate is 80%.
Claims (1)
1. a kind of vacuum annealing method based on two-dimentional telluride gallium material FET, it is characterised in that comprise the following steps：
Step 1: using traditional photoetching-metallization-stripping technology, in clean 10mm × 10mm 300nm SiO2/ Si substrates
Surface prepares the grid, source electrode and drain electrode of FET, and wherein grid, source electrode and the material of drain electrode is 5nm Ti/30nm Au,
Channel width is 2 μm -10 μm；
Step 2: choosing the GaTe materials of the smooth corrugationless in surface, and GaTe materials are separated into polylith along natural cleavage plane；
Step 3: the use of think high adhesive tape to tear off one piece of thickness from GaTe block materials surface being 6-8 μm of GaTe thin slices；
Step 4: the high adhesive tape of think of with GaTe thin slices is repeatedly bonded into separation, until tape surface is no longer bright, successfully adhere to
The GaTe lamellas of hundreds of nanometers intensive of thickness；Should make in order to protect GaTe material even curfaces, during stripping GaTe surfaces with
Think high tape surface fully to contact；Think when high adhesive tape is separated, it is necessary to which one direction is slowly carried out；
Step 5: the high adhesive tape gluing of think of with GaTe lamellas is used in combination on the PDMS film surface that thickness is 0.5 ± 0.03mm
Cotton swab, which uniformly presses the high tape surface of think of, makes the high adhesive tape of think of fully be fitted with PDMS；It is rapid again to separate the high adhesive tape of think of with PDMS；
Step 6: using metallography microscope sem observation PDMS surfaces, choosing two-dimentional GaTe materials in uniform thickness and being taken pictures, and remember
Position of the lower two-dimentional GaTe materials on PDMS surfaces；
Step 7: by the two-dimentional GaTe materials of mark by snapping into 300nm SiO to quasi- transfer platform2The source electrode on/Si surfaces
Between drain electrode；
Step 8: be put into the two-dimentional GaTe FETs that finish are constructed in the silica crucible that internal diameter is 15 ± 1mm, and using true
Empty pump assembly will be evacuated to 10 in silica crucible-5Pa magnitudes, and silica crucible mouthful is baked into real sealing with oxyhydrogen flame；
100-140 minutes are incubated Step 9: the silica crucible after sealing is placed in 150 DEG C of -200 DEG C of cycle annealing stoves, then
Cooled down in atmosphere, complete annealing process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201710235701.7A CN107123599A (en) | 2017-04-12 | 2017-04-12 | Vacuum annealing method based on two-dimentional telluride gallium material FET |
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| CN201710235701.7A CN107123599A (en) | 2017-04-12 | 2017-04-12 | Vacuum annealing method based on two-dimentional telluride gallium material FET |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107994099A (en) * | 2017-11-23 | 2018-05-04 | 西北工业大学 | Based on two-dimentional gallium selenide material field-effect transistor preparation method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103236469A (en) * | 2013-04-22 | 2013-08-07 | 哈尔滨工业大学 | Method for preparing gallium telluride two-dimensional structural material and method for producing flexible transparent two-dimensional structural gallium telluride optical detector |
| CN104528664A (en) * | 2014-12-25 | 2015-04-22 | 西北工业大学 | Preparation method of two-dimensional gallium telluride material |
-
2017
- 2017-04-12 CN CN201710235701.7A patent/CN107123599A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103236469A (en) * | 2013-04-22 | 2013-08-07 | 哈尔滨工业大学 | Method for preparing gallium telluride two-dimensional structural material and method for producing flexible transparent two-dimensional structural gallium telluride optical detector |
| CN104528664A (en) * | 2014-12-25 | 2015-04-22 | 西北工业大学 | Preparation method of two-dimensional gallium telluride material |
Non-Patent Citations (2)
| Title |
|---|
| FUCAI LIU等: "High-Sensitivity Photodetectors Based-on Multilayer GaTe Flakes", 《ACS NANO》 * |
| HAI HUANG等: "Highly sensitive phototransistor based on GaSe nanosheets", 《APPLIED PHYSICS LETTERS》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107994099A (en) * | 2017-11-23 | 2018-05-04 | 西北工业大学 | Based on two-dimentional gallium selenide material field-effect transistor preparation method |
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Application publication date: 20170901 |