CN107112323B

CN107112323B - Integrated semiconductor circuit

Info

Publication number: CN107112323B
Application number: CN201580059120.1A
Authority: CN
Inventors: C·普伦特克; W·冯埃姆登; N·戴维斯
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 2014-10-30
Filing date: 2015-09-18
Publication date: 2021-03-26
Anticipated expiration: 2035-09-18
Also published as: JP2017535079A; DE102014222214A1; CN107112323A; JP6355846B2; WO2016066329A1

Abstract

An integrated semiconductor circuit (1) having a planar substrate (2) is arranged on an insulating layer (3), wherein a semiconductor layer (4) is arranged on the insulating layer (3), wherein the semiconductor layer (4) has at least three sections (5,6,7) directly adjoining one another, wherein the sections (5,6,7) adjoining one another have opposite charge carriers, so that alternately a pn junction or an np junction is formed, wherein the three sections (5,6,7) adjoining one another, when the semiconductor layer (4) is electrically switched on, form a diode (11) in the switching-on direction and a diode (12) in the switching-off direction, wherein a switching-on layer (8) is arranged, for example, on the sections (6,7), which represent the diode (12) in the switching-off direction, so that the diode (12) in the switching-off direction is short-circuited, and a metal layer (9) is arranged on the via layer (8), wherein the metal layer (9) completely covers the via layer (8) and is arranged at least partially at a vertical distance laterally above the three sections (5,6,7) adjacent to each other.

Description

Integrated semiconductor circuit

Technical Field

The invention relates to an integrated semiconductor circuit, a circuit arrangement having at least two integrated semiconductor circuits, and the use of the circuit arrangement for sensing temperature.

Background

In the power output pole (leistungsendlife), for example, a predefined temperature is not allowed to be exceeded for operating the electric motor. The actual temperature of the power module in the environment is unknown due to manufacturing-induced numerical scatter (Streuung) and operating states that could not be determined accurately before. It is therefore known to provide buffer regions in the construction of the power output stage in order to avoid temperature peaks occurring in the power components. The disadvantage here is that additional semiconductor surfaces result in costs and waste of installation space.

A diode is described in document DE 19904575C 1, which acts as a monolithically integrated temperature sensor.

A power semiconductor is described in DE 102011050122 a1, which includes a temperature sensor and is used in a steering system.

Disclosure of Invention

An integrated semiconductor circuit has a planar substrate. An insulating layer is disposed on the planar substrate. A semiconductor layer is disposed on the insulating layer. The semiconductor layer has at least three sections adjoining one another. The sections directly adjoining one another have opposite charge carriers or dopings. Thus, pn-junctions or np-junctions are alternately formed, so that three sections adjoining one another have a diode in the on direction and a diode in the off direction when the semiconductor layer is electrically switched on. The switching layer is arranged locally (breichweise) on the section of the diode representing the blocking direction. The via layer extends in the transverse direction partially over the second and third portions. The turn-on layer shorts the diode in the turn-off direction. A metal layer is disposed on the via layer. The metal layer completely covers the via layer and electrically connects the via layer. The metal layer is arranged laterally at least in places at a vertical distance above the three sections adjoining one another.

The advantage here is that a series circuit of diodes in the direction of conduction can be realized in a simple manner and that the forward voltage and the temperature coefficient can be adjusted with this series circuit as a function of the number of diodes. In addition, it is advantageous that a small drift in the service life of the diode is produced by the partial covering of three mutually adjacent sections by means of a metal layer. Additionally, the metal layer prevents impurities, such as ion diffusion and light incidence, by the covering.

In one embodiment, the semiconductor layer is switched by means of a first switching structure and a second switching structure, the first switching structure being configured as a cathode and the second switching structure being configured as an anode.

In one embodiment, the ratio of the width, which extends parallel to the contact region of the section, to the length, which is defined as the distance between one pn junction and the next pn junction or between one np junction and the next np junction, has at least one value greater than 3.

It is advantageous here that the electrical breakdown strength (durchschlagsfestkeit) is high.

In a further embodiment, the vertical distance of the metal layers corresponds to the layer thickness of the contact layer.

In this case, the advantage is that the field strength at the surface of the semiconductor layer of the integrated semiconductor circuit is small.

In one embodiment, the insulating layer comprises silicon dioxide.

In this case, the semiconductor circuit can advantageously be integrated monolithically in different semiconductor processes, for example a power field effect transistor (PowerMOSFET), an Insulated Gate Bipolar Transistor (IGBT) or an Application Specific Integrated Circuit (ASIC).

The circuit arrangement has at least two integrated semiconductor circuits according to the invention, wherein the at least two integrated semiconductor circuits are arranged at a distance from one another in at least one direction of extension of the substrate on an insulating layer on the planar substrate, wherein the two semiconductor circuits have an opposite doping sequence.

In this case, it is advantageous that the circuit arrangement has a low drift, since the diode can be operated without breaking down.

In one embodiment, a diode in the on-direction and a diode in the off-direction are arranged in the first semiconductor circuit. The diode in the on direction and the diode in the off direction are also arranged in the second semiconductor circuit. The diodes of the first semiconductor circuit arranged in the off direction and the diodes of the second semiconductor circuit arranged in the on direction are electrically connected to a common metal layer. The metal layer is arranged laterally at least in places at a vertical distance above three sections of the semiconductor layers of the two integrated semiconductor circuits, which sections adjoin one another in each case.

In this case, it is advantageous to achieve a uniform voltage distribution across the individual diodes by means of the anti-parallel connection of the diode chain and the connection of the diodes polarized in the blocking direction to the metal layer, since the voltage drop across each individual blocking diode cannot exceed the value of the forward voltage of the diode connected in anti-parallel.

Temperature is sensed using an integrated semiconductor circuit or circuit device. The integrated semiconductor circuit is connected to a voltage source or a current source. A signal is generated when a temperature threshold is exceeded. The temperature threshold can be set in dependence on the forward voltage of the integrated semiconductor circuit or the circuit arrangement. The value of the forward voltage is adjusted according to the number of pn-and np-junctions.

It is advantageous here for the complexity of the system for determining the temperature and the complexity of the balancing to be precise

Low.

In one embodiment, the value of the forward voltage is adjusted as a function of the doping of the n-region or the p-region.

Further advantages result from the following description of the embodiments or from the dependent claims.

Drawings

The invention is elucidated below on the basis of a preferred embodiment and reference numerals. As shown in the drawings, in which,

FIG. 1a is an exemplary turned-on integrated semiconductor circuit having a semiconductor layer with at least three sections and a semiconductor layer;

FIG. 1b is an equivalent circuit diagram of the integrated semiconductor circuit of FIG. 1 a;

FIG. 1c is a cross-sectional view in the x-z plane of the integrated semiconductor circuit of FIG. 1 a;

FIG. 1d shows another embodiment of an integrated semiconductor circuit in which a via layer is arranged below a semiconductor layer;

FIG. 2a shows a circuit arrangement with two integrated semiconductor circuits;

FIG. 2b is an equivalent circuit diagram of the circuit arrangement in FIG. 2 a;

FIG. 3a is a circuit for sensing temperature;

FIG. 3b is an equivalent circuit diagram of the circuit of FIG. 3 a;

FIG. 3c another circuit for sensing temperature with a doped region having a curvilinear configuration;

fig. 3d shows another circuit for sensing temperature with doped regions having a circular configuration.

Detailed Description

Fig. 1a shows an integrated semiconductor circuit 1, which can be connected to further components or voltage or current sources by means of two switching structures 14 and 15. The integrated semiconductor circuit 1 has a planar substrate 2 on which an insulating layer 3 is arranged. A semiconductor layer 4 is arranged on the insulating layer 3, said semiconductor layer having three

sections

5,6 and 7 adjoining one another. The first section 5 and the third section 7 have a first doping. The second section 6 has a second doping. The first doping and the second doping have opposite charge carriers, i.e. the first section 5 and the third section 7 are for example p-doped and the second section is n-doped. The second section 6 is arranged between the first section 5 and the third section 7. Since the first section 5 directly adjoins the second section 6 and the second section 6 directly adjoins the 7 th section, a switching-on region is formed at the section transitions or carrier transitions, which form a pn junction or np junction, due to the opposite carriers of the

sections

5,6 and 7. The region marked with reference numeral 13 in fig. 1a therefore comprises a diode 11 in the on direction and a diode 12 in the off direction, as is shown in the equivalent circuit diagram in fig. 1 b. In order to obtain a high breakdown resistance of the diode, the width of the pn or np junction, which is defined parallel to the pn or np junction, is designed relative to the length of the track region (Bahngebiet) of the segment adjoining the switch-on region in such a way that the ratio of the width to the length has a value of at least 3. A via layer 8 is arranged at least partially above the second section 6 and the third section 7 and electrically connects them. The switching layer 8 therefore shows a common switching of the two

segments

6 and 7, i.e. the switching layer bridges the switching region and therefore shorts the diodes 12 arranged in the blocking direction in the exemplary embodiment. According to the invention, the diode in the blocking direction is always short-circuited. The contact layer 8 is highly doped retrograde (intrinsic) or metallic, forming a low resistance ohmic contact with the second section 6 and with the third section 7. The metal layer 9 is arranged on the via layer 8 and completely covers the via layer 8. The metal layer 9 is connected to the via layer 8. Alternatively, the via layer 8 and the metal layer 9 are formed as one layer. The metal layer 9 is arranged laterally at least in places at a vertical distance above the three

sections

5,6 and 7 and thus protects the area-wise covered semiconductor layer from light incidence and diffusion of impurities. The metal layer 9 has for example highly doped or degenerated n + + -polysilicon or aluminum bronze. The metal layer 9 is optionally formed by a plurality of layers, in particular by a metal layer acting as a barrier, for example titanium, titanium nitride or tungsten. The insulating layer 3 comprises silicon dioxide, Tetraethylorthosilicate (TEOS), or BSPG. Instead, the insulating layer 3 comprises silicon nitride. The planar substrate 2 comprises silicon, polysilicon or other semiconductor material. The switch-on structure 14 is configured as a cathode and the switch-on structure 15 is configured as an anode. The segments of the switch-on structures 14 and 15 have opposite charge carriers. The electrical contacting is effected by means of a contact layer, wherein the contact layer is arranged on the respective section and not on the transition. The cathode 17 in the equivalent circuit diagram in fig. 1b is therefore directly connected to the

diodes

11 and 12. Since a further section transition is required for the formation of the anode 16, the process produces the diode 18 in the conducting direction in a defined manner.

In one embodiment, the via layer 8 is configured as a via. The metallization of the via and the metal layer 9 can thus be configured as one layer.

In a further embodiment, the track resistance (bahnwinderstand) and/or the temperature coefficient of resistance of the three

sections

5,6 and 7 are substantially equally large by means of the geometry.

In another embodiment, the semiconductor layer 4 has a plurality of sections adjoining one another. In this case, the sections directly adjoining one another have opposite charge carriers. This results in a plurality of pn or np junctions. If the outer section or the contact structure of the semiconductor layer 4 is connected to a voltage or current source, a surface optimization of the diode in the on-direction or the diode in the off-direction results

I.e. a diode chain. Since the diode process in the blocking direction occurs in a defined manner, the diode must be shorted for the purpose of temperature sensing. This is achieved by means of a switching layer, which is arranged, for example, on the section of the diode that generates the blocking direction. In this way, a predefined forward voltage of the integrated semiconductor circuit can be set, from which the temperature can be derived.

In one embodiment, the width and the length of the track region extending parallel to the pn-junction or np-junction are equally large. That is to say that the sections of the semiconductor layer are square.

Fig. 1c shows the integrated semiconductor circuit in a cross-sectional view in the x-z plane. The vertical distance of the metal layer 9 with respect to the semiconductor layer 2 corresponds to the layer thickness of the via layer 8 or the depth of the via etching.

Fig. 1d shows an embodiment in which the via layer 8 is arranged below the semiconductor layer 4. The switching layer 8 also short-circuits the diode in the blocking direction. A metal layer 9 is arranged below the via layer 8. The metal layer 9 and the via layer 8 are each surrounded by an insulating layer.

Fig. 2a shows a circuit arrangement with two integrated semiconductor circuits 31 and 32. Fig. 2b shows an equivalent circuit diagram belonging to the circuit arrangement. In the following sections reference is made to two figures 2a and ab. The circuit arrangement 30 is provided with switch-on structures 41 and 42, which switch on the diode chain. In this case, a diode in the conducting direction is produced in the first semiconductor circuit 31 at the anode connection 42 or 46, and a diode in the conducting direction is produced in the second semiconductor circuit 32 at the cathode connection 41 or 45. The circuit arrangement 30 comprises two semiconductor layers, each of which comprises three sections. The two semiconductor layers are arranged spaced apart in the y-direction on the insulating layer 33 of the planar substrate 44. The first semiconductor layer has a diode 40 in the on direction and a diode 39 in the off direction. The second semiconductor layer has a diode 37 in the off direction and a diode 38 in the on direction. In the first semiconductor layer and the second semiconductor layer,

diodes

37 and 39 in the blocking direction are short-circuited by means of the turn-on layer 34 or 35, respectively. A common metal layer 36 is arranged on the contact layers 34 and 35, said common metal layer completely covering the contact layers 34 and 35 and being electrically contacted. The metal layer 36 has a vertical distance with respect to the first semiconductor layer and the second semiconductor layer, and is locally arranged over three sections of the semiconductor layer. The metal layer 36 serves both for electrical contact and for shielding from the incident light or diffusion of impurities. The metal layer 36 is shown in fig. 2b as a connection 43.

Figure 3a shows a circuit for sensing temperature in the form of a top view of the x-y plane of the circuit. The top view shows a possible layout of the circuit. Each diode chain shows 5 diodes respectively. The first semiconductor layer 31.1 is arranged parallel to the second semiconductor layer 32.1 on the insulating layer 3.1. The first semiconductor layer 31.1 and the second semiconductor layer 32.1 alternately have p-doped regions 6.1 and n-doped regions 5.1, wherein regions of the same charge carriers are opposite. The diode in the blocking direction of the first semiconductor layer 31.1 and the diode in the blocking direction of the second semiconductor layer 32.1 are short-circuited by means of the connection layer 8.1. The metal layer 9.1 is arranged above three mutually adjoining sections of the first semiconductor layer 31.1 and the second semiconductor layer 32.1, respectively, so that the metal layer 9.1 forms, for example, a rectangle. In the region of the connections with the anode or cathode, the metal layer 9.1 has another shape.

Fig. 3b shows an associated equivalent circuit diagram 50. The equivalent circuit diagram 50 has a first diode chain 53 and an antiparallel-connected second diode chain 54. The connection terminal 51 serves as a cathode and the connection terminal 52 serves as an anode. In addition, the blocking diodes of first diode chain 53 are electrically connected to the blocking diodes of second diode chain 54, wherein the blocking diodes are opposite one another.

Fig. 3c shows another configuration of the circuit for sensing temperature with the same equivalent circuit diagram of fig. 3 b. In this case, the doped semiconductor regions 5.2 and 6.2, the via layer 8.2 and the metal layer 9.2 are arranged in a wave-like manner above the insulating layer 3. Alternatively, the geometry of the pn or np junction is curved or waved in order to enlarge the effective pn width profile of the diode.

Fig. 3d shows a further embodiment of a circuit for sensing temperature, in which insulating layer 3.3, doped semiconductor regions 5.3 and 6.3, via layer 8.3 and metal layer 9.3 are arranged in a circular manner.

The circuits of fig. 3a, 3b, 3c and 3d are suitable for sensing temperature due to the temperature dependence of the forward voltage of the diode. By means of the circuit, the temperature coefficient of the diode string can be determined. For this purpose, the cathode terminal in the power semiconductor is connected, for example, to the source, emitter or ground (master). If a current is fed to the anode connection, a temperature-dependent forward voltage of the diode polarized in the conduction direction can be determined. The temperature of the power component, in which the circuit can be integrated, can also be determined from the temperature-dependent forward voltage. The forward voltage is related to the emission factor, thermal voltage, forward current, saturation current, and series or track resistance. In order to produce the most linear possible relationship between forward voltage, saturation current and temperature, the temperature dependence of the emission factor and the series resistance must be reduced. Reducing the emission factor by: the doping concentration is set in the regions with opposite carriers in such a way that the regions with opposite carriers have substantially the same resistance. Thereby reducing the total resistance or track resistance. The overall series resistance is additionally reduced by the high side ratio, since the length of the track region is thereby maximally shortened in the current direction, and the width of the pn junction is increased. In addition to the geometric layout of the circuit arrangement and the doping of the p-and n-regions, the distributed vias also serve to reduce the track resistance, since the semiconductor layer underneath the vias is connected in a low-resistance manner. Thus, the forward voltage is substantially linearly related to temperature. By means of the arrangement or connection of the diodes, the blocking voltage of each individual diode is limited to the forward voltage of the diode connected in anti-parallel thereto. Reading of the forward voltage can be achieved in both directions. The circuit may be integrated in a power field effect transistor, an insulated gate bipolar transistor or an application specific integrated circuit, for example.

Claims

1. An integrated semiconductor circuit (1) having a planar substrate (2) on which an insulating layer (3) is arranged, wherein a semiconductor layer (4) is arranged on the insulating layer (3), wherein the semiconductor layer (4) has at least three sections (5,6,7) directly adjoining one another, wherein the sections (5,6,7) directly adjoining one another have opposite charge carriers, so that pn or np junctions are formed alternately, wherein, when the semiconductor layer (4) is electrically switched on, the three sections (5,6,7) directly adjoining one another form a diode (11) in the switching-on direction and a diode (12) in the switching-off direction, wherein a switching-on layer (8) is arranged locally on the sections (6,7) representing the diode (12) in the switching-off direction, so that the diode (12) in the switching-off direction is shorted, and a metal layer (9) is arranged on the via layer (8), wherein the metal layer (9) completely covers the via layer (8) and is arranged at least partially laterally at a vertical distance above the three directly adjacent sections (5,6,7), wherein the vertical distance of the metal layer (9) relative to the semiconductor layer (4) corresponds to the layer thickness of the via layer (8).

2. Integrated semiconductor circuit (1) according to claim 1, characterized in that the switching-on of the semiconductor layer (4) is effected by means of a first switching-on structure (14) and a second switching-on structure (15), wherein the first switching-on structure (14) is configured as a cathode and the second switching-on structure (15) is configured as an anode.

3. Integrated semiconductor circuit (1) according to claim 1 or 2, characterized in that the ratio of the width of the section (6) to the length, which length is defined as the distance between one pn-junction and the next, has at least one value greater than 3, wherein the width extends parallel to the turn-on region (10) of the section (5, 6).

4. Integrated semiconductor circuit (1) according to claim 1 or 2, characterized in that the insulating layer (3) has silicon dioxide.

5. A circuit arrangement (30) with at least two integrated semiconductor circuits according to one of the preceding claims, characterized in that the at least two integrated semiconductor circuits are arranged on an insulating layer (33) on a planar substrate (44) at a distance from one another in at least one substrate extension direction, wherein the two semiconductor circuits (31, 32) have opposite doping orders.

6. A circuit arrangement (30) as claimed in claim 5, wherein a diode (39) in the on-direction and a diode (40) in the off-direction of the first semiconductor circuit (31) and a diode (38) in the on-direction and a diode (37) in the off-direction of the second semiconductor circuit (32) are arranged in each case, wherein the diodes (37, 40) in the off-direction are electrically connected to a common metal layer (36), wherein the metal layer (36) is arranged laterally at least in places at a vertical distance on in each case three directly adjoining sections of the semiconductor layers of the two integrated semiconductor circuits.

7. Use of an integrated semiconductor circuit (1) according to one of claims 1 to 4 or of a circuit arrangement (30) according to one of claims 5 or 6 for sensing a temperature, wherein the integrated semiconductor circuit (1) or the circuit arrangement (30) is connected to a voltage or current source, wherein a signal is generated when a temperature threshold value is exceeded, wherein the temperature threshold value can be adjusted depending on a forward voltage of the integrated semiconductor circuit (1) or circuit arrangement (30), wherein the value of the forward voltage is adjusted depending on the number of pn junctions or np junctions.

8. Use according to claim 7, wherein the value of the forward voltage is adjusted depending on the doping of the n-region or p-region of the pn-or np-junction.