CN107112323A - Integrated semiconductor circuit - Google Patents
Integrated semiconductor circuit Download PDFInfo
- Publication number
- CN107112323A CN107112323A CN201580059120.1A CN201580059120A CN107112323A CN 107112323 A CN107112323 A CN 107112323A CN 201580059120 A CN201580059120 A CN 201580059120A CN 107112323 A CN107112323 A CN 107112323A
- Authority
- CN
- China
- Prior art keywords
- diode
- circuit
- layer
- section
- integrated semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
Abstract
Arranged with planar substrate (2) integrated semiconductor circuit (1) on insulating barrier (3), wherein, semiconductor layer (4) is arranged on the insulating barrier (3), wherein, the semiconductor layer (4) has at least three direct sections (5 adjacent to each other, 6, 7), wherein, the section (5 adjacent to each other, 6, 7) there is opposite carrier, so as to which alternately construction pn-junction or np are tied, wherein, when the semiconductor layer (4) is electrically connected, described three sections (5 adjacent to each other, 6, 7) diode (12) on the diode (11) and cut-off direction on construction conducting direction, wherein, layer (8) is connected for example in the section (6, 7) arranged on, the section represents the diode (12) on the cut-off direction, so as to diode (12) short circuit on the cut-off direction, and metal level (9) is arranged on the connection layer (8), wherein, the connection layer (8) is completely covered and at least partially with a vertical range laterally in described three sections (5 adjacent to each other in the metal level (9), 6, 7) arrange above.
Description
Technical field
Filled the present invention relates to a kind of integrated semiconductor circuit, a kind of circuit with least two integrated semiconductor circuits
Put and with the circuit arrangement come the purposes of sensing temperature.
Background technology
In power output pole (Leistungsendstufe), for service meter, for example, do not allow more than predetermined
Temperature.Because numerical value disperses (Streuung) and the running status that cannot accurately determine before, power packages caused by manufacture
Actual temperature is unknown to part in the environment.Therefore, it is known that buffer area is set in the structure of power output stage, to keep away
Exempt from the temperature peak occurred in (PCC) power.Herein disadvantageously, produced by additional semiconductor surface and spend and waste knot
Conformational space.
The diode described in the C1 of document DE 19904575, it serves as single chip integrated temperature sensor.
The power semiconductor described in the A1 of document DE 102011050122, the power semiconductor includes temperature sensor
And use in the steering system.
The content of the invention
Integrated semiconductor circuit has planar substrate.Insulating barrier is arranged on a planar substrate.Arrange and partly lead on the insulating layer
Body layer.Semiconductor layer has at least three sections adjacent to each other.Directly section adjacent to each other have opposite carrier or
Doping.Thus, pn-junction or np knots are alternately formed, so that when semiconductor layer is electrically connected, three sections adjacent to each other have
The diode on diode and cut-off direction on conducting direction.Connecting layer, partly (breichweise) is arranged in representative section
Only on the section of the diode on direction.Partly extend in the horizontal on the second section and the 3rd section here, connecting layer.
Connecting layer makes the diode short circuit on cut-off direction.Metal level is arranged on layer is connected.Metal level be completely covered connection layer and
Layer is connected in electrical connection.Metal level is laterally at least partially arranged in above three sections adjacent to each other with a vertical range.
Here, advantage is, the series circuit of the diode on conducting direction can be realized with simple mode, and can be with
Forward voltage and temperature coefficient are adjusted according to the quantity of diode with the series circuit.It is moreover advantageous that by by metal
The less service life that layer partly covers three sections adjacent to each other and produces diode is drifted about.Additionally, metal level
Impurity is prevented by the covering --- for example ion diffusion and light are incident.
In a kind of expansion scheme, the connection of semiconductor layer is realized by the first engaging structure and the second engaging structure, its
In, the first engaging structure is configured as negative electrode and the second engaging structure is configured as anode.
In a kind of expansion scheme, the ratio of width and length has the value that at least one is more than 3, wherein the width with
The connection region of section is extended parallel to, the length be defined as between a pn-junction and next pn-junction or np knot with it is next
The distance between np knots.
Herein advantageously, electric resistance to breakdown strength (Durchschlagsfestigkeit) is high.
In another configuration, the vertical range of metal level is corresponding to the thickness degree for connecting layer.
Here, advantage is, the field strength on the surface of the semiconductor layer of integrated semiconductor circuit is small.
In a kind of expansion scheme, insulating barrier has silica.
Herein, it is advantageous to which semiconductor circuit can be monolithically integrated in different semiconductor technologies, such as power field
Effect transistor (PowerMOSFET), insulated gate bipolar transistor (IGBT) or application specific integrated circuit (ASIC).
Circuit arrangement has at least two according to the integrated semiconductor circuits of the present invention, wherein, at least two integrated partly lead
Body circuit at least one substrate bearing of trend each other with a distance arrangement insulating barrier on a planar substrate, wherein, two
Individual semiconductor circuit has opposite doping-sequence.
Here, advantage is, circuit arrangement has low drifting, because can not run diode to puncturing.
In a kind of expansion scheme, arranged in the first semiconductor circuit on the diode on conducting direction and cut-off direction
Diode.The diode on diode and cut-off direction in the second semiconductor circuit on same arrangement conducting direction.The
The diode arranged on cut-off direction of semiconductor circuit and arranged on conducting direction the two of the second semiconductor circuit
Pole pipe is electrically connected with common metal level.Metal level is at least partially transversely disposed on two with a vertical range and integrated partly led
Above the difference three of the semiconductor layer of body circuit section adjacent to each other.
Herein advantageously, the diode polarized by the reverse parallel connection circuit of diode chain and on cut-off direction with
The uniform voltage's distribiuting on single diode is realized in the connection of metal level, because the voltage drop on each single hold-off diode
The value of the forward voltage of its diode being connected in antiparallel cannot be exceeded.
Carry out sensing temperature using integrated semiconductor circuit or circuit arrangement.Here, integrated semiconductor circuit and voltage source or
Current source is connected.Signal is produced when more than temperature threshold.Here, can be according to integrated semiconductor circuit or circuit arrangement just
To voltage-regulation temperature threshold.The value of forward voltage is adjusted according to pn-junction and the np quantity tied.
Herein advantageously, the system complexity and balance complexity for temperature
It is low.
In a kind of expansion scheme, the value of forward voltage is adjusted according to the doping in n areas or p areas.
Other advantages are drawn by the description below of embodiment or by category claims.
Brief description of the drawings
The present invention is illustrated below according to preferred embodiment and reference.Accompanying drawing shows,
A kind of integrated semiconductor circuits of the exemplary connection with semiconductor layer and semiconductor layer of Fig. 1 a, the semiconductor
Layer has at least three sections；
The equivalent circuit diagram of integrated semiconductor circuit in Fig. 1 b Fig. 1 a；
The profile of the x-z-plane of integrated semiconductor circuit in Fig. 1 c Fig. 1 a；
Another embodiment of Fig. 1 d integrated semiconductor circuits, in the semiconductor circuit, connection layer, which is arranged in, partly leads
Under body layer；
Fig. 2 a have the circuit arrangement of two integrated semiconductor circuits；
The equivalent circuit diagram of circuit arrangement in Fig. 2 b Fig. 2 a；
Fig. 3 a are used for the circuit of sensing temperature；
The equivalent circuit diagram of circuit in Fig. 3 b Fig. 3 a；
Fig. 3 c are used for another circuit of the doped region with shaped form configuration of sensing temperature；
Fig. 3 d are used for another circuit of the doped region with circular in configuration of sensing temperature.
Embodiment
Fig. 1 a show integrated semiconductor circuit 1, and the semiconductor circuit can be by two engaging structures 14 and 15 and its
His component or the connection of voltage source or current source.Integrated semiconductor circuit 1 has planar substrate 2, is arranged in the planar substrate
Insulating barrier 3.Semiconductor layer 4 arranges that on the insulating layer 3 the semiconductor layer has three sections 5,6 and 7 adjacent to each other.The
One section 5 and the 3rd section 7 have the first doping.Second section 6 has the second doping.First doping and second is doped with phase
Anti- carrier, i.e. the first section 5 and the 3rd section 7 are, for example, p doping and the second section is n doping.Second section 6 is
Arranged between one section 5 and the 3rd section 7.Because the first section 5 abuts directly against the second section 6 and the second section 6 is directly adjacent
The 7th section is connect, because the opposite carrier of section 5,6 and 7 is in section transition or carrier transition --- the section transition
Or carrier transition forms pn-junction or np knots --- place, which is formed, connects region.Therefore, marked in fig 1 a with reference marker 13
Region includes the diode 12 on diode 11 and cut-off direction on conducting direction, such as institute in equivalent circuit diagram in Figure 1b
As showing.In order to obtain the high resistance to sparking of diode, pn-junction or np knots width --- the width is defined as and pn
Knot or np balance row --- and the length relative to the adjacent orbital region (Bahngebiet) for connecting region of section is so designed that,
So that width and the ratio of length have at least 3 value.Connection layer 8 is at least partially on the second section 6 and the 3rd section 7
Face is arranged, and electrically connects them.Therefore, the common connection that layer 8 shows two sections 6 and 7 is connected, that is, connects layer and connects
The short circuit of diode 12 that logical region and therefore making in the described embodiment is arranged on cut-off direction.Always made according to the present invention
Diode short circuit on cut-off direction.Connect layer 8 be highly doped degeneration (entartet) or metal so that formed with
Second section 6 and with low-resistance Ohmic contact of the 3rd section 7.Metal level 9 is arranged and is completely covered on layer 8 is connected and connects
Logical layer 8.Metal level 9 connects layer 8.Alternatively, connect layer 8 and metal level 9 is configured as a layer.Metal level 9 is at least local
Ground is transversely disposed on three tops of section 5,6 and 7 and the semiconductor layer for therefore preventing region-type from covering with a vertical range
Spread by light incidence and impurity.Metal level 9 is for example with highly doped or degeneration n++- polysilicons or copper aluminium.Metal
Layer 9 is alternatively formed by multiple layers, is especially formed by the metal level for serving as potential barrier, for example titanium, titanium nitride or tungsten.Insulating barrier 3 is wrapped
Include silica, tetraethyl orthosilicate (TEOS) or BSPG.Instead, insulating barrier 3 includes silicon nitride.Planar substrate 2 includes silicon, many
Crystal silicon or other semi-conducting materials.Engaging structure 14 is configured as negative electrode and engaging structure 15 is configured as anode.Engaging structure 14
Section with 15 has opposite carrier.Electrically connected by layer realization is connected, wherein, connection layer is arranged on each section
Without in the transition.Therefore, the negative electrode 17 in the equivalent circuit diagram in Fig. 1 b is directly connected with diode 11 and 12.Cause
Another section transition to be needed in order to construct anode 16, so technique limits the diode 18 on ground generation conducting direction.
In one embodiment, layer 8 is connected to be configured as connecting hole.Therefore metallization and the metal level 9 in hole can be will turn on
It is configured as a layer.
In another embodiment, pass through geometric configuration, the track resistance (Bahnwiderstand) of three sections 5,6 and 7
And/or temperature-coefficient of electrical resistance is substantially identical big.
In another embodiment, semiconductor layer 4 has multiple sections adjacent to each other.Here, directly adjacent to each other
Section has opposite carrier.Thus multiple pn-junctions or np knots are drawn.If the section of the outside of semiconductor layer 4 connects knot
Structure is connected with voltage source or current source, draws the face optimization of the diode on conducting direction or the diode on cut-off directionSeries circuit, i.e. diode chain.Occur because ending the diode technique on direction and limiting ground,
Necessary for sensing temperature purposes and short circuit diode.This realizes that the connection layer is for example arranged in generation by layer is connected
On the section for ending the diode on direction.It is possible thereby to the predetermined forward voltage of integrated semiconductor circuit be adjusted, from institute
Temperature can be exported by stating in forward voltage.
In one embodiment, the width and length parallel to pn-junction or np junction spreadings of orbital region are equally big.
That is the section of semiconductor layer is square.
Fig. 1 c illustrate integrated semiconductor circuit with the section of x-z-plane.Metal level 9 is vertical relative to semiconductor layer 2
Distance corresponds to the thickness degree for connecting layer 8 or the depth for connecing via etch.
Fig. 1 d show a kind of embodiment, in the described embodiment, connect layer 8 and are arranged under semiconductor layer 4.Connect layer 8
Make the diode short circuit on cut-off direction herein.Metal level 9 is arranged under connection layer 8.Metal level 9 with connect layer 8 all respectively by
Insulating barrier is surrounded.
Fig. 2 a show the circuit arrangement with two integrated semiconductor circuits 31 and 32.Fig. 2 b places of showing belong to the circuit dress
The equivalent circuit diagram put.With reference to two Fig. 2 a and ab in lower curtate.Circuit arrangement 30 is provided with engaging structure 41 and 42, described
Engaging structure connects diode chain.Here, conducting side is produced at anode connection portion 42 or 46 in the first semiconductor circuit 31
Upward diode, and in two poles at negative electrode connection portion 41 or 45 on generation conducting direction in the second semiconductor circuit 32
Pipe.Here, circuit arrangement 30 includes two semiconductor layers, described two semiconductor layers include three sections respectively.Two and half lead
Body layer is arranged at interval on the insulating barrier 33 of planar substrate 44 in y-direction.First semiconductor layer has on conducting direction
Diode 40 and cut-off direction on diode 39.Second semiconductor layer has diode 37 and conducting side on cut-off direction
Upward diode 38.In the first semiconductor layer and the second semiconductor layer, make cut-off direction respectively by layer 34 or 35 is connected
On the short circuit of diode 37 and 39.Common metal level 36 is arranged on connection layer 34 and 35, and the common metal level is complete
Covering is connected layer 34 and 35 and electrically connected.Metal level 36 has vertical relative to the first semiconductor layer and the second semiconductor layer
Distance, and be partially disposed above three sections of semiconductor layer.Metal level 36 not only be used for electrically connect again be used for shield into
Penetrate the diffusion of light or impurity.Metal level 36 is shown as connecting portion 43 in figure 2b.
Fig. 3 a show the circuit for sensing temperature in the form of the top view of the x-y plane of circuit.Vertical view illustrates electricity
The possible layout on road.5 diodes are shown respectively in each diode chain.First semiconductor layer 31.1 is parallel to the second semiconductor
32.1 ground of layer are arranged on insulating barrier 3.1.First semiconductor layer 31.1 and the second semiconductor layer 32.1 alternately have p doped regions
Section 6.1 and n doping sections 5.1, wherein, the section of identical carrier is opposed.Make the first semiconductor layer 31.1 by layer 8.1 is connected
Cut-off direction on diode and the second semiconductor layer 32.1 cut-off direction on diode short circuit.Metal level 9.1 is distinguished
Above three sections adjacent to each other for being arranged in the first semiconductor layer 31.1 and the second semiconductor layer 32.1, so that metal level
9.1 for example form rectangle.In the region in the connection portion with male or female, metal level 9.1 has other shapes.
Fig. 3 b show affiliated equivalent circuit Figure 50.There is equivalent circuit Figure 50 the first diode chain 53 and reverse parallel connection to connect
The second diode chain 54 connect.Connection end 51 serves as negative electrode and anode is served as in connection end 52.Additionally, the first diode chain 53
Hold-off diode electrically connected with the hold-off diode of the second diode chain 54, wherein, affiliated hold-off diode is opposed.
Fig. 3 c show another configuration of the circuit with equivalent circuit diagram same in Fig. 3 b for sensing temperature.
This, the semiconductor section 5.2 of doping with 6.2, be arranged in the top of insulating barrier 3 with connecting layer 8.2 and the waveform of metal level 9.2.Can
The geometry of selection of land, pn-junction or np knots is shaped form or waveform for the effective pn width configurations for expanding diode.
Fig. 3 d show another configuration of the circuit for sensing temperature, in the configuration, insulating barrier 3.3, doping half
Conductor section 5.3 with 6.3, connect layer 8.3 and metal level 9.3 is circularly arranged.
Fig. 3 a, 3b, 3c and 3d circuit are suitable for sensing temperature due to the temperature dependency of the forward voltage of diode.
By the circuit, it may be determined that the temperature coefficient of diode chain.Therefore, cathode connection terminal in power semiconductor for example with source
Pole, emitter-base bandgap grading or ground (Masse) connection.If to anode connection end feed-in electric current, two polarized on conducting direction can be determined
The related forward voltage of the temperature of pole pipe.(PCC) power can also be determined by the related forward voltage of temperature --- in the power
Can be with integrated circuit in component --- temperature.Forward voltage and Emission Factor, thermal voltage, forward current, saturation current and string
Join resistance or track resistance is relevant., must in order to produce the linear relationship as far as possible between forward voltage, saturation current and temperature
The temperature dependency of Emission Factor and series resistance must be reduced.Reduce Emission Factor in the following manner：With opposite current-carrying
The concentration that so regulation is adulterated in the region of son, so that the region with opposite carrier has substantially the same resistance.By
This reduces all-in resistance or track resistance.Additionally by high side than reducing total series resistance, because thus along electric current side
To the length of maximally shortening orbital region, and improve the width of pn-junction.Except the geometric programming of circuit arrangement and p areas and n areas
Doping beyond, the connection portion of distribution is also used for reducing track resistance, because the semiconductor layer low resistance below connection portion
Bridging.Therefore, forward voltage is substantially related to temperature linearity.Arrangement or connection by diode, each two single poles
The forward voltage for the diode that the blanking voltage gauge of pipe is connected in antiparallel to it.It can realize in the two directions to forward direction
The reading of voltage.The circuit for example can be in power field effect transistor, insulated gate bipolar transistor or special integrated electricity
It is integrated in road.
Claims (9)
1. a kind of integrated semiconductor circuit (1), it has planar substrate (2), and insulating barrier (3) is disposed with the planar substrate
On, wherein, semiconductor layer (4) is disposed with the insulating barrier (3), wherein, the semiconductor layer (4) is straight with least three
Section (5,6,7) adjacent to each other is connect, wherein, the section (5,6,7) adjacent to each other has opposite carrier, so as to hand over
Pn-junction or np knots are alternately formed, wherein, when the semiconductor layer (4) is electrically connected, described three sections adjacent to each other (5,6,
7) diode (12) formed on the diode (11) on conducting direction and cut-off direction, wherein, connect layer (8) and partly arrange
On the section (6,7) of diode (12) on the cut-off direction is represented, so that the diode (12) on the cut-off direction
Short circuit, and metal level (9) is arranged on connection layer (8), wherein, the connection layer is completely covered in the metal level (9)
(8) and at least partially it is transversely disposed on a vertical range above described three sections (5,6,7) adjacent to each other.
2. integrated semiconductor circuit (1) according to claim 1, it is characterised in that by the first engaging structure (14) and
Second engaging structure (15) realizes the connection of the semiconductor layer (4), wherein, first engaging structure (14) is configured as negative electrode
And second engaging structure (15) is configured as anode.
3. integrated semiconductor circuit (1) according to claim 1 or 2, it is characterised in that the width of the section (6) with
The ratio of length has the value that at least one is more than 3, wherein, the connection region (10) of the width and the section (5,6) is put down
Extend capablely, the length is defined as the distance between a pn-junction and next pn-junction.
4. the integrated semiconductor circuit (1) according to any one of the claims, it is characterised in that the metal level
(9) vertical range relative to the semiconductor layer (4) corresponds to the thickness degree of the connection layer (8).
5. the integrated semiconductor circuit (1) according to any one of the claims, it is characterised in that the insulating barrier
(3) there is silica.
6. a kind of electricity of at least two integrated semiconductor circuits (31,32) with according to any one of the claims
Road device (30), it is characterised in that at least two integrated semiconductor circuit (31,32) is at least one substrate bearing of trend
On be arranged in each other with a distance on the insulating barrier (33) in planar substrate (44), wherein, described two semiconductor circuits (31,
32) there is opposite doping-sequence.
7. circuit arrangement (30) according to claim 6, it is characterised in that be respectively disposed with the first semiconductor circuit (31)
Conducting direction on diode (39) and cut-off direction on diode (40) and the second semiconductor circuit (32) conducting
The diode (37) on diode (38) and cut-off direction on direction, wherein, the diode (37,40) on the cut-off direction
Electrically connected with common metal level (36), wherein, the metal level (36) is at least partially laterally arranged with a vertical range
On three sections adjacent to each other of difference of the semiconductor layer of two integrated semiconductor circuits (31,32).
8. integrated semiconductor circuit (1) according to any one of claim 1 to 5 or according to any in claim 6 or 7
The application of circuit arrangement (30) described in, for sensing temperature, wherein, the integrated semiconductor circuit (1) or the circuit
Device (30) is connected with voltage source or current source, wherein, signal is produced when more than temperature threshold, wherein, institute can be depended on
The forward voltage of integrated semiconductor circuit (1) or circuit arrangement (30) is stated to adjust the temperature threshold, wherein, depending on described
Pn-junction or the quantity of np knots adjust the value of the forward voltage.
9. application according to claim 8, it is characterised in that adjusted depending on the doping in the n areas or p areas it is described just
To the value of voltage.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102014222214.1 | 2014-10-30 | ||
| DE102014222214.1A DE102014222214A1 (en) | 2014-10-30 | 2014-10-30 | Integrated semiconductor circuit |
| PCT/EP2015/071424 WO2016066329A1 (en) | 2014-10-30 | 2015-09-18 | Integrated semiconductor circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107112323A true CN107112323A (en) | 2017-08-29 |
| CN107112323B CN107112323B (en) | 2021-03-26 |
Family
ID=54150411
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201580059120.1A Active CN107112323B (en) | 2014-10-30 | 2015-09-18 | Integrated semiconductor circuit |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP6355846B2 (en) |
| CN (1) | CN107112323B (en) |
| DE (1) | DE102014222214A1 (en) |
| WO (1) | WO2016066329A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111936856A (en) * | 2018-04-06 | 2020-11-13 | Sls生物有限公司 | Novel immunoglobulin E epitope, antibody binding thereto, and kit for analyzing immunoglobulin E in sample comprising same |
| CN117043962A (en) * | 2021-03-17 | 2023-11-10 | 罗姆股份有限公司 | Semiconductor device with a semiconductor device having a plurality of semiconductor chips |
| EP4207284A1 (en) * | 2021-12-31 | 2023-07-05 | Nexperia B.V. | Semiconductor device and bidirectional esd protection device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5500547A (en) * | 1993-12-28 | 1996-03-19 | Nec Corporation | Integrated semiconductor device with temperature sensing circuit and method for operating same |
| JP2000031290A (en) * | 1998-07-10 | 2000-01-28 | Nissan Motor Co Ltd | Semiconductor device |
| US20040084753A1 (en) * | 2002-11-04 | 2004-05-06 | Fruth John R. | Integrated circuit including semiconductor power device and electrically isolated thermal sensor |
| CN1828948A (en) * | 2005-01-14 | 2006-09-06 | 三菱电机株式会社 | Infrared solid-state image pickup apparatus and a production method thereof |
| US20070285856A1 (en) * | 2006-06-12 | 2007-12-13 | Denso Corporation | Semiconductor device having protection diode |
| CN101548401A (en) * | 2006-09-18 | 2009-09-30 | 康奈尔研究基金会股份有限公司 | Self powered sensors with radioisotope source |
| CN102403321A (en) * | 2011-09-30 | 2012-04-04 | 上海新傲科技股份有限公司 | Semiconductor device and preparation method thereof |
| CN102412343A (en) * | 2011-11-30 | 2012-04-11 | 中国科学院半导体研究所 | Manufacturing method of flat-type avalanche diode detector used for detecting single photon |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW463362B (en) * | 1999-01-19 | 2001-11-11 | Seiko Epson Corp | Electrostatic protection circuit and semiconductor integrated circuit using the same |
| DE19904575C1 (en) | 1999-02-04 | 2000-03-30 | Siemens Ag | Temperature-protected semiconductor switch with integrated diode-type temperature sensor |
| JP5560538B2 (en) * | 2008-05-22 | 2014-07-30 | 富士電機株式会社 | Manufacturing method of semiconductor device |
| US8537512B2 (en) * | 2009-02-26 | 2013-09-17 | Freescale Semiconductor, Inc. | ESD protection using isolated diodes |
| JP5439968B2 (en) * | 2009-06-18 | 2014-03-12 | 富士電機株式会社 | Semiconductor device |
| DE102011050122A1 (en) | 2010-12-17 | 2012-06-21 | Zf Lenksysteme Gmbh | Component useful as a circuit breaker for an inverter, comprises a MOSFET having a gate terminal and a source terminal, a first diode for measuring a junction temperature of the MOSFET, and a second diode and/or a third diode |
| JP5990437B2 (en) * | 2012-09-10 | 2016-09-14 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
-
2014
- 2014-10-30 DE DE102014222214.1A patent/DE102014222214A1/en not_active Ceased
-
2015
- 2015-09-18 JP JP2017523821A patent/JP6355846B2/en active Active
- 2015-09-18 CN CN201580059120.1A patent/CN107112323B/en active Active
- 2015-09-18 WO PCT/EP2015/071424 patent/WO2016066329A1/en active Application Filing
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5500547A (en) * | 1993-12-28 | 1996-03-19 | Nec Corporation | Integrated semiconductor device with temperature sensing circuit and method for operating same |
| JP2000031290A (en) * | 1998-07-10 | 2000-01-28 | Nissan Motor Co Ltd | Semiconductor device |
| US20040084753A1 (en) * | 2002-11-04 | 2004-05-06 | Fruth John R. | Integrated circuit including semiconductor power device and electrically isolated thermal sensor |
| CN1828948A (en) * | 2005-01-14 | 2006-09-06 | 三菱电机株式会社 | Infrared solid-state image pickup apparatus and a production method thereof |
| US20070285856A1 (en) * | 2006-06-12 | 2007-12-13 | Denso Corporation | Semiconductor device having protection diode |
| CN101548401A (en) * | 2006-09-18 | 2009-09-30 | 康奈尔研究基金会股份有限公司 | Self powered sensors with radioisotope source |
| CN102403321A (en) * | 2011-09-30 | 2012-04-04 | 上海新傲科技股份有限公司 | Semiconductor device and preparation method thereof |
| CN102412343A (en) * | 2011-11-30 | 2012-04-11 | 中国科学院半导体研究所 | Manufacturing method of flat-type avalanche diode detector used for detecting single photon |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2017535079A (en) | 2017-11-24 |
| DE102014222214A1 (en) | 2016-05-04 |
| JP6355846B2 (en) | 2018-07-11 |
| WO2016066329A1 (en) | 2016-05-06 |
| CN107112323B (en) | 2021-03-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104425484B (en) | The method that semiconductor device and triggering avalanche puncture | |
| CN103545311B (en) | There is the high tension apparatus of parallel resistors | |
| CN103681783B (en) | Manufacturing silicon carbide semiconductor device | |
| KR101792678B1 (en) | Optoelectronic component | |
| CN107086247A (en) | Semiconductor device and its manufacture method and circuit including temperature sensor | |
| CN102403357A (en) | Semiconductor device and method of manufacturing the same | |
| CN107195678B (en) | A kind of superjunction IGBT of carrier storage enhancing | |
| CN107112323A (en) | Integrated semiconductor circuit | |
| CN106252397A (en) | There is the semiconductor device of the emitter efficiency of reduction | |
| CN104103691A (en) | Semiconductor device with compensation regions | |
| US8188568B2 (en) | Semiconductor integrated circuit | |
| CN103325768B (en) | There are integrated power transistor circuit arrangement and the manufacture method thereof of current measuring unit | |
| US20150255629A1 (en) | Semiconductor device | |
| JP6133373B2 (en) | Semiconductor device with sensor potential applied to active region | |
| CN104115275A (en) | Semiconductor device | |
| CN105679836A (en) | Ultra-low-capacitance TVS diode structure and preparation method therefor | |
| CN105144404B (en) | For being not necessarily to the method and structure of physically-isolated more battery unit devices | |
| JP2009176884A (en) | Semiconductor device | |
| CN109148442B (en) | Voltage suppressor and preparation method thereof | |
| CN104106136B (en) | It is used for the semiconductor arrangement of current sensor in power semiconductor | |
| CN105185832A (en) | Ultrahigh voltage isolation structure | |
| US10361184B2 (en) | Semiconductor device | |
| US11810958B2 (en) | Transistor component having gate electrodes and field electrodes | |
| KR101607207B1 (en) | Transient voltage suppressor and manufacturing method thereof | |
| CN208538857U (en) | Power crystal tube elements |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |